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authorQi Zhang <qi.z.zhang@intel.com>2019-03-25 13:44:34 +0800
committerFerruh Yigit <ferruh.yigit@intel.com>2019-03-29 17:25:31 +0100
commitd796d38274d1f70d111a994f4daeda0b012738b0 (patch)
treef13757c62f9c4007bb4c37c6337143cd8fd1f8dd /drivers
parent98afdf10b981334f129d3c98d692239c3ecd5e9a (diff)
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net/ice/base: ensure only valid bits are set
In the ice_aq_set_phy_cfg AQ command, the 16.4 bit is reserved. This patch will make sure that this bit will never be set to 1. Signed-off-by: Chinh T Cao <chinh.t.cao@intel.com> Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com> Reviewed-by: Qiming Yang <qiming.yang@intel.com> Reviewed-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/ice/base/ice_adminq_cmd.h1
-rw-r--r--drivers/net/ice/base/ice_common.c9
2 files changed, 10 insertions, 0 deletions
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index ca3d40c..70cd060 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1327,6 +1327,7 @@ struct ice_aqc_set_phy_cfg_data {
__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
u8 caps;
+#define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0)
#define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
#define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
#define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index f5cbd47..1c381b5 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2351,6 +2351,15 @@ ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport,
if (!cfg)
return ICE_ERR_PARAM;
+ /* Ensure that only valid bits of cfg->caps can be turned on. */
+ if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
+ ice_debug(hw, ICE_DBG_PHY,
+ "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
+ cfg->caps);
+
+ cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
+ }
+
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
desc.params.set_phy.lport_num = lport;
desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);