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authorQi Zhang <qi.z.zhang@intel.com>2019-03-25 13:44:39 +0800
committerFerruh Yigit <ferruh.yigit@intel.com>2019-03-29 17:25:31 +0100
commit995fa411530dd2a7062f1885241f03bf3ee7644e (patch)
treebe23f89816c5f509a55b986a7037809b10a83b3b /drivers
parentfd28d468988ff3b6971a8badca9bb15dfb94ee23 (diff)
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net/ice/base: fix minor issues
1. Fix some problems with filling the HW tables. 2. Fix a logic error in ice_rem_prof_from_list. Fixes: 51d04e4933e3 ("net/ice/base: add flexible pipeline module") Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com> Reviewed-by: Qiming Yang <qiming.yang@intel.com> Reviewed-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/ice/base/ice_flex_pipe.c18
1 files changed, 15 insertions, 3 deletions
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index 8876092..1dd121b 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -2935,9 +2935,11 @@ static void ice_fill_tbl(struct ice_hw *hw, enum ice_block block_id, u32 sid)
while (sect) {
switch (sid) {
+ case ICE_SID_XLT1_SW:
case ICE_SID_XLT1_FD:
case ICE_SID_XLT1_RSS:
case ICE_SID_XLT1_ACL:
+ case ICE_SID_XLT1_PE:
xlt1 = (struct ice_xlt1_section *)sect;
src = xlt1->value;
sect_len = LE16_TO_CPU(xlt1->count) *
@@ -2946,9 +2948,11 @@ static void ice_fill_tbl(struct ice_hw *hw, enum ice_block block_id, u32 sid)
dst_len = hw->blk[block_id].xlt1.count *
sizeof(*hw->blk[block_id].xlt1.t);
break;
+ case ICE_SID_XLT2_SW:
case ICE_SID_XLT2_FD:
case ICE_SID_XLT2_RSS:
case ICE_SID_XLT2_ACL:
+ case ICE_SID_XLT2_PE:
xlt2 = (struct ice_xlt2_section *)sect;
src = (u8 *)xlt2->value;
sect_len = LE16_TO_CPU(xlt2->count) *
@@ -2957,9 +2961,11 @@ static void ice_fill_tbl(struct ice_hw *hw, enum ice_block block_id, u32 sid)
dst_len = hw->blk[block_id].xlt2.count *
sizeof(*hw->blk[block_id].xlt2.t);
break;
+ case ICE_SID_PROFID_TCAM_SW:
case ICE_SID_PROFID_TCAM_FD:
case ICE_SID_PROFID_TCAM_RSS:
case ICE_SID_PROFID_TCAM_ACL:
+ case ICE_SID_PROFID_TCAM_PE:
pid = (struct ice_prof_id_section *)sect;
src = (u8 *)pid->entry;
sect_len = LE16_TO_CPU(pid->count) *
@@ -2968,9 +2974,11 @@ static void ice_fill_tbl(struct ice_hw *hw, enum ice_block block_id, u32 sid)
dst_len = hw->blk[block_id].prof.count *
sizeof(*hw->blk[block_id].prof.t);
break;
+ case ICE_SID_PROFID_REDIR_SW:
case ICE_SID_PROFID_REDIR_FD:
case ICE_SID_PROFID_REDIR_RSS:
case ICE_SID_PROFID_REDIR_ACL:
+ case ICE_SID_PROFID_REDIR_PE:
pr = (struct ice_prof_redir_section *)sect;
src = pr->redir_value;
sect_len = LE16_TO_CPU(pr->count) *
@@ -2979,15 +2987,19 @@ static void ice_fill_tbl(struct ice_hw *hw, enum ice_block block_id, u32 sid)
dst_len = hw->blk[block_id].prof_redir.count *
sizeof(*hw->blk[block_id].prof_redir.t);
break;
+ case ICE_SID_FLD_VEC_SW:
case ICE_SID_FLD_VEC_FD:
case ICE_SID_FLD_VEC_RSS:
case ICE_SID_FLD_VEC_ACL:
+ case ICE_SID_FLD_VEC_PE:
es = (struct ice_sw_fv_section *)sect;
src = (u8 *)es->fv;
sect_len = LE16_TO_CPU(es->count) *
- sizeof(*hw->blk[block_id].prof_redir.t);
+ hw->blk[block_id].es.fvw *
+ sizeof(*hw->blk[block_id].es.t);
dst = (u8 *)hw->blk[block_id].es.t;
dst_len = hw->blk[block_id].es.count *
+ hw->blk[block_id].es.fvw *
sizeof(*hw->blk[block_id].es.t);
break;
default:
@@ -4964,8 +4976,8 @@ ice_rem_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl)
if (status)
goto err_ice_rem_prof_id_flow;
- } else if (ice_find_dup_props_vsig(hw, blk, &copy,
- &vsig)) {
+ } else if (!ice_find_dup_props_vsig(hw, blk, &copy,
+ &vsig)) {
/* found an exact match */
/* add or move VSI to the VSIG that matches */
/* Search for a VSIG with a matching profile