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authorTomasz Duszynski <tdu@semihalf.com>2018-09-25 09:05:05 +0200
committerFerruh Yigit <ferruh.yigit@intel.com>2018-09-28 01:41:03 +0200
commite04ec42af0cbeefc65aa3f114e33c5159403a755 (patch)
tree86bcc7def76ded2cf8cd399d0edc66f3ceb501c3 /drivers/net/mvpp2
parent79ec62028b9ae144e7171642120dd7e6e25fe7f7 (diff)
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net/mvpp2: align with MUSDK 18.09
This patch introduces necessary changes required by MUSDK 18.09 library. * As of MUSDK 18.09, pp2_cookie_t is no longer available. Now RX descriptor cookie is defined as plain u64 so existing cast is no longer valid. * MUSDK 18.09 increased number of available bpools (buffer hw pools) by introducing dma regions support. Update mvpp2 driver accordingly. * replace MV_NET_IP4_F_TOS with MV_NET_IP4_F_DSCP Before this patch, API allowed to configure a classification rule according to IPv4 TOS, which was not supported in classifier. This patch fixes this by using proper field. * use 48 bit address mask We cannot get pointers exceeding 48 bits thus using 48 bit mask for extracting higher IOVA address bits is enough. Signed-off-by: Natalie Samsonov <nsamsono@marvell.com> Signed-off-by: Yuval Caduri <cyuval@marvell.com> Signed-off-by: Tomasz Duszynski <tdu@semihalf.com> Reviewed-by: Shlomi Gridish <sgridish@marvell.com> Reviewed-by: Alan Winkowski <walan@marvell.com> Reviewed-by: Liron Himi <lironh@marvell.com>
Diffstat (limited to 'drivers/net/mvpp2')
-rw-r--r--drivers/net/mvpp2/mrvl_ethdev.c10
-rw-r--r--drivers/net/mvpp2/mrvl_flow.c3
-rw-r--r--drivers/net/mvpp2/mrvl_qos.c2
3 files changed, 7 insertions, 8 deletions
diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c
index 24bd0a5..26497ef 100644
--- a/drivers/net/mvpp2/mrvl_ethdev.c
+++ b/drivers/net/mvpp2/mrvl_ethdev.c
@@ -54,9 +54,7 @@
#define MRVL_ARP_LENGTH 28
#define MRVL_COOKIE_ADDR_INVALID ~0ULL
-
-#define MRVL_COOKIE_HIGH_ADDR_SHIFT (sizeof(pp2_cookie_t) * 8)
-#define MRVL_COOKIE_HIGH_ADDR_MASK (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
+#define MRVL_COOKIE_HIGH_ADDR_MASK 0xffffff0000000000
/** Port Rx offload capabilities */
#define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
@@ -1534,7 +1532,7 @@ mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
entries[i].buff.addr =
rte_mbuf_data_iova_default(mbufs[i]);
- entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
+ entries[i].buff.cookie = (uint64_t)mbufs[i];
entries[i].bpool = bpool;
}
@@ -2170,7 +2168,7 @@ mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
if (unlikely(status != PP2_DESC_ERR_OK)) {
struct pp2_buff_inf binf = {
.addr = rte_mbuf_data_iova_default(mbuf),
- .cookie = (pp2_cookie_t)(uint64_t)mbuf,
+ .cookie = (uint64_t)mbuf,
};
pp2_bpool_put_buff(hif, bpool, &binf);
@@ -2431,7 +2429,7 @@ mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
rte_mbuf_prefetch_part2(pref_pkt_hdr);
}
- sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
+ sq->ent[sq->head].buff.cookie = (uint64_t)mbuf;
sq->ent[sq->head].buff.addr =
rte_mbuf_data_iova_default(mbuf);
sq->ent[sq->head].bpool =
diff --git a/drivers/net/mvpp2/mrvl_flow.c b/drivers/net/mvpp2/mrvl_flow.c
index 065b1aa..ffd1dab 100644
--- a/drivers/net/mvpp2/mrvl_flow.c
+++ b/drivers/net/mvpp2/mrvl_flow.c
@@ -2437,7 +2437,8 @@ mrvl_create_cls_table(struct rte_eth_dev *dev, struct rte_flow *first_flow)
if (first_flow->pattern & F_IP4_TOS) {
key->proto_field[key->num_fields].proto = MV_NET_PROTO_IP4;
- key->proto_field[key->num_fields].field.ipv4 = MV_NET_IP4_F_TOS;
+ key->proto_field[key->num_fields].field.ipv4 =
+ MV_NET_IP4_F_DSCP;
key->key_size += 1;
key->num_fields += 1;
}
diff --git a/drivers/net/mvpp2/mrvl_qos.c b/drivers/net/mvpp2/mrvl_qos.c
index 5d80c3e..7fd9703 100644
--- a/drivers/net/mvpp2/mrvl_qos.c
+++ b/drivers/net/mvpp2/mrvl_qos.c
@@ -654,7 +654,7 @@ setup_tc(struct pp2_ppio_tc_params *param, uint8_t inqs,
struct pp2_ppio_inq_params *inq_params;
param->pkt_offset = MRVL_PKT_OFFS;
- param->pools[0] = bpool;
+ param->pools[0][0] = bpool;
param->default_color = color;
inq_params = rte_zmalloc_socket("inq_params",