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authorViacheslav Ovsiienko <viacheslavo@mellanox.com>2019-09-18 06:54:11 +0000
committerFerruh Yigit <ferruh.yigit@intel.com>2019-10-07 15:00:57 +0200
commit06def9bc4e6cf3836192f8e5a0e939f8e56a5f84 (patch)
tree27b403b2dd017c954e4392a9c4069ad12fdd57e0 /drivers/net/mlx5/mlx5_txq.c
parente289400669d552600c64d3fff1c0798fcf7ae5d0 (diff)
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net/mlx5: fix UAR remap initialization for 32-bit systems
The txq_uar_init() routine uses the uninitialized uar_mmap_offset field in 32-bit configurations due to this field is initialized after txq_uar_init() call. Fixes: 120dc4a7dcd3 ("net/mlx5: remove device register remap") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
Diffstat (limited to 'drivers/net/mlx5/mlx5_txq.c')
-rw-r--r--drivers/net/mlx5/mlx5_txq.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index 81f3b40..2b7d6c0 100644
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -572,7 +572,6 @@ mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx)
txq_ibv->cq = tmpl.cq;
rte_atomic32_inc(&txq_ibv->refcnt);
txq_ctrl->bf_reg = qp.bf.reg;
- txq_uar_init(txq_ctrl);
if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
DRV_LOG(DEBUG, "port %u: uar_mmap_offset 0x%"PRIx64,
@@ -585,6 +584,7 @@ mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx)
rte_errno = EINVAL;
goto error;
}
+ txq_uar_init(txq_ctrl);
LIST_INSERT_HEAD(&priv->txqsibv, txq_ibv, next);
txq_ibv->txq_ctrl = txq_ctrl;
priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;