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authorNĂ©lio Laranjeiro <nelio.laranjeiro@6wind.com>2016-06-24 15:17:45 +0200
committerBruce Richardson <bruce.richardson@intel.com>2016-06-27 16:17:52 +0200
commit0431c40f47021fefd6b2064be1c02596e07f858e (patch)
treef63d95c9edd030660b9445ab5755f3d256205a57 /drivers/net/mlx5/mlx5_defs.h
parent97c784fb1833a77f0158d23b88f80fbdb28e6c9a (diff)
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net/mlx5: remove inline Tx support
Inline TX will be fully managed by the PMD after Verbs is bypassed in the data path. Remove the current code until then. Signed-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com> Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
Diffstat (limited to 'drivers/net/mlx5/mlx5_defs.h')
-rw-r--r--drivers/net/mlx5/mlx5_defs.h5
1 files changed, 0 insertions, 5 deletions
diff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h
index da1c90e..9a19835 100644
--- a/drivers/net/mlx5/mlx5_defs.h
+++ b/drivers/net/mlx5/mlx5_defs.h
@@ -54,11 +54,6 @@
/* RSS Indirection table size. */
#define RSS_INDIRECTION_TABLE_SIZE 256
-/* Maximum size for inline data. */
-#ifndef MLX5_PMD_MAX_INLINE
-#define MLX5_PMD_MAX_INLINE 0
-#endif
-
/*
* Maximum number of cached Memory Pools (MPs) per TX queue. Each RTE MP
* from which buffers are to be transmitted will have to be mapped by this