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| author | Phil Yang <phil.yang@arm.com> | 2018-10-08 17:11:43 +0800 |
|---|---|---|
| committer | Thomas Monjalon <thomas@monjalon.net> | 2018-10-26 18:09:22 +0200 |
| commit | ede56cc18dba2db0d261b15815063394dcb2035a (patch) | |
| tree | 4862f95fdc9515b1e96f21d83ddcccf49239100b /config | |
| parent | b78f32cff94d0fc2a0a6de9a21318d7fb49f394e (diff) | |
| download | dpdk-next-eventdev-ede56cc18dba2db0d261b15815063394dcb2035a.zip dpdk-next-eventdev-ede56cc18dba2db0d261b15815063394dcb2035a.tar.gz dpdk-next-eventdev-ede56cc18dba2db0d261b15815063394dcb2035a.tar.xz | |
config: rename option for C11 memory model
Keep only single config option RTE_USE_C11_MEM_MODEL for C11 memory
model, so all modules can leverage C11 atomic extension by enable this
option.
Signed-off-by: Phil Yang <phil.yang@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Diffstat (limited to 'config')
| -rw-r--r-- | config/arm/meson.build | 2 | ||||
| -rw-r--r-- | config/common_armv8a_linuxapp | 4 | ||||
| -rw-r--r-- | config/common_base | 6 | ||||
| -rw-r--r-- | config/defconfig_arm64-thunderx-linuxapp-gcc | 2 |
4 files changed, 9 insertions, 5 deletions
diff --git a/config/arm/meson.build b/config/arm/meson.build index 94cca49..4b23b39 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -53,7 +53,7 @@ flags_cavium = [ ['RTE_MAX_NUMA_NODES', 2], ['RTE_MAX_LCORE', 96], ['RTE_MAX_VFIO_GROUPS', 128], - ['RTE_RING_USE_C11_MEM_MODEL', false]] + ['RTE_USE_C11_MEM_MODEL', false]] flags_dpaa = [ ['RTE_MACHINE', '"dpaa"'], ['RTE_CACHE_LINE_SIZE', 64], diff --git a/config/common_armv8a_linuxapp b/config/common_armv8a_linuxapp index 111c005..ad88a37 100644 --- a/config/common_armv8a_linuxapp +++ b/config/common_armv8a_linuxapp @@ -17,6 +17,8 @@ CONFIG_RTE_FORCE_INTRINSICS=y # to address minimum DMA alignment across all arm64 implementations. CONFIG_RTE_CACHE_LINE_SIZE=128 +CONFIG_RTE_USE_C11_MEM_MODEL=y + # Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest) # to determine the best threshold in code. Refer to notes in source file # (lib/librte_eal/common/include/arch/arm/rte_memcpy_64.h) for more info. @@ -29,8 +31,6 @@ CONFIG_RTE_ARCH_ARM64_MEMCPY=n #CONFIG_RTE_ARM64_MEMCPY_ALIGN_MASK=0xF #CONFIG_RTE_ARM64_MEMCPY_STRICT_ALIGN=n -CONFIG_RTE_RING_USE_C11_MEM_MODEL=y - CONFIG_RTE_LIBRTE_FM10K_PMD=n CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n CONFIG_RTE_LIBRTE_AVP_PMD=n diff --git a/config/common_base b/config/common_base index be7365e..38beaab 100644 --- a/config/common_base +++ b/config/common_base @@ -56,6 +56,11 @@ CONFIG_RTE_MAJOR_ABI= CONFIG_RTE_CACHE_LINE_SIZE=64 # +# Memory model +# +CONFIG_RTE_USE_C11_MEM_MODEL=n + +# # Compile Environment Abstraction Layer # CONFIG_RTE_LIBRTE_EAL=y @@ -698,7 +703,6 @@ CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=y # Compile librte_ring # CONFIG_RTE_LIBRTE_RING=y -CONFIG_RTE_RING_USE_C11_MEM_MODEL=n # # Compile librte_mempool diff --git a/config/defconfig_arm64-thunderx-linuxapp-gcc b/config/defconfig_arm64-thunderx-linuxapp-gcc index 2bed66c..fd160aa 100644 --- a/config/defconfig_arm64-thunderx-linuxapp-gcc +++ b/config/defconfig_arm64-thunderx-linuxapp-gcc @@ -7,10 +7,10 @@ CONFIG_RTE_MACHINE="thunderx" CONFIG_RTE_CACHE_LINE_SIZE=128 +CONFIG_RTE_USE_C11_MEM_MODEL=n CONFIG_RTE_MAX_NUMA_NODES=2 CONFIG_RTE_MAX_LCORE=96 CONFIG_RTE_MAX_VFIO_GROUPS=128 -CONFIG_RTE_RING_USE_C11_MEM_MODEL=n # # Compile PMD for octeontx sso event device |