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authorJingjing Wu <jingjing.wu@intel.com>2015-11-16 15:08:30 +0800
committerThomas Monjalon <thomas.monjalon@6wind.com>2015-11-23 23:51:14 +0100
commit4522eca1352d8ed7c0823e328e2a68c2ba6459ab (patch)
tree65af97246e797e4161fe675e08700e45087683c7
parent1487a7c6ef10bceedff50cf4736f082fe6c22b29 (diff)
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i40evf: fix write flush
For i40e vf driver, should use I40EVF_WRITE_FLUSH to flush configuration but not I40E_WRITE_FLUSH. This patch fixed this issue. Fixes: be6c228d4da3 (i40evf: support Rx interrupt) Reported-by: Qian Xu <qian.q.xu@intel.com> Signed-off-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Helin Zhang <helin.zhang@intel.com>
-rw-r--r--drivers/net/i40e/i40e_ethdev_vf.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c
index 7ce8687..ea96f85 100644
--- a/drivers/net/i40e/i40e_ethdev_vf.c
+++ b/drivers/net/i40e/i40e_ethdev_vf.c
@@ -1700,7 +1700,7 @@ i40evf_enable_queues_intr(struct rte_eth_dev *dev)
I40E_VFINT_DYN_CTL01,
I40E_VFINT_DYN_CTL01_INTENA_MASK |
I40E_VFINT_DYN_CTL01_CLEARPBA_MASK);
- I40E_WRITE_FLUSH(hw);
+ I40EVF_WRITE_FLUSH(hw);
return;
}
@@ -1716,7 +1716,7 @@ i40evf_enable_queues_intr(struct rte_eth_dev *dev)
I40E_VFINT_DYN_CTL01_INTENA_MASK |
I40E_VFINT_DYN_CTL01_CLEARPBA_MASK);
- I40E_WRITE_FLUSH(hw);
+ I40EVF_WRITE_FLUSH(hw);
}
static inline void
@@ -1728,7 +1728,7 @@ i40evf_disable_queues_intr(struct rte_eth_dev *dev)
if (!rte_intr_allow_others(intr_handle)) {
I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
- I40E_WRITE_FLUSH(hw);
+ I40EVF_WRITE_FLUSH(hw);
return;
}
@@ -1740,7 +1740,7 @@ i40evf_disable_queues_intr(struct rte_eth_dev *dev)
else
I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
- I40E_WRITE_FLUSH(hw);
+ I40EVF_WRITE_FLUSH(hw);
}
static int
@@ -1770,7 +1770,7 @@ i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
(interval <<
I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
- I40E_WRITE_FLUSH(hw);
+ I40EVF_WRITE_FLUSH(hw);
rte_intr_enable(&dev->pci_dev->intr_handle);
@@ -1793,7 +1793,7 @@ i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
I40E_RX_VEC_START),
0);
- I40E_WRITE_FLUSH(hw);
+ I40EVF_WRITE_FLUSH(hw);
return 0;
}