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authorGavin Hu <gavin.hu@arm.com>2018-12-11 11:55:50 +0800
committerThomas Monjalon <thomas@monjalon.net>2018-12-19 00:28:00 +0100
commit592a13c9e6739b07e6657def5df5cd1e7abe2423 (patch)
tree1282350355974746f6fa5c70f6c47f7af1be74a1 /config
parent77a83d10afbb5ca5858a8de28c59a76cc9cc37fc (diff)
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config: enable C11 memory model for armv8 with meson
This patch makes the configuration based on makefile and the configuration based on meson to be the same. Fixes: c6e536e38437 ("build: add more implementers IDs and PNs for ARM") Cc: stable@dpdk.org Signed-off-by: Gavin Hu <gavin.hu@arm.com> Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com> Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Diffstat (limited to 'config')
-rw-r--r--config/arm/meson.build3
1 files changed, 3 insertions, 0 deletions
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 3f91725..dae55d6 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -47,6 +47,7 @@ flags_common_default = [
flags_generic = [
['RTE_MACHINE', '"armv8a"'],
['RTE_MAX_LCORE', 256],
+ ['RTE_USE_C11_MEM_MODEL', true],
['RTE_CACHE_LINE_SIZE', 128]]
flags_cavium = [
['RTE_MACHINE', '"thunderx"'],
@@ -57,11 +58,13 @@ flags_cavium = [
['RTE_USE_C11_MEM_MODEL', false]]
flags_dpaa = [
['RTE_MACHINE', '"dpaa"'],
+ ['RTE_USE_C11_MEM_MODEL', true],
['RTE_CACHE_LINE_SIZE', 64],
['RTE_MAX_NUMA_NODES', 1],
['RTE_MAX_LCORE', 16]]
flags_dpaa2 = [
['RTE_MACHINE', '"dpaa2"'],
+ ['RTE_USE_C11_MEM_MODEL', true],
['RTE_CACHE_LINE_SIZE', 64],
['RTE_MAX_NUMA_NODES', 1],
['RTE_MAX_LCORE', 16],