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authorDavid Christensen <drc@linux.vnet.ibm.com>2019-05-08 16:02:43 -0500
committerThomas Monjalon <thomas@monjalon.net>2019-05-09 21:58:31 +0200
commit2d119c3baac4409092d064d386deb33d8f61f90f (patch)
treedcce021b62b5db9346750ec7d2ab1e551f40f6e1
parentf8f207c00f03882295abad82d6e4e603f2b19085 (diff)
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test/barrier: fix for Power CPUs
The memory barrier test fails on IBM Power 9 systems. Add additional barriers to accommodate the weakly ordered model used on Power CPUs. Fixes: 93da5b59afc9 ("test: introduce memory barrier test case") Cc: stable@dpdk.org Signed-off-by: David Christensen <drc@linux.vnet.ibm.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
-rw-r--r--app/test/test_barrier.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/app/test/test_barrier.c b/app/test/test_barrier.c
index a0b4704..43b5f62 100644
--- a/app/test/test_barrier.c
+++ b/app/test/test_barrier.c
@@ -92,12 +92,14 @@ plock_lock(struct plock *l, uint32_t self)
other = self ^ 1;
l->flag[self] = 1;
+ rte_smp_wmb();
l->victim = self;
store_load_barrier(l->utype);
while (l->flag[other] == 1 && l->victim == self)
rte_pause();
+ rte_smp_rmb();
}
static void