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#########################################################################
#
# @par
#   BSD LICENSE
# 
#   Copyright(c) 2010-2012 Intel Corporation. All rights reserved.
#   All rights reserved.
# 
#   Redistribution and use in source and binary forms, with or without 
#   modification, are permitted provided that the following conditions 
#   are met:
# 
#     * Redistributions of source code must retain the above copyright 
#       notice, this list of conditions and the following disclaimer.
#     * Redistributions in binary form must reproduce the above copyright 
#       notice, this list of conditions and the following disclaimer in 
#       the documentation and/or other materials provided with the 
#       distribution.
#     * Neither the name of Intel Corporation nor the names of its 
#       contributors may be used to endorse or promote products derived 
#       from this software without specific prior written permission.
# 
#   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
#   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
#   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 
#   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
#   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
#   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
#   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 
#   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 
#   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
#   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
# 
#########################################################################
########################################################
#
# This file is the configuration for a single dh89xxcc_qa
# device.
#
# Each device has up to two accelerators.
# - The client may load balance between these
#   accelerators.
# Each accelerator has 8 independent ring banks.
# - The interrupt for each can be directed to a
#   specific core.
# Each ring bank as 16 rings (hardware assisted queues).
#
########################################################

##############################################
# General Section
##############################################

[GENERAL]
ServicesEnabled = cy0;cy1

# Look Aside Cryptographic Configuration
cyHmacAuthMode = 1

# Look Aside Compression Configuration
dcTotalSRAMAvailable = 0
dcSRAMPerInstance = 0

# Firmware Location Configuration
Firmware_UofPath = uof_firmware.bin
Firmware_MmpPath = mmp_firmware.bin

# QAT Parameters
Accel0AdminBankNumber = 0
Accel0AcceleratorNumber = 0
Accel0AdminTx = 0
Accel0AdminRx = 1

Accel1AcceleratorNumber = 1
Accel1AdminBankNumber = 0
Accel1AdminTx = 0
Accel1AdminRx = 1

#Statistics, valid values: 1,0
statsGeneral = 1
statsDc = 1
statsDh = 1
statsDrbg = 1
statsDsa = 1
statsEcc = 1
statsKeyGen = 1
statsLn = 1
statsPrime = 1
statsRsa = 1
statsSym = 1

#Debug feature, if set to 1 it enables additional entries in /proc filesystem
ProcDebug = 1


################################################
#
# Hardware Access Ring Bank Configuration
# Each Accelerator has 8 ring banks (0-7)
# If the OS supports MSI-X, each ring bank has an
# steerable MSI-x interrupt which may be
# affinitized to a particular node/core.
#
################################################


[Accelerator0]
Bank0InterruptCoalescingEnabled = 1
Bank0InterruptCoalescingTimerNs = 10000
Bank0CoreIDAffinity = 0
Bank0InterruptCoalescingNumResponses = 0

Bank1InterruptCoalescingEnabled = 1
Bank1InterruptCoalescingTimerNs = 10000
Bank1CoreIDAffinity = 2
Bank1InterruptCoalescingNumResponses = 0

Bank2InterruptCoalescingEnabled = 1
Bank2InterruptCoalescingTimerNs = 10000
Bank2CoreIDAffinity = 4
Bank2InterruptCoalescingNumResponses = 0

Bank3InterruptCoalescingEnabled = 1
Bank3InterruptCoalescingTimerNs = 10000
Bank3CoreIDAffinity = 6
Bank3InterruptCoalescingNumResponses = 0

Bank4InterruptCoalescingEnabled = 1
Bank4InterruptCoalescingTimerNs = 10000
Bank4CoreIDAffinity = 7
Bank4InterruptCoalescingNumResponses = 0

Bank5InterruptCoalescingEnabled = 1
Bank5InterruptCoalescingTimerNs = 10000
Bank5CoreIDAffinity = 7
Bank5InterruptCoalescingNumResponses = 0

Bank6InterruptCoalescingEnabled = 1
Bank6InterruptCoalescingTimerNs = 10000
Bank6CoreIDAffinity = 7
Bank6InterruptCoalescingNumResponses = 0

Bank7InterruptCoalescingEnabled = 1
Bank7InterruptCoalescingTimerNs = 10000
Bank7CoreIDAffinity = 7
Bank7InterruptCoalescingNumResponses = 0

[Accelerator1]
Bank0InterruptCoalescingEnabled = 1
Bank0InterruptCoalescingTimerNs = 10000
Bank0CoreIDAffinity = 1
Bank0InterruptCoalescingNumResponses = 0

Bank1InterruptCoalescingEnabled = 1
Bank1InterruptCoalescingTimerNs = 10000
Bank1CoreIDAffinity = 3
Bank1InterruptCoalescingNumResponses = 0

Bank2InterruptCoalescingEnabled = 1
Bank2InterruptCoalescingTimerNs = 10000
Bank2CoreIDAffinity = 5
Bank2InterruptCoalescingNumResponses = 0

Bank3InterruptCoalescingEnabled = 1
Bank3InterruptCoalescingTimerNs = 10000
Bank3CoreIDAffinity = 7
Bank3InterruptCoalescingNumResponses = 0

Bank4InterruptCoalescingEnabled = 1
Bank4InterruptCoalescingTimerNs = 10000
Bank4CoreIDAffinity = 7
Bank4InterruptCoalescingNumResponses = 0

Bank5InterruptCoalescingEnabled = 1
Bank5InterruptCoalescingTimerNs = 10000
Bank5CoreIDAffinity = 7
Bank5InterruptCoalescingNumResponses = 0

Bank6InterruptCoalescingEnabled = 1
Bank6InterruptCoalescingTimerNs = 10000
Bank6CoreIDAffinity = 7
Bank6InterruptCoalescingNumResponses = 0

Bank7InterruptCoalescingEnabled = 1
Bank7InterruptCoalescingTimerNs = 10000
Bank7CoreIDAffinity = 7
Bank7InterruptCoalescingNumResponses = 0

#######################################################
#
# Logical Instances Section
# A logical instance allows each address domain
# (kernel space and individual user space processes)
# to configure rings (i.e. hardware assisted queues)
# to be used by that address domain and to define the
# behavior of that ring.
#
# The address domains are in the following format
# - For kernel address domains
#       [KERNEL]
# - For user process address domains
#   [xxxxx]
#   Where xxxxx may be any ascii value which uniquely identifies
#   the user mode process.
#   To allow the driver correctly configure the
#   logical instances associated with this user process,
#   the process must call the icp_sal_userStart(...)
#   passing the xxxxx string during process initialisation.
#   When the user space process is finish it must call
#   icp_sal_userStop(...) to free resources.
#   If there are multiple devices present in the system all conf
#   files that describe the devices must have the same address domain
#   sections even if the address domain does not configure any instances
#   on that particular device. So if icp_sal_userStart("xxxxx") is called
#   then user process address domain [xxxxx] needs to be present in all
#   conf files for all devices in the system.
#
# Items configurable by a logical instance are:
# - Name of the logical instance
# - The accelerator associated with this logical
#   instance
# - The ring bank associated with this logical
#   instance.
# - The response mode associated wth this logical instance (0
#   for IRQ or 1 for polled).
# - The ring for receiving and the ring for transmitting.
# - The number of concurrent requests supported by a pair of
#   rings on this instance (tx + rx). Note this number affects
#   the amount of memory allocated by the driver. Also
#   Bank<n>InterruptCoalescingNumResponses is only supported for
#   number of concurrent requests equal to 512.
#
# Note: Logical instances may not share the same ring, but
#           may share a ring bank.
#
# The format of the logical instances are:
# - For crypto:
#               Cy<n>Name = "xxxx"
#               Cy<n>AcceleratorNumber = 0|1
#               Cy<n>BankNumber = 0-7
#               Cy<n>IsPolled = 0|1
#               Cy<n>NumConcurrentSymRequests = 64|128|256|512|1024|2048|4096
#               Cy<n>NumConcurrentAsymRequests = 64|128|256|512|1024|2048|4096
#               Cy<n>RingAsymTx = 0-15
#               Cy<n>RingAsymRx = 0-15
#               Cy<n>RingSymTxHi = 0-15
#               Cy<n>RingSymRxHi = 0-15
#               Cy<n>RingSymRx = 0-15
#
# - For Data Compression
#               Dc<n>Name = "xxxx"
#               Dc<n>AcceleratorNumber = 0|1
#               Dc<n>BankNumber = 0-7
#               Dc<n>IsPolled = 0|1
#               Dc<n>NumConcurrentRequests = 64|128|256|512|1024|2048|4096
#               Dc<n>RingTx = 0-15
#               Dc<n>RingRx = 0-15
#
# Where:
#       - n is the number of this logical instance starting at 0.
#       - xxxx may be any ascii value which identifies the logical instance.
#
########################################################

##############################################
# Kernel Instances Section
##############################################
[KERNEL]
NumberCyInstances = 0
NumberDcInstances = 0


##############################################
# User Process Instance Section
##############################################
[SSL]
NumberCyInstances = 8
NumberDcInstances = 0

# Crypto - User instance #0
Cy0Name = "SSL0"
Cy0IsPolled = 1
Cy0AcceleratorNumber = 0
Cy0ExecutionEngine = 0
Cy0BankNumber = 0
Cy0NumConcurrentSymRequests = 512
Cy0NumConcurrentAsymRequests = 64

Cy0RingAsymTx =  2
Cy0RingAsymRx =  3
Cy0RingSymTxHi = 4
Cy0RingSymRxHi = 5
Cy0RingSymTxLo = 6
Cy0RingSymRxLo = 7

# Crypto - User instance #1
Cy1Name = "SSL1"
Cy1AcceleratorNumber = 1
Cy1ExecutionEngine = 0
Cy1BankNumber = 0
Cy1IsPolled = 1
Cy1NumConcurrentSymRequests = 512
Cy1NumConcurrentAsymRequests = 64

Cy1RingAsymTx =  2
Cy1RingAsymRx =  3
Cy1RingSymTxHi = 4
Cy1RingSymRxHi = 5
Cy1RingSymTxLo = 6
Cy1RingSymRxLo = 7

# Crypto - User instance #2
Cy2Name = "SSL2"
Cy2IsPolled= 1
Cy2AcceleratorNumber = 0
Cy2ExecutionEngine = 1
Cy2BankNumber = 1
Cy2NumConcurrentSymRequests = 512
Cy2NumConcurrentAsymRequests = 64

Cy2RingAsymTx =  0
Cy2RingAsymRx =  1
Cy2RingSymTxHi = 2
Cy2RingSymRxHi = 3
Cy2RingSymTxLo = 4
Cy2RingSymRxLo = 5

# Crypto - User instance #3
Cy3Name = "SSL3"
Cy3AcceleratorNumber = 1
Cy3ExecutionEngine = 1
Cy3BankNumber = 1
Cy3IsPolled = 1
Cy3NumConcurrentSymRequests = 512
Cy3NumConcurrentAsymRequests = 64

Cy3RingAsymTx =  0
Cy3RingAsymRx =  1
Cy3RingSymTxHi = 2
Cy3RingSymRxHi = 3
Cy3RingSymTxLo = 4
Cy3RingSymRxLo = 5


# Crypto - User instance #4
Cy4Name = "SSL4"
Cy4IsPolled= 1
Cy4AcceleratorNumber = 0
Cy4ExecutionEngine = 0
Cy4BankNumber = 2
Cy4NumConcurrentSymRequests = 512
Cy4NumConcurrentAsymRequests = 64

Cy4RingAsymTx =  0
Cy4RingAsymRx =  1
Cy4RingSymTxHi = 2
Cy4RingSymRxHi = 3
Cy4RingSymTxLo = 4
Cy4RingSymRxLo = 5

# Crypto - User instance #5
Cy5Name = "SSL5"
Cy5AcceleratorNumber = 1
Cy5ExecutionEngine = 0
Cy5BankNumber = 2
Cy5IsPolled = 1
Cy5NumConcurrentSymRequests = 512
Cy5NumConcurrentAsymRequests = 64

Cy5RingAsymTx =  0
Cy5RingAsymRx =  1
Cy5RingSymTxHi = 2
Cy5RingSymRxHi = 3
Cy5RingSymTxLo = 4
Cy5RingSymRxLo = 5

# Crypto - User instance #6
Cy6Name = "SSL6"
Cy6IsPolled = 1
Cy6AcceleratorNumber = 0
Cy6ExecutionEngine = 1
Cy6BankNumber = 3
Cy6NumConcurrentSymRequests = 512
Cy6NumConcurrentAsymRequests = 64

Cy6RingAsymTx =  0
Cy6RingAsymRx =  1
Cy6RingSymTxHi = 2
Cy6RingSymRxHi = 3
Cy6RingSymTxLo = 4
Cy6RingSymRxLo = 5

# Crypto - User instance #7
Cy7Name = "SSL7"
Cy7AcceleratorNumber = 1
Cy7ExecutionEngine = 1
Cy7BankNumber = 3
Cy7IsPolled = 1
Cy7NumConcurrentSymRequests = 512
Cy7NumConcurrentAsymRequests = 64

Cy7RingAsymTx =  0
Cy7RingAsymRx =  1
Cy7RingSymTxHi = 2
Cy7RingSymRxHi = 3
Cy7RingSymTxLo = 4
Cy7RingSymRxLo = 5