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path: root/drivers/net/mlx5/mlx5_prm.h
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12 daysnet/mlx5: fix legacy inline multi-packet performanceViacheslav Ovsiienko
The legacy multi-packet write is the feature allowing to put multiple packets into one transmitting descriptor, this feature is supported by only NIC ConnectX-4LX. The number of packets should be limited to provide optimal size descriptor and better performance. Fixes: 18a1c20044c0 ("net/mlx5: implement Tx burst template") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
12 daysnet/mlx5: fix legacy non-inline multi-packet performanceViacheslav Ovsiienko
The legacy multi-packet write is the feature allowing to put multiple packets into one transmitting descriptor, this feature is supported by only NIC ConnectX-4LX. The number of packets should be limited to provide optimal size descriptor and better performance. Fixes: 18a1c20044c0 ("net/mlx5: implement Tx burst template") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
2019-11-11net/mlx5: support meter modification operationsSuanming Mou
This commit add meter enable and disable supoort. New internal functions in rte_mtr_ops callback: 1. meter_enable() 2. meter_disable() The meter_enable() enables the meter action and the meter_disable() disables the meter action. Signed-off-by: Suanming Mou <suanmingm@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
2019-11-11net/mlx5: prepare meter flow tablesSuanming Mou
This commit prepare the meter table and suffix table. A flow with meter will be split to three flows. The three flows are created on differnet tables. The packets transfer between the flows on the tables as below: Prefix flow -> Meter flow -> Suffix flow Prefix flow does the user defined match and the meter action. The meter action colors the packet and set its destination to meter table to be processed by the meter flow. The meter flow judges if the packet can be passed or not. If packet can be passed, it will be transferred to the suffix table. The suffix flow on the suffix table will apply the left user defined actions to the packet. The ingress egress and transfer all have the independent meter and suffix tables. Signed-off-by: Suanming Mou <suanmingm@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
2019-11-11net/mlx5: validate meter profileSuanming Mou
The add meter profile should be validated if it is valid or has been add to the list. Invalid and exist profile should not be add to the list. Signed-off-by: Suanming Mou <suanmingm@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
2019-11-11net/mlx5: add metadata support to Rx datapathViacheslav Ovsiienko
This patch moves metadata from completion descriptor to appropriate dynamic mbuf field. Signed-off-by: Yongseok Koh <yskoh@mellanox.com> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
2019-11-11net/mlx5: add devarg for extensive metadata supportViacheslav Ovsiienko
The PMD parameter dv_xmeta_en is added to control extensive metadata support. A nonzero value enables extensive flow metadata support if device is capable and driver supports it. This can enable extensive support of MARK and META item of rte_flow. The newly introduced SET_TAG and SET_META actions do not depend on dv_xmeta_en parameter, because there is no compatibility issue for new entities. The dv_xmeta_en is disabled by default. There are some possible configurations, depending on parameter value: - 0, this is default value, defines the legacy mode, the MARK and META related actions and items operate only within NIC Tx and NIC Rx steering domains, no MARK and META information crosses the domain boundaries. The MARK item is 24 bits wide, the META item is 32 bits wide. - 1, this engages extensive metadata mode, the MARK and META related actions and items operate within all supported steering domains, including FDB, MARK and META information may cross the domain boundaries. The ``MARK`` item is 24 bits wide, the META item width depends on kernel and firmware configurations and might be 0, 16 or 32 bits. Within NIC Tx domain META data width is 32 bits for compatibility, the actual width of data transferred to the FDB domain depends on kernel configuration and may be vary. The actual supported width can be retrieved in runtime by series of rte_flow_validate() trials. - 2, this engages extensive metadata mode, the MARK and META related actions and items operate within all supported steering domains, including FDB, MARK and META information may cross the domain boundaries. The META item is 32 bits wide, the MARK item width depends on kernel and firmware configurations and might be 0, 16 or 24 bits. The actual supported width can be retrieved in runtime by series of rte_flow_validate() trials. If there is no E-Switch configuration the ``dv_xmeta_en`` parameter is ignored and the device is configured to operate in legacy mode (0). Signed-off-by: Yongseok Koh <yskoh@mellanox.com> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
2019-11-11net/mlx5: check metadata registers availabilityViacheslav Ovsiienko
The metadata registers reg_c provide support for TAG and SET_TAG features. Although there are 8 registers are available on the current mlx5 devices, some of them can be reserved. The availability should be queried by iterative trial-and-error implemented by mlx5_flow_discover_mreg_c() routine. If reg_c is available, it can be regarded inclusively that the extensive metadata support is possible. E.g. metadata register copy action, supporting 16 modify header actions (instead of 8 by default) preserving register across different domains (FDB and NIC) and so on. Signed-off-by: Yongseok Koh <yskoh@mellanox.com> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
2019-11-11net/mlx5: update modify header action translatorViacheslav Ovsiienko
When composing device command for modify header action, provided mask should be taken more accurate into account thus length and offset in action should be set accordingly at precise bit-wise boundaries. For the future use, metadata register copy action is also added. Signed-off-by: Yongseok Koh <yskoh@mellanox.com> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
2019-11-08net/mlx5: add internal tag item and actionOri Kam
This commit introduce the setting and matching on registers. This item and and action will be used with number of different features like hairpin, metering, metadata. Signed-off-by: Ori Kam <orika@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-11-08net/mlx5: add hairpin binding functionOri Kam
When starting the port, in addition to creating the queues we need to bind the hairpin queues. Signed-off-by: Ori Kam <orika@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-11-08net/mlx5: support Tx hairpin queuesOri Kam
This commit adds the support for creating Tx hairpin queues. Hairpin queue is a queue that is created using DevX and only used by the HW. Signed-off-by: Ori Kam <orika@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-10-23net/mlx5: add flow match on GENEVE itemMoti Haimovsky
This commit adds support for matching flows on Geneve headers. Signed-off-by: Moti Haimovsky <motih@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-10-23net/mlx5: query HCA for enabled FLEX parser protocolsMoti Haimovsky
This commit add querying the HCA which FLEX protocols are already enabled. Signed-off-by: Moti Haimovsky <motih@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-10-08net/mlx5: update source and destination vport translationsViacheslav Ovsiienko
There new kernel/rdma_core [1] supports matching on metadata register instead of vport field to provide operations over VF LAG bonding configurations. This patch provides correct translations for flow matchers and destination port actions if united E-Switch (for VF LAG) is configured and/or new vport matching mode is engaged. [1] http://patchwork.ozlabs.org/cover/1122170/ "Mellanox, mlx5 vport metadata matching" Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
2019-09-20net/mlx5: support modify VLAN ID on existing VLAN headerMoti Haimovsky
This commit adds support for modifying the VID of the outermost VLAN header already present in the packet. Signed-off-by: Moti Haimovsky <motih@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-08-06net/mlx5: fix packet size inline settingsViacheslav Ovsiienko
This patch fixes the default settings for packet size to inline with Enhanced Multi-Packet Write feature, allowing 256B packets to be inlined with Out-Of-the-Box settings. Fixes: 50724e1bba76 ("net/mlx5: update Tx definitions") Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
2019-07-29net/mlx5: fix Tx completion request generationViacheslav Ovsiienko
The packets transmitting in mlx5 is performed by building Tx descriptors (WQEs) and sending last ones to the NIC. The descriptor can contain the special flags, telling the NIC to generate Tx completion notification (CQEs). At the beginning of tx_burst() routine PMD checks whether there are some Tx completions and frees the transmitted packet buffers. The flags to request completion generation must be set once per specified amount of packets to provide uniform stream of completions and freeing the Tx queue in uniform fashion. The previous implementation sets the completion request generation once per burst, if burst size if big enough it may latency in CQE generation and freeing large amount of buffers in tx_burst routine on multiple completions which also affects the latency and even causes the Tx queue overflow and Tx drops. This patches enforces the completion request will be set in the exact Tx descriptor if specified amount of packets is already sent. Fixes: 18a1c20044c0 ("net/mlx5: implement Tx burst template") Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
2019-07-29net/mlx5: fix DevX Rx queue memory alignmentMatan Azrad
The alignment requested by the FW for WQ buffer allocation is 512. Change it from cache line alignment to 512. Fixes: dc9ceff73c99 ("net/mlx5: create advanced RxQ via DevX") Signed-off-by: Matan Azrad <matan@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-07-29net/mlx5: allow LRO in regular Rx queueMatan Azrad
LRO support was only for MPRQ, hence mprq Rx burst was selected when LRO was configured in the port. The current support for MPRQ is suffering from bad memory utilization since an external mempool is allocated by the PMD for the packets data in addition to the user mempool, besides that, the user may get packet data addresses which were not configured by him. Even though MPRQ has the best performance for packet receiving in the most cases and because of the above facts it is better to remove the automatic MPRQ select when LRO is configured. Move MPRQ to be selected only when the user force it by the PMD arguments including LRO case. Allow LRO offload using the regular RQ with the regular Rx burst function. Signed-off-by: Matan Azrad <matan@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-07-29net/mlx5: limit LRO size to maximum Rx packetMatan Azrad
The field max_rx_pkt_len in Rx configuration indicates the maximum size for Rx packet to be received. There was no any field to indicate the maximum size of LRO packet to be received by the application. Assuming the user configures max_rx_pkt_len as the maximum LRO packet length when LRO is configured on the port, the PMD limits the maximum LRO packet size received from HW to be max_rx_pkt_len. Signed-off-by: Matan Azrad <matan@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-07-23net/mlx5: handle LRO packets in Rx queueMatan Azrad
When LRO offload is configured in Rx queue, the HW may coalesce TCP packets from same TCP connection into single packet. In this case the SW should fix the relevant packet headers because the HW doesn't update them according to the new created packet characteristics. Add update header code to the mprq Rx burst function to support LRO feature. Signed-off-by: Matan Azrad <matan@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-07-23net/mlx5: update LRO fields in completion entryMatan Azrad
Update the CQE structure to include LRO fields. Some reserved values were changed, hence also data-path code used the reserved values were updated accordingly. Signed-off-by: Matan Azrad <matan@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-07-23net/mlx5: create advanced RxQ table via DevXDekel Peled
Implement function mlx5_devx_cmd_create_rqt() to create RQT object using DevX API. Add related structs in mlx5.h and mlx5_prm.h. Signed-off-by: Dekel Peled <dekelp@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-07-23net/mlx5: create advanced Rx object via DevXDekel Peled
Implement function mlx5_devx_cmd_create_tir() to create TIR object using DevX API.. Add related structs in mlx5.h and mlx5_prm.h. Signed-off-by: Dekel Peled <dekelp@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-07-23net/mlx5: modify advanced RxQ object via DevXDekel Peled
Implement function mlx5_devx_cmd_modify_rq() to modify RQ. Add related structs in mlx5.h and mlx5_prm.h. Signed-off-by: Dekel Peled <dekelp@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-07-23net/mlx5: create advanced RxQ object via DevXDekel Peled
Implement function mlx5_devx_cmd_create_rq() to create RQ object using DevX API. Add related structs in mlx5.h and mlx5_prm.h. Signed-off-by: Dekel Peled <dekelp@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-07-23net/mlx5: support Tx interface query via DevXDekel Peled
Implement function mlx5_devx_cmd_qp_tis_td_query(), to query QP TIS Transport Domain value. Add related structs in mlx5_prm.h. Signed-off-by: Dekel Peled <dekelp@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-07-23net/mlx5: query LRO capabilities via DevXDekel Peled
Update function mlx5_devx_cmd_query_hca_attr() to query HCA capabilities related to LRO. Add relevant structs in drivers/net/mlx5/mlx5_prm.h. Signed-off-by: Dekel Peled <dekelp@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-07-23net/mlx5: extend NIC attributes query via DevXViacheslav Ovsiienko
This patch extends the NIC attributes query via DevX. The appropriate interface structures are borrowed from kernel driver headers and DevX calls are added to mlx5_devx_cmd_query_hca_attr() routine. Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Yongseok Koh <yskoh@mellanox.com>
2019-07-23net/mlx5: update Tx definitionsViacheslav Ovsiienko
This patch updates Tx datapath definitions, mostly hardware related. The Tx descriptor structures are redefined with required fields, size definitions are renamed to reflect the meanings in more appropriate way. This is a preparation step before introducing the new Tx datapath implementation. Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Yongseok Koh <yskoh@mellanox.com>
2019-07-23net/mlx5: remove Tx implementationViacheslav Ovsiienko
This patch removes the existing Tx datapath code as preparation step before introducing the new implementation. The following entities are being removed: - deprecated devargs support - tx_burst() routines - related PRM definitions - SQ configuration code - Tx routine selection code - incompatible Tx completion code The following devargs are deprecated and ignored: - "txq_inline" is going to be converted to "txq_inline_max" for compatibility issue - "tx_vec_en" - "txqs_max_vec" - "txq_mpw_hdr_dseg_en" - "txq_max_inline_len" is going to be converted to "txq_inline_mpw" for compatibility issue The deprecated devarg keys are recognized by PMD and ignored/converted to the new ones in order not to block device probing. Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Yongseok Koh <yskoh@mellanox.com>
2019-07-23net/mlx5: allow basic counter management fallbackMatan Azrad
In case the asynchronous devx commands are not supported in RDMA core fallback to use a basic counter management. Here, the PMD counters cashe is redundant and the host thread doesn't update it. hence, each counter operation will go to the FW and the acceleration reduces. Signed-off-by: Matan Azrad <matan@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2019-07-23net/mlx5: accelerate DV flow counter transactionsMatan Azrad
The DevX interface exposes a new feature to the PMD that can allocate a batch of counters by one FW command. It can improve the flow transaction rate (with count action). Add a new counter pools mechanism to manage HW counters in the PMD. So, for each flow with counter creation the PMD will try to find a free counter in the PMD pools container and only if there is no a free counter, it will allocate a new DevX batch counters. Currently we cannot support batch counter for a group 0 flow, so create a 2 container types, one which allocates counters one by one and one which allocates X counters by the batch feature. The allocated counters objects are never released back to the HW assuming the flows maximum number will be close to the actual value of the flows number. Later, it can be updated, and dynamic release mechanism can be added. The counters are contained in pools, each pool with 512 counters. The pools are contained in counter containers according to the allocation resolution type - single or batch. The cache memory of the counters statistics is saved as raw data per pool. All the raw data memory is allocated for all the container in one memory allocation and is managed by counter_stats_mem_mng structure which registers all the raw memory to the HW. Each pool points to one raw data structure. The query operation is in pool resolution which updates all the pool counter raw data by one operation. Signed-off-by: Matan Azrad <matan@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2019-07-23net/mlx5: match GRE key and present bitsXiaoyu Min
Support matching on the present bits (C,K,S) as well as the optional key field. If the rte_flow_item_gre_key is specified in pattern, it will set K present match automatically. Signed-off-by: Xiaoyu Min <jackmin@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-07-05net/mlx5: modify TCP header using Direct VerbsDekel Peled
This patch implements additional actions of packet header modifications. Add actions: - INC_TCP_SEQ - Increase sequence number in the outermost TCP header. - DEC_TCP_SEQ - Decrease sequence number in the outermost TCP header. - INC_TCP_ACK - Increase acknowledgment number in the outermost TCP header. - DEC_TCP_ACK - Decrease acknowledgment number in the outermost TCP header. Original work by Xiaoyu Min. Signed-off-by: Dekel Peled <dekelp@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
2019-06-14net/mlx5: handle Tx completion with errorMatan Azrad
When WQEs are posted to the HW to send packets, the PMD may get a completion report with error from the HW, aka error CQE which is associated to a bad WQE. The error reason may be bad address, wrong lkey, bad sizes, etc. that can wrongly be configured by the PMD or by the user. Checking all the optional mistakes to prevent error CQEs doesn't make sense due to performance impacts and huge complexity. The error CQEs change the SQ state to error state what causes all the next posted WQEs to be completed with CQE flush error forever. Currently, the PMD doesn't handle Tx error CQEs and even may crashed when one of them appears. Extend the Tx data-path to detect these error CQEs, to report them by the statistics error counters, to recover the SQ by moving the state to ready again and adjusting the management variables appropriately. Sometimes the error CQE root cause is very hard to debug and even may be related to some corner cases which are not reproducible easily, hence a dump file with debug information will be created for the first number of error CQEs, this number can be configured by the PMD probe parameters. Cc: stable@dpdk.org Signed-off-by: Matan Azrad <matan@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2019-05-27net/mlx5: remove redundant size calculation macroDekel Peled
Patch [1] added, among other definitions, the macro MLX5_ST_SZ_DB. Patch [2] added later the macro MLX5_ST_SZ_BYTES, which is exactly the same macro with a different name. Each of these macros was used in very few places. This patch removes the definition of MLX5_ST_SZ_DB, and replaces it with MLX5_ST_SZ_BYTES wherever it was used. Macro MLX5_ST_SZ_BYTES was preffered since it is the same macro name used in kernel code, see [3]. [1] http://patches.dpdk.org/patch/45254/ [2] http://patches.dpdk.org/patch/49403/ [3] https://lists.openwall.net/netdev/2014/10/02/75 Signed-off-by: Dekel Peled <dekelp@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2019-04-19net/mlx5: support Direct Rules E-SwitchOri Kam
This commit checks the for DR E-Switch support. The support is based on both Device and Kernel. This commit also enables the user to manually disable this this feature. Signed-off-by: Ori Kam <orika@mellanox.com> Acked-by: Yongseok Koh <yskoh@mellanox.com>
2019-04-05net/mlx5: add Direct Rules APIOri Kam
Adds calls to the Direct Rules API inside the glue functions. Due to difference in parameters between the Direct Rules and Direct Verbs some of the glue functions API was updated. Signed-off-by: Ori Kam <orika@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2019-01-14net/mlx5: support flow counters using devxMoti Haimovsky
This commit adds counters support when creating flows via direct verbs. The implementation uses devx interface in order to create query and delete the counters. This support requires MLNX_OFED_LINUX-4.5-0.1.0.1 installation. Signed-off-by: Moti Haimovsky <motih@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2019-01-03net/mlx5: support modify header using Direct VerbsDekel Peled
This patch implements the set of actions to support offload of packet header modifications to MLX5 NIC. Implementation is based on RFC [1]. [1] http://mails.dpdk.org/archives/dev/2018-November/119971.html Signed-off-by: Dekel Peled <dekelp@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2018-10-26net/mlx5: support metadata as flow rule criteriaDekel Peled
As described in series starting at [1], it adds option to set metadata value as match pattern when creating a new flow rule. This patch adds metadata support in mlx5 driver, in two parts: - Add the validation and setting of metadata value in matcher, when creating a new flow rule. - Add the passing of metadata value from mbuf to wqe when indicated by ol_flag, in different burst functions. [1] "ethdev: support metadata as flow rule criteria" http://mails.dpdk.org/archives/dev/2018-September/113269.html Signed-off-by: Dekel Peled <dekelp@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2018-10-11net/mlx5: add Direct Verbs translate itemsOri Kam
This commit handles the translation of the requested flow into Direct Verbs API. The Direct Verbs introduce the matcher object which acts as shared mask for all flows that are using the same mask. So in this commit we translate the item and get in return a matcher and the value that should be matched. Signed-off-by: Ori Kam <orika@mellanox.com> Acked-by: Yongseok Koh <yskoh@mellanox.com>
2018-10-11net/mlx5: add Direct Verbs prepare functionOri Kam
This function allocates the Direct Verbs device flow, and introduce the relevant PRM structures. This commit also adds the matcher object. The matcher object acts as a mask and should be shared between flows. For example all rules that should match source IP with full mask should use the same matcher. A flow that should match dest IP or source IP but without full mask should have a new matcher allocated. Signed-off-by: Ori Kam <orika@mellanox.com> Acked-by: Yongseok Koh <yskoh@mellanox.com>
2018-07-12net/mlx5: use a macro for the RSS key sizeNelio Laranjeiro
ConnectX 4-5 support only 40 bytes of RSS key, using a compiled size hash key is not necessary. Signed-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com> Acked-by: Yongseok Koh <yskoh@mellanox.com>
2018-07-03net/mlx5: add new fields in Rx completion entryYongseok Koh
Stride index is added to mlx5_mini_cqe8 structure and WQE ID is added to mlx5_cqe structure. Signed-off-by: Yongseok Koh <yskoh@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2018-05-14net/mlx5: add Multi-Packet Rx supportYongseok Koh
Multi-Packet Rx Queue (MPRQ a.k.a Striding RQ) can further save PCIe bandwidth by posting a single large buffer for multiple packets. Instead of posting a buffer per a packet, one large buffer is posted in order to receive multiple packets on the buffer. A MPRQ buffer consists of multiple fixed-size strides and each stride receives one packet. Rx packet is mem-copied to a user-provided mbuf if the size of Rx packet is comparatively small, or PMD attaches the Rx packet to the mbuf by external buffer attachment - rte_pktmbuf_attach_extbuf(). A mempool for external buffers will be allocated and managed by PMD. Signed-off-by: Yongseok Koh <yskoh@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2018-04-27net/mlx5: support generic tunnel offloadingXueming Li
This commit adds support for generic tunnel TSO and checksum offload. PMD will compute the inner/outer headers offset according to the mbuf fields. Hardware will do calculation based on offsets and types. Signed-off-by: Xueming Li <xuemingl@mellanox.com> Acked-by: Yongseok Koh <yskoh@mellanox.com>
2018-04-11align SPDX Mellanox copyrightsShahaf Shuler
Aligning Mellanox SPDX copyrights to a single format. In addition replace to SPDX licence files which were missed. Signed-off-by: Shahaf Shuler <shahafs@mellanox.com> Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>