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path: root/doc/guides/nics/mlx5.rst
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7 daysdoc: update offload dependencies in mlx5 guideRaslan Darawsheh
Fix OFED and rdma-core versions for current offloads. Add new offloads minimum versions. Signed-off-by: Raslan Darawsheh <rasland@mellanox.com> Acked-by: Ori Kam <orika@mellanox.com>
9 daysnet/mlx5: fix flow engine choiceDekel Peled
Commit in fixes line sets the DV (Direct Verbs) flow engine as default. Newer versions of DV flow engine use the DR (Direct Rules) features. DR is supported from RDMA Core library version rdma-core-24.0. This cause failure to start port when using older rdma-core version, without DR support. This patch selects DV flow engine if rdma-core version is v24.0 or higher. Verbs flow engine is selected otherwise. Fixes: cd4569d2bf3c ("net/mlx5: change default flow engine to DV") Signed-off-by: Dekel Peled <dekelp@mellanox.com> Acked-by: Ori Kam <orika@mellanox.com>
9 daysdoc: update metadata feature in mlx5 guideViacheslav Ovsiienko
Legacy Verbs supports MARK and FLAG metadata actions only. Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-11-20net/mlx5: fix Tx doorbell write memory barrierViacheslav Ovsiienko
As the result of testing it was found that some hosts have the performance penalty imposed by required write memory barrier after doorbell writing. Before 19.08 release there was some heuristics to decide whether write memory barrier should be performed. For the bursts of recommended size (or multiple) it was supposed there were some extra ongoing packets in the next burst and write memory barrier may be skipped (supposed to be performed in the next burst, at least after descriptor writing). This patch restores that behaviour, the devargs tx_db_nc=2 must be specified to engage this performance tuning feature. Fixes: 8409a28573d3 ("net/mlx5: control transmit doorbell register mapping") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-11-20net/mlx5: change default flow engine to DVDekel Peled
The default flow engine is Verbs flow engine, for legacy reasons. This patch changes the default to DV flow engine (dv_flow_en = 1). Documentation is updated accordingly. Signed-off-by: Dekel Peled <dekelp@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-11-12net/mlx5: set maximum LRO packet sizeDekel Peled
This patch implements use of the API for LRO aggregated packet max size. Rx queue create is updated to use the relevant configuration. Documentation is updated accordingly. Signed-off-by: Dekel Peled <dekelp@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
2019-11-11net/mlx5: control transmit doorbell register mappingViacheslav Ovsiienko
The rdma core library can map doorbell register in two ways, depending on the environment variable "MLX5_SHUT_UP_BF": - as regular cached memory, the variable is either missing or set to zero. This type of mapping may cause the significant doorbell register writing latency and requires explicit memory write barrier to mitigate this issue and prevent write combining. - as non-cached memory, the variable is present and set to not "0" value. This type of mapping may cause performance impact under heavy loading conditions but the explicit write memory barrier is not required and it may improve core performance. The new devarg is introduced "tx_db_nc", if this parameter is set to zero, the doorbell register is forced to be mapped to cached memory and requires explicit memory barrier after writing to. If "tx_db_nc" is set to non-zero value the doorbell will be mapped as non-cached memory, not requiring the memory barrier. If "tx_db_nc" is missing the behaviour will be defined by presence of "MLX5_SHUT_UP_BF" in environment. If variable is missed the default value zero will be set for ARM64 hosts and one for others. In run time the code checks the mapping type and provides the memory barrier after writing to tx doorbell register if it is needed. The mapping type is extracted directly from the uar_mmap_offset field in the queue properties. Fixes: 18a1c20044c0 ("net/mlx5: implement Tx burst template") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
2019-11-11net/mlx5: add devarg for extensive metadata supportViacheslav Ovsiienko
The PMD parameter dv_xmeta_en is added to control extensive metadata support. A nonzero value enables extensive flow metadata support if device is capable and driver supports it. This can enable extensive support of MARK and META item of rte_flow. The newly introduced SET_TAG and SET_META actions do not depend on dv_xmeta_en parameter, because there is no compatibility issue for new entities. The dv_xmeta_en is disabled by default. There are some possible configurations, depending on parameter value: - 0, this is default value, defines the legacy mode, the MARK and META related actions and items operate only within NIC Tx and NIC Rx steering domains, no MARK and META information crosses the domain boundaries. The MARK item is 24 bits wide, the META item is 32 bits wide. - 1, this engages extensive metadata mode, the MARK and META related actions and items operate within all supported steering domains, including FDB, MARK and META information may cross the domain boundaries. The ``MARK`` item is 24 bits wide, the META item width depends on kernel and firmware configurations and might be 0, 16 or 32 bits. Within NIC Tx domain META data width is 32 bits for compatibility, the actual width of data transferred to the FDB domain depends on kernel configuration and may be vary. The actual supported width can be retrieved in runtime by series of rte_flow_validate() trials. - 2, this engages extensive metadata mode, the MARK and META related actions and items operate within all supported steering domains, including FDB, MARK and META information may cross the domain boundaries. The META item is 32 bits wide, the MARK item width depends on kernel and firmware configurations and might be 0, 16 or 24 bits. The actual supported width can be retrieved in runtime by series of rte_flow_validate() trials. If there is no E-Switch configuration the ``dv_xmeta_en`` parameter is ignored and the device is configured to operate in legacy mode (0). Signed-off-by: Yongseok Koh <yskoh@mellanox.com> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
2019-11-08net/mlx5: add ConnectX6-DX device IDRaslan Darawsheh
This adds new device id to the list of Mellanox devices that runs mlx5 PMD. - ConnectX-6DX device ID - ConnectX-6DX SRIOV device ID Signed-off-by: Raslan Darawsheh <rasland@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-11-08net/mlx5: fix LRO dependency to include DV flowDekel Peled
Rx queue for LRO is created using DevX. Flows created on this queue must use the DV flow engine. This patch adds check of dv_flow_en=1 when configuring LRO support on device spawn. Documentation is updated accordingly. Fixes: 175f1c21d033 ("net/mlx5: check conditions to enable LRO") Cc: stable@dpdk.org Signed-off-by: Dekel Peled <dekelp@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-10-23net/mlx5: add flow match on GENEVE itemMoti Haimovsky
This commit adds support for matching flows on Geneve headers. Signed-off-by: Moti Haimovsky <motih@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-10-08net/mlx5: adjust inline setting for large Tx queue sizesViacheslav Ovsiienko
The hardware may have limitations on maximal amount of supported Tx descriptors building blocks (WQEBB). Application requires the Tx queue must accept the specified amount of packets. If inline data feature is engaged the packet may require more WQEBBs and overall amount of blocks may exceed the hardware capabilities. Application has to make a trade-off between Tx queue size and maximal data inline size. In case if the inline settings are not requested explicitly with devarg keys the default values are used. This patch adjusts the applied default values if large Tx queue size is requested and default inline settings can not be satisfied due to hardware limitations. The explicitly requested inline setting may be aligned (enlarging only) by configurations routines to provide better WQEBB filling, this implicit alignment is the subject for adjustment either. The warning message is emitted to the log if adjustment happens. Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-09-20net/mlx5: support modify VLAN ID on existing VLAN headerMoti Haimovsky
This commit adds support for modifying the VID of the outermost VLAN header already present in the packet. Signed-off-by: Moti Haimovsky <motih@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-09-20net/mlx5: support modify VLAN ID on new VLAN headerMoti Haimovsky
This commit adds support for modifying the VLAN ID (VID) field in an about-to-be-pushed VLAN header. This feature can only modify the VID field of a new VLAN header yet to be pushed. It does not support modifying an existing or already pushed VLAN headers. Signed-off-by: Moti Haimovsky <motih@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-09-20net/mlx5: support modifying VLAN priority on VLAN headerMoti Haimovsky
This commit adds support for modifying the VLAN priority (PCP) field in about-to-be-pushed VLAN header. This feature can only modify the PCP field of a new VLAN header yet to be pushed. It does not support modifying an existing or already pushed VLAN headers. Signed-off-by: Moti Haimovsky <motih@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-09-20net/mlx5: support push flow action on VLAN headerMoti Haimovsky
This commit adds support for RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN using direct verbs flow rules. If present in the flow, The VLAN default values are taken from the VLAN item configuration. In this commit only the VLAN TPID value can be set since VLAN modification actions are not supported yet. Signed-off-by: Moti Haimovsky <motih@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-09-20net/mlx5: support pop flow action on VLAN headerMoti Haimovsky
This commit adds support for RTE_FLOW_ACTION_TYPE_OF_POP_VLAN via direct verbs flow rules. Signed-off-by: Moti Haimovsky <motih@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-08-08doc: add limitation with mlx5 Tx inline settingsViacheslav Ovsiienko
Introduces the possible limitations on maximal Tx queue size in descriptors if Tx inline data are enabled. Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-08-07doc: update Tx inline settings in mlx5 guideViacheslav Ovsiienko
This patch updates mlx5 documentation in parts: - txq_inline_min parameter is described in more details, values are fixed - maximal amount of segments in multi-segment packets. Fixes: 38b4b397a57d ("net/mlx5: add Tx configuration and setup") Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Raslan Darawsheh <rasland@mellanox.com>
2019-08-06doc: add more details about mlx5 offloadsThomas Monjalon
Add firmware config for MPLS and DevX (required by LRO and DR). Add a table for queue offloads requirements. Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Acked-by: Raslan Darawsheh <rasland@mellanox.com>
2019-08-06doc: add mlx5 design detailsThomas Monjalon
Some details about libibverbs were missing: - automatic detection by meson - main ways to access the device Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Acked-by: Raslan Darawsheh <rasland@mellanox.com>
2019-08-06doc: remove useless console syntax in mlx guidesThomas Monjalon
It is not needed to use "console" syntax highlighting for literal blocks. The file is easier to read by removing the code-block lines and simply having double colons in previous line. Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Acked-by: Raslan Darawsheh <rasland@mellanox.com>
2019-08-06doc: fix wording and formatting of mlx5 guideThomas Monjalon
These are simple fixes of punctuation, anchor placement or wording. The table format is fixed to avoid having a long line in the first column. Fixes: 909be50a34d0 ("doc: update Mellanox guides and release notes") Cc: stable@dpdk.org Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Acked-by: Raslan Darawsheh <rasland@mellanox.com>
2019-08-06doc: improve firmware configuration in mlx5 guideThomas Monjalon
The command mlxconfig was not enough explained and too much verbose at the same time. The syntax is now explained in introduction before listing the options, without repeating the commands. Some options, which are explained elsewhere in the doc, are added to this list. Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Acked-by: Raslan Darawsheh <rasland@mellanox.com>
2019-08-06net/mlx5: fix packet size inline settingsViacheslav Ovsiienko
This patch fixes the default settings for packet size to inline with Enhanced Multi-Packet Write feature, allowing 256B packets to be inlined with Out-Of-the-Box settings. Fixes: 50724e1bba76 ("net/mlx5: update Tx definitions") Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
2019-07-31doc: update features supported by mlxThomas Monjalon
Flow control was not documented as a supported feature since the first fill of features matrix for mlx drivers. Flow API and CRC offload flag support in mlx4 were missing in the feature matrix when they were implemented (see below commits). Fixes: 46d5736a7049 ("net/mlx4: support basic flow items and actions") Fixes: ce07b1514d59 ("net/mlx4: fix CRC stripping capability report") Fixes: e86b85ca757b ("doc: fill nics features matrix for mlx") Cc: stable@dpdk.org Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Acked-by: Matan Azrad <matan@mellanox.com>
2019-07-29net/mlx5: handle LRO packets in regular Rx queueMatan Azrad
When LRO offload is configured in Rx queue, the HW may coalesce TCP packets from same TCP connection into single packet. In this case the SW should fix the relevant packet headers because the HW doesn't update them according to the new created packet characteristics but provides the update values in the CQE. Add update header code to the regular Rx burst function to support LRO feature. Make sure the first mbuf has enough space to include each TCP header, otherwise the header update may cross mbufs what complicates the operation too match. Signed-off-by: Matan Azrad <matan@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-07-29net/mlx5: support mbuf headroom for LRO packetMatan Azrad
Patch [1] zeroes the mbuf headroom when the port is configured with LRO because when working with more than one stride per packet the HW cannot guaranty an headroom in the start stride of each packet. Change the solution to support mbuf headroom by adding an empty buffer as the first packet segment, scatter mode must be enabled to support it. [1] http://patches.dpdk.org/patch/56912/ Signed-off-by: Matan Azrad <matan@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-07-23net/mlx5: zero LRO mbuf headroomMatan Azrad
LRO packet may consume all the stride memory, hence the PMD cannot guaranty head-room for the LRO mbuf. The issue is lack in HW support to write the packet in offset from the stride start. A new striding RQ feature may be added in CX6 DX to allow head-room and tail-room for the LRO strides. Signed-off-by: Matan Azrad <matan@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-07-23net/mlx5: check conditions to enable LRODekel Peled
Use DevX API to read device LRO capabilities. Check if LRO is supported and can be enabled. Check if MPRQ is supported and can be used. Enable MPRQ for LRO use if not enabled by user. Added note for mlx5_mprq_enabled(), to emphasize that LRO enables MPRQ. Disable CQE compression and CRC stripping if LRO is enabled. Signed-off-by: Dekel Peled <dekelp@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-07-23net/mlx5: introduce LRODekel Peled
Add command-line argument to set LRO session timeout. Add LRO settings struct in PMD configuration struct. Add support of LRO offload in port configuration. Add macros and function to check if LRO is supported and enabled. Signed-off-by: Dekel Peled <dekelp@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-07-23net/mlx5: add Tx devargsViacheslav Ovsiienko
This patch introduces new mlx5 PMD devarg options: - txq_inline_min - specifies minimal amount of data to be inlined into WQE during Tx operations. NICs may require this minimal data amount to operate correctly. The exact value may depend on NIC operation mode, requested offloads, etc. - txq_inline_max - specifies the maximal packet length to be completely inlined into WQE Ethernet Segment for ordinary SEND method. If packet is larger the specified value, the packet data won't be copied by the driver at all, data buffer is addressed with a pointer. If packet length is less or equal all packet data will be copied into WQE. - txq_inline_mpw - specifies the maximal packet length to be completely inlined into WQE for Enhanced MPW method. Driver documentation is also updated. Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Yongseok Koh <yskoh@mellanox.com>
2019-07-23net/mlx5: remove Tx implementationViacheslav Ovsiienko
This patch removes the existing Tx datapath code as preparation step before introducing the new implementation. The following entities are being removed: - deprecated devargs support - tx_burst() routines - related PRM definitions - SQ configuration code - Tx routine selection code - incompatible Tx completion code The following devargs are deprecated and ignored: - "txq_inline" is going to be converted to "txq_inline_max" for compatibility issue - "tx_vec_en" - "txqs_max_vec" - "txq_mpw_hdr_dseg_en" - "txq_max_inline_len" is going to be converted to "txq_inline_mpw" for compatibility issue The deprecated devarg keys are recognized by PMD and ignored/converted to the new ones in order not to block device probing. Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Yongseok Koh <yskoh@mellanox.com>
2019-07-23net/mlx5: support IP-in-IP tunnelXiaoyu Min
Enabled IP-in-IP tunnel type support on DV/DR flow engine. This includes the following combination: - IPv4 over IPv4 - IPv4 over IPv6 - IPv6 over IPv4 - IPv6 over IPv6 MLX5 NIC supports IP-in-IP tunnel via FLEX Parser so need to make sure fw using FLEX Paser profile 0. mlxconfig -d <mst device> -y set FLEX_PARSER_PROFILE_ENABLE=0 The example testpmd commands would be: - Match on IPv4 over IPv4 packets and do inner RSS: testpmd> flow create 0 ingress pattern eth / ipv4 proto is 0x04 / ipv4 / udp / end actions rss level 2 queues 0 1 2 3 end / end - Match on IPv6 over IPv4 packets and do inner RSS: testpmd> flow create 0 ingress pattern eth / ipv4 proto is 0x29 / ipv6 / udp / end actions rss level 2 queues 0 1 2 3 end / end Signed-off-by: Xiaoyu Min <jackmin@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-07-08net/mlx5: support matching on ICMP/ICMP6Xiaoyu Min
On DV/DR flow engine, MLX5 can match on ICMP/ICMP6's code and type field via FLEX Parser, which can be enabled by config FW using FLEX Parser profile 2: mlxconfig -d <mst device> -y set FLEX_PARSER_PROFILE_ENABLE=2 The testpmd commands could be: testpmd> flow create 0 ingress pattern eth / ipv4 / icmp type is 8 code is 0 / end actions rss queues 0 1 end / end testpmd> flow create 0 ingress pattern eth / ipv6 / icmp6 type is 128 code is 0 / end actions rss queues 0 1 end / end Signed-off-by: Xiaoyu Min <jackmin@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-07-05net/mlx5: remove TCF supportMoti Haimovsky
This commit removes the support of configuring the device E-switch using TCF since it is now possible to configure it via DR (direct verbs rules), and by that to also remove the PMD dependency in libmnl. Signed-off-by: Moti Haimovsky <motih@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2019-06-14net/mlx5: add log file procedure for debug dataMatan Azrad
Add a global function in the PMD which dumps debug information to specific file. The data can be printed in hexadecimal format or as regular string. The number of debug files per PMD entity should be limited by a new PMD probe parameter called max_dump_files_num. The files will be created in the /var/log directory or in the current directory. Cc: stable@dpdk.org Signed-off-by: Matan Azrad <matan@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2019-05-13doc: update Mellanox guides and release notesOri Kam
This patch adds some missing features to Mellanox drivers release notes. It also updates the mlx5/mlx4 documentations. Fixes: d85b204b5dba ("doc: update release notes for Mellanox drivers") Signed-off-by: Ori Kam <orika@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2019-05-08doc: fix typo in mlx5 guideYongseok Koh
Fixes: 43e9d9794cde ("net/mlx5: support upstream rdma-core") Cc: stable@dpdk.org Signed-off-by: Yongseok Koh <yskoh@mellanox.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
2019-05-03doc: fix spelling reported by aspell in guidesJohn McNamara
Fix spelling errors in the guide docs. Signed-off-by: John McNamara <john.mcnamara@intel.com> Acked-by: Rami Rosen <ramirose@gmail.com>
2019-04-05net/mlx5: enable secondary process to register DMA memoryYongseok Koh
The Memory Region (MR) for DMA memory can't be created from secondary process due to lib/driver limitation. Whenever it is needed, secondary process can make a request to primary process through the EAL IPC channel (rte_mp_msg) which is established on initialization. Once a MR is created by primary process, it is immediately visible to secondary process because the MR list is global per a device. Thus, secondary process can look up the list after the request is successfully returned. Signed-off-by: Yongseok Koh <yskoh@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2019-04-05net/mlx5: add control of excessive memory pinning by kernelYongseok Koh
A new PMD parameter (mr_ext_memseg_en) is added to control extension of memseg when creating a MR. It is enabled by default. If enabled, mlx5_mr_create() tries to maximize the range of MR registration so that the LKey lookup tables on datapath become smaller and get the best performance. However, it may worsen memory utilization because registered memory is pinned by kernel driver. Even if a page in the extended chunk is freed, that doesn't become reusable until the entire memory is freed and the MR is destroyed. To make freed pages available immediately, this parameter has to be turned off but it could drop performance. Signed-off-by: Yongseok Koh <yskoh@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2019-04-05net/mlx5: fix external memory registrationYongseok Koh
Secondary process is not allowed to register MR due to a restriction of library and kernel driver. Fixes: 7e43a32ee060 ("net/mlx5: support externally allocated static memory") Cc: stable@dpdk.org Signed-off-by: Yongseok Koh <yskoh@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2019-04-05doc: fix typos in mlx5 guideDekel Peled
Correct typing mistakes: appiled ==> applied tarffic ==> traffic Fixes: 0280f2812284 ("doc: add mlx5 E-Switch VXLAN tunnels limitations") Cc: stable@dpdk.org Signed-off-by: Dekel Peled <dekelp@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2019-03-12mk: use linux and freebsd in config namesBruce Richardson
Rather than using linuxapp and bsdapp everywhere, we can change things to use the, more readable, terms "linux" and "freebsd" in our build configs. Rather than renaming the configs we can just duplicate the existing ones with the new names using symlinks, and use the new names exclusively internally. ["make showconfigs" also only shows the new names to keep the list short] The result is that backward compatibility is kept fully but any new builds or development can be done using the newer names, i.e. both "make config T=x86_64-native-linuxapp-gcc" and "T=x86_64-native-linux-gcc" work. Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
2019-01-31doc: add references to flow isolated mode in NICs guideThomas Monjalon
Some drivers (mlx, mvpp2, sfc) support the flow isolated mode, but the feature was not advertised. A reference to the feature description is added for each driver. Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2019-01-31doc: add Mellanox EN support in mlx5 guideYongseok Koh
Mellanox EN package is supported along with Mellanox OFED. Mellanox EN is distriubuted for Ethernet users. Signed-off-by: Yongseok Koh <yskoh@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2019-01-31doc: add mlx5 note for Bluefield build configurationYongseok Koh
Fixes: d14e4e976f65 ("config: add Mellanox BlueField armv8 SoC") Cc: stable@dpdk.org Signed-off-by: Yongseok Koh <yskoh@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2019-01-18net/mlx5: fix Rx packet paddingYongseok Koh
Rx packet padding is supposed to be set by an environment variable - MLX5_PMD_ENABLE_PADDING, but it has been missing for some time by mistake. Rather than using such a variable, a PMD parameter (rxq_pkt_pad_en) is added instead. Fixes: a1366b1a2be3 ("net/mlx5: add reference counter on DPDK Rx queues") Cc: stable@dpdk.org Signed-off-by: Yongseok Koh <yskoh@mellanox.com> Reviewed-by: Erez Ferber <erezf@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2019-01-14config: add static linkage of mlx dependencyThomas Monjalon
The libraries provided by rdma-core may be statically linked if enabling CONFIG_RTE_IBVERBS_LINK_STATIC in the make-based build. If CONFIG_RTE_BUILD_SHARED_LIB is disabled, the applications will embed the mlx PMDs with ibverbs and the mlx libraries. If CONFIG_RTE_BUILD_SHARED_LIB is enabled, the mlx PMDs will embed ibverbs and the mlx libraries. Support with meson may be added later. Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Acked-by: Shahaf Shuler <shahafs@mellanox.com>