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-rw-r--r--kernel/linux/kni/ethtool/ixgbe/ixgbe.h912
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/ixgbe_82598.c1281
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/ixgbe_82598.h29
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/ixgbe_82599.c2299
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/ixgbe_82599.h43
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/ixgbe_api.c1142
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/ixgbe_api.h153
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/ixgbe_common.c4067
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/ixgbe_common.h125
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/ixgbe_dcb.h153
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/ixgbe_ethtool.c2894
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/ixgbe_fcoe.h76
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/ixgbe_main.c2951
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/ixgbe_mbx.h90
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/ixgbe_osdep.h117
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/ixgbe_phy.c1832
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/ixgbe_phy.h122
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/ixgbe_type.h3239
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/ixgbe_x540.c922
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/ixgbe_x540.h43
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/kcompat.c1231
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/kcompat.h3144
-rw-r--r--kernel/linux/kni/ethtool/ixgbe/meson.build13
23 files changed, 0 insertions, 26878 deletions
diff --git a/kernel/linux/kni/ethtool/ixgbe/ixgbe.h b/kernel/linux/kni/ethtool/ixgbe/ixgbe.h
deleted file mode 100644
index cc15ec6..0000000
--- a/kernel/linux/kni/ethtool/ixgbe/ixgbe.h
+++ /dev/null
@@ -1,912 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*******************************************************************************
-
- Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2012 Intel Corporation.
-
- Contact Information:
- e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
- Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-
-#ifndef _IXGBE_H_
-#define _IXGBE_H_
-
-#ifndef IXGBE_NO_LRO
-#include <net/tcp.h>
-#endif
-
-#include <linux/pci.h>
-#include <linux/netdevice.h>
-#ifdef HAVE_IRQ_AFFINITY_HINT
-#include <linux/cpumask.h>
-#endif /* HAVE_IRQ_AFFINITY_HINT */
-#include <linux/vmalloc.h>
-
-#ifdef SIOCETHTOOL
-#include <linux/ethtool.h>
-#endif
-#ifdef NETIF_F_HW_VLAN_TX
-#include <linux/if_vlan.h>
-#endif
-#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
-#define IXGBE_DCA
-#include <linux/dca.h>
-#endif
-#include "ixgbe_dcb.h"
-
-#include "kcompat.h"
-
-#ifdef HAVE_SCTP
-#include <linux/sctp.h>
-#endif
-
-#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
-#define IXGBE_FCOE
-#include "ixgbe_fcoe.h"
-#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
-
-#if defined(CONFIG_PTP_1588_CLOCK) || defined(CONFIG_PTP_1588_CLOCK_MODULE)
-#define HAVE_IXGBE_PTP
-#endif
-
-#include "ixgbe_api.h"
-
-#define PFX "ixgbe: "
-#define DPRINTK(nlevel, klevel, fmt, args...) \
- ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
- printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
- __func__ , ## args)))
-
-/* TX/RX descriptor defines */
-#define IXGBE_DEFAULT_TXD 512
-#define IXGBE_DEFAULT_TX_WORK 256
-#define IXGBE_MAX_TXD 4096
-#define IXGBE_MIN_TXD 64
-
-#define IXGBE_DEFAULT_RXD 512
-#define IXGBE_DEFAULT_RX_WORK 256
-#define IXGBE_MAX_RXD 4096
-#define IXGBE_MIN_RXD 64
-
-
-/* flow control */
-#define IXGBE_MIN_FCRTL 0x40
-#define IXGBE_MAX_FCRTL 0x7FF80
-#define IXGBE_MIN_FCRTH 0x600
-#define IXGBE_MAX_FCRTH 0x7FFF0
-#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
-#define IXGBE_MIN_FCPAUSE 0
-#define IXGBE_MAX_FCPAUSE 0xFFFF
-
-/* Supported Rx Buffer Sizes */
-#define IXGBE_RXBUFFER_512 512 /* Used for packet split */
-#ifdef CONFIG_IXGBE_DISABLE_PACKET_SPLIT
-#define IXGBE_RXBUFFER_1536 1536
-#define IXGBE_RXBUFFER_2K 2048
-#define IXGBE_RXBUFFER_3K 3072
-#define IXGBE_RXBUFFER_4K 4096
-#define IXGBE_RXBUFFER_7K 7168
-#define IXGBE_RXBUFFER_8K 8192
-#define IXGBE_RXBUFFER_15K 15360
-#endif /* CONFIG_IXGBE_DISABLE_PACKET_SPLIT */
-#define IXGBE_MAX_RXBUFFER 16384 /* largest size for single descriptor */
-
-/*
- * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
- * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
- * this adds up to 512 bytes of extra data meaning the smallest allocation
- * we could have is 1K.
- * i.e. RXBUFFER_512 --> size-1024 slab
- */
-#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
-
-#define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
-
-/* How many Rx Buffers do we bundle into one write to the hardware ? */
-#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
-
-#define IXGBE_TX_FLAGS_CSUM (u32)(1)
-#define IXGBE_TX_FLAGS_HW_VLAN (u32)(1 << 1)
-#define IXGBE_TX_FLAGS_SW_VLAN (u32)(1 << 2)
-#define IXGBE_TX_FLAGS_TSO (u32)(1 << 3)
-#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 4)
-#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 5)
-#define IXGBE_TX_FLAGS_FSO (u32)(1 << 6)
-#define IXGBE_TX_FLAGS_TXSW (u32)(1 << 7)
-#define IXGBE_TX_FLAGS_TSTAMP (u32)(1 << 8)
-#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
-#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
-#define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
-#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
-
-#define IXGBE_MAX_RX_DESC_POLL 10
-
-#define IXGBE_MAX_VF_MC_ENTRIES 30
-#define IXGBE_MAX_VF_FUNCTIONS 64
-#define IXGBE_MAX_VFTA_ENTRIES 128
-#define MAX_EMULATION_MAC_ADDRS 16
-#define IXGBE_MAX_PF_MACVLANS 15
-#define IXGBE_82599_VF_DEVICE_ID 0x10ED
-#define IXGBE_X540_VF_DEVICE_ID 0x1515
-
-#ifdef CONFIG_PCI_IOV
-#define VMDQ_P(p) ((p) + adapter->num_vfs)
-#else
-#define VMDQ_P(p) (p)
-#endif
-
-#define UPDATE_VF_COUNTER_32bit(reg, last_counter, counter) \
- { \
- u32 current_counter = IXGBE_READ_REG(hw, reg); \
- if (current_counter < last_counter) \
- counter += 0x100000000LL; \
- last_counter = current_counter; \
- counter &= 0xFFFFFFFF00000000LL; \
- counter |= current_counter; \
- }
-
-#define UPDATE_VF_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
- { \
- u64 current_counter_lsb = IXGBE_READ_REG(hw, reg_lsb); \
- u64 current_counter_msb = IXGBE_READ_REG(hw, reg_msb); \
- u64 current_counter = (current_counter_msb << 32) | \
- current_counter_lsb; \
- if (current_counter < last_counter) \
- counter += 0x1000000000LL; \
- last_counter = current_counter; \
- counter &= 0xFFFFFFF000000000LL; \
- counter |= current_counter; \
- }
-
-struct vf_stats {
- u64 gprc;
- u64 gorc;
- u64 gptc;
- u64 gotc;
- u64 mprc;
-};
-
-struct vf_data_storage {
- unsigned char vf_mac_addresses[ETH_ALEN];
- u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
- u16 num_vf_mc_hashes;
- u16 default_vf_vlan_id;
- u16 vlans_enabled;
- bool clear_to_send;
- struct vf_stats vfstats;
- struct vf_stats last_vfstats;
- struct vf_stats saved_rst_vfstats;
- bool pf_set_mac;
- u16 pf_vlan; /* When set, guest VLAN config not allowed. */
- u16 pf_qos;
- u16 tx_rate;
- u16 vlan_count;
- u8 spoofchk_enabled;
- struct pci_dev *vfdev;
-};
-
-struct vf_macvlans {
- struct list_head l;
- int vf;
- bool free;
- bool is_macvlan;
- u8 vf_macvlan[ETH_ALEN];
-};
-
-#ifndef IXGBE_NO_LRO
-#define IXGBE_LRO_MAX 32 /*Maximum number of LRO descriptors*/
-#define IXGBE_LRO_GLOBAL 10
-
-struct ixgbe_lro_stats {
- u32 flushed;
- u32 coal;
-};
-
-/*
- * ixgbe_lro_header - header format to be aggregated by LRO
- * @iph: IP header without options
- * @tcp: TCP header
- * @ts: Optional TCP timestamp data in TCP options
- *
- * This structure relies on the check above that verifies that the header
- * is IPv4 and does not contain any options.
- */
-struct ixgbe_lrohdr {
- struct iphdr iph;
- struct tcphdr th;
- __be32 ts[0];
-};
-
-struct ixgbe_lro_list {
- struct sk_buff_head active;
- struct ixgbe_lro_stats stats;
-};
-
-#endif /* IXGBE_NO_LRO */
-#define IXGBE_MAX_TXD_PWR 14
-#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
-
-/* Tx Descriptors needed, worst case */
-#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
-#ifdef MAX_SKB_FRAGS
-#define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
-#else
-#define DESC_NEEDED 4
-#endif
-
-/* wrapper around a pointer to a socket buffer,
- * so a DMA handle can be stored along with the buffer */
-struct ixgbe_tx_buffer {
- union ixgbe_adv_tx_desc *next_to_watch;
- unsigned long time_stamp;
- struct sk_buff *skb;
- unsigned int bytecount;
- unsigned short gso_segs;
- __be16 protocol;
- DEFINE_DMA_UNMAP_ADDR(dma);
- DEFINE_DMA_UNMAP_LEN(len);
- u32 tx_flags;
-};
-
-struct ixgbe_rx_buffer {
- struct sk_buff *skb;
- dma_addr_t dma;
-#ifndef CONFIG_IXGBE_DISABLE_PACKET_SPLIT
- struct page *page;
- unsigned int page_offset;
-#endif
-};
-
-struct ixgbe_queue_stats {
- u64 packets;
- u64 bytes;
-};
-
-struct ixgbe_tx_queue_stats {
- u64 restart_queue;
- u64 tx_busy;
- u64 tx_done_old;
-};
-
-struct ixgbe_rx_queue_stats {
- u64 rsc_count;
- u64 rsc_flush;
- u64 non_eop_descs;
- u64 alloc_rx_page_failed;
- u64 alloc_rx_buff_failed;
- u64 csum_err;
-};
-
-enum ixgbe_ring_state_t {
- __IXGBE_TX_FDIR_INIT_DONE,
- __IXGBE_TX_DETECT_HANG,
- __IXGBE_HANG_CHECK_ARMED,
- __IXGBE_RX_RSC_ENABLED,
-#ifndef HAVE_NDO_SET_FEATURES
- __IXGBE_RX_CSUM_ENABLED,
-#endif
- __IXGBE_RX_CSUM_UDP_ZERO_ERR,
-#ifdef IXGBE_FCOE
- __IXGBE_RX_FCOE_BUFSZ,
-#endif
-};
-
-#define check_for_tx_hang(ring) \
- test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
-#define set_check_for_tx_hang(ring) \
- set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
-#define clear_check_for_tx_hang(ring) \
- clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
-#ifndef IXGBE_NO_HW_RSC
-#define ring_is_rsc_enabled(ring) \
- test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
-#else
-#define ring_is_rsc_enabled(ring) false
-#endif
-#define set_ring_rsc_enabled(ring) \
- set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
-#define clear_ring_rsc_enabled(ring) \
- clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
-#define netdev_ring(ring) (ring->netdev)
-#define ring_queue_index(ring) (ring->queue_index)
-
-
-struct ixgbe_ring {
- struct ixgbe_ring *next; /* pointer to next ring in q_vector */
- struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
- struct net_device *netdev; /* netdev ring belongs to */
- struct device *dev; /* device for DMA mapping */
- void *desc; /* descriptor ring memory */
- union {
- struct ixgbe_tx_buffer *tx_buffer_info;
- struct ixgbe_rx_buffer *rx_buffer_info;
- };
- unsigned long state;
- u8 __iomem *tail;
- dma_addr_t dma; /* phys. address of descriptor ring */
- unsigned int size; /* length in bytes */
-
- u16 count; /* amount of descriptors */
-
- u8 queue_index; /* needed for multiqueue queue management */
- u8 reg_idx; /* holds the special value that gets
- * the hardware register offset
- * associated with this ring, which is
- * different for DCB and RSS modes
- */
- u16 next_to_use;
- u16 next_to_clean;
-
- union {
-#ifdef CONFIG_IXGBE_DISABLE_PACKET_SPLIT
- u16 rx_buf_len;
-#else
- u16 next_to_alloc;
-#endif
- struct {
- u8 atr_sample_rate;
- u8 atr_count;
- };
- };
-
- u8 dcb_tc;
- struct ixgbe_queue_stats stats;
- union {
- struct ixgbe_tx_queue_stats tx_stats;
- struct ixgbe_rx_queue_stats rx_stats;
- };
-} ____cacheline_internodealigned_in_smp;
-
-enum ixgbe_ring_f_enum {
- RING_F_NONE = 0,
- RING_F_VMDQ, /* SR-IOV uses the same ring feature */
- RING_F_RSS,
- RING_F_FDIR,
-#ifdef IXGBE_FCOE
- RING_F_FCOE,
-#endif /* IXGBE_FCOE */
- RING_F_ARRAY_SIZE /* must be last in enum set */
-};
-
-#define IXGBE_MAX_DCB_INDICES 8
-#define IXGBE_MAX_RSS_INDICES 16
-#define IXGBE_MAX_VMDQ_INDICES 64
-#define IXGBE_MAX_FDIR_INDICES 64
-#ifdef IXGBE_FCOE
-#define IXGBE_MAX_FCOE_INDICES 8
-#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
-#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
-#else
-#define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
-#define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
-#endif /* IXGBE_FCOE */
-struct ixgbe_ring_feature {
- int indices;
- int mask;
-};
-
-#ifndef CONFIG_IXGBE_DISABLE_PACKET_SPLIT
-/*
- * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
- * this is twice the size of a half page we need to double the page order
- * for FCoE enabled Rx queues.
- */
-#if defined(IXGBE_FCOE) && (PAGE_SIZE < 8192)
-static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
-{
- return test_bit(__IXGBE_RX_FCOE_BUFSZ, &ring->state) ? 1 : 0;
-}
-#else
-#define ixgbe_rx_pg_order(_ring) 0
-#endif
-#define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
-#define ixgbe_rx_bufsz(_ring) ((PAGE_SIZE / 2) << ixgbe_rx_pg_order(_ring))
-
-#endif
-struct ixgbe_ring_container {
- struct ixgbe_ring *ring; /* pointer to linked list of rings */
- unsigned int total_bytes; /* total bytes processed this int */
- unsigned int total_packets; /* total packets processed this int */
- u16 work_limit; /* total work allowed per interrupt */
- u8 count; /* total number of rings in vector */
- u8 itr; /* current ITR setting for ring */
-};
-
-/* iterator for handling rings in ring container */
-#define ixgbe_for_each_ring(pos, head) \
- for (pos = (head).ring; pos != NULL; pos = pos->next)
-
-#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
- ? 8 : 1)
-#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
-
-/* MAX_MSIX_Q_VECTORS of these are allocated,
- * but we only use one per queue-specific vector.
- */
-struct ixgbe_q_vector {
- struct ixgbe_adapter *adapter;
- int cpu; /* CPU for DCA */
- u16 v_idx; /* index of q_vector within array, also used for
- * finding the bit in EICR and friends that
- * represents the vector for this ring */
- u16 itr; /* Interrupt throttle rate written to EITR */
- struct ixgbe_ring_container rx, tx;
-
-#ifdef CONFIG_IXGBE_NAPI
- struct napi_struct napi;
-#endif
-#ifndef HAVE_NETDEV_NAPI_LIST
- struct net_device poll_dev;
-#endif
-#ifdef HAVE_IRQ_AFFINITY_HINT
- cpumask_t affinity_mask;
-#endif
-#ifndef IXGBE_NO_LRO
- struct ixgbe_lro_list lrolist; /* LRO list for queue vector*/
-#endif
- int numa_node;
- char name[IFNAMSIZ + 9];
-
- /* for dynamic allocation of rings associated with this q_vector */
- struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
-};
-
-/*
- * microsecond values for various ITR rates shifted by 2 to fit itr register
- * with the first 3 bits reserved 0
- */
-#define IXGBE_MIN_RSC_ITR 24
-#define IXGBE_100K_ITR 40
-#define IXGBE_20K_ITR 200
-#define IXGBE_16K_ITR 248
-#define IXGBE_10K_ITR 400
-#define IXGBE_8K_ITR 500
-
-/* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
-static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
- const u32 stat_err_bits)
-{
- return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
-}
-
-/* ixgbe_desc_unused - calculate if we have unused descriptors */
-static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
-{
- u16 ntc = ring->next_to_clean;
- u16 ntu = ring->next_to_use;
-
- return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
-}
-
-#define IXGBE_RX_DESC(R, i) \
- (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
-#define IXGBE_TX_DESC(R, i) \
- (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
-#define IXGBE_TX_CTXTDESC(R, i) \
- (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
-
-#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
-#ifdef IXGBE_FCOE
-/* use 3K as the baby jumbo frame size for FCoE */
-#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
-#endif /* IXGBE_FCOE */
-
-#define TCP_TIMER_VECTOR 0
-#define OTHER_VECTOR 1
-#define NON_Q_VECTORS (OTHER_VECTOR + TCP_TIMER_VECTOR)
-
-#define IXGBE_MAX_MSIX_Q_VECTORS_82599 64
-#define IXGBE_MAX_MSIX_Q_VECTORS_82598 16
-
-struct ixgbe_mac_addr {
- u8 addr[ETH_ALEN];
- u16 queue;
- u16 state; /* bitmask */
-};
-#define IXGBE_MAC_STATE_DEFAULT 0x1
-#define IXGBE_MAC_STATE_MODIFIED 0x2
-#define IXGBE_MAC_STATE_IN_USE 0x4
-
-#ifdef IXGBE_PROCFS
-struct ixgbe_therm_proc_data {
- struct ixgbe_hw *hw;
- struct ixgbe_thermal_diode_data *sensor_data;
-};
-
-#endif /* IXGBE_PROCFS */
-
-/*
- * Only for array allocations in our adapter struct. On 82598, there will be
- * unused entries in the array, but that's not a big deal. Also, in 82599,
- * we can actually assign 64 queue vectors based on our extended-extended
- * interrupt registers. This is different than 82598, which is limited to 16.
- */
-#define MAX_MSIX_Q_VECTORS IXGBE_MAX_MSIX_Q_VECTORS_82599
-#define MAX_MSIX_COUNT IXGBE_MAX_MSIX_VECTORS_82599
-
-#define MIN_MSIX_Q_VECTORS 1
-#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
-
-/* default to trying for four seconds */
-#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
-
-/* board specific private data structure */
-struct ixgbe_adapter {
-#ifdef NETIF_F_HW_VLAN_TX
-#ifdef HAVE_VLAN_RX_REGISTER
- struct vlan_group *vlgrp; /* must be first, see ixgbe_receive_skb */
-#else
- unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
-#endif
-#endif /* NETIF_F_HW_VLAN_TX */
- /* OS defined structs */
- struct net_device *netdev;
- struct pci_dev *pdev;
-
- unsigned long state;
-
- /* Some features need tri-state capability,
- * thus the additional *_CAPABLE flags.
- */
- u32 flags;
-#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 0)
-#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1)
-#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 2)
-#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3)
-#ifndef IXGBE_NO_LLI
-#define IXGBE_FLAG_LLI_PUSH (u32)(1 << 4)
-#endif
-#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 8)
-#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
-#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 9)
-#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 10)
-#define IXGBE_FLAG_DCA_ENABLED_DATA (u32)(1 << 11)
-#else
-#define IXGBE_FLAG_DCA_ENABLED (u32)0
-#define IXGBE_FLAG_DCA_CAPABLE (u32)0
-#define IXGBE_FLAG_DCA_ENABLED_DATA (u32)0
-#endif
-#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 12)
-#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 13)
-#define IXGBE_FLAG_DCB_CAPABLE (u32)(1 << 14)
-#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 15)
-#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 16)
-#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 18)
-#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 19)
-#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 20)
-#define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 21)
-#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 22)
-#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 23)
-#ifdef IXGBE_FCOE
-#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 24)
-#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 25)
-#endif /* IXGBE_FCOE */
-#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 26)
-#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 27)
-#define IXGBE_FLAG_SRIOV_REPLICATION_ENABLE (u32)(1 << 28)
-#define IXGBE_FLAG_SRIOV_L2SWITCH_ENABLE (u32)(1 << 29)
-#define IXGBE_FLAG_SRIOV_L2LOOPBACK_ENABLE (u32)(1 << 30)
-#define IXGBE_FLAG_RX_BB_CAPABLE (u32)(1 << 31)
-
- u32 flags2;
-#ifndef IXGBE_NO_HW_RSC
-#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
-#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
-#else
-#define IXGBE_FLAG2_RSC_CAPABLE 0
-#define IXGBE_FLAG2_RSC_ENABLED 0
-#endif
-#define IXGBE_FLAG2_VMDQ_DEFAULT_OVERRIDE (u32)(1 << 2)
-#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 4)
-#define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 5)
-#define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 6)
-#define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 7)
-#define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 8)
-#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 9)
-#define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 10)
-#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 11)
-#define IXGBE_FLAG2_OVERFLOW_CHECK_ENABLED (u32)(1 << 12)
-
- /* Tx fast path data */
- int num_tx_queues;
- u16 tx_itr_setting;
- u16 tx_work_limit;
-
- /* Rx fast path data */
- int num_rx_queues;
- u16 rx_itr_setting;
- u16 rx_work_limit;
-
- /* TX */
- struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
-
- u64 restart_queue;
- u64 lsc_int;
- u32 tx_timeout_count;
-
- /* RX */
- struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
- int num_rx_pools; /* == num_rx_queues in 82598 */
- int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
- u64 hw_csum_rx_error;
- u64 hw_rx_no_dma_resources;
- u64 rsc_total_count;
- u64 rsc_total_flush;
- u64 non_eop_descs;
-#ifndef CONFIG_IXGBE_NAPI
- u64 rx_dropped_backlog; /* count drops from rx intr handler */
-#endif
- u32 alloc_rx_page_failed;
- u32 alloc_rx_buff_failed;
-
- struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
-
-#ifdef HAVE_DCBNL_IEEE
- struct ieee_pfc *ixgbe_ieee_pfc;
- struct ieee_ets *ixgbe_ieee_ets;
-#endif
- struct ixgbe_dcb_config dcb_cfg;
- struct ixgbe_dcb_config temp_dcb_cfg;
- u8 dcb_set_bitmap;
- u8 dcbx_cap;
-#ifndef HAVE_MQPRIO
- u8 tc;
-#endif
- enum ixgbe_fc_mode last_lfc_mode;
-
- int num_msix_vectors;
- int max_msix_q_vectors; /* true count of q_vectors for device */
- struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
- struct msix_entry *msix_entries;
-
-#ifndef HAVE_NETDEV_STATS_IN_NETDEV
- struct net_device_stats net_stats;
-#endif
-#ifndef IXGBE_NO_LRO
- struct ixgbe_lro_stats lro_stats;
-#endif
-
-#ifdef ETHTOOL_TEST
- u32 test_icr;
- struct ixgbe_ring test_tx_ring;
- struct ixgbe_ring test_rx_ring;
-#endif
-
- /* structs defined in ixgbe_hw.h */
- struct ixgbe_hw hw;
- u16 msg_enable;
- struct ixgbe_hw_stats stats;
-#ifndef IXGBE_NO_LLI
- u32 lli_port;
- u32 lli_size;
- u32 lli_etype;
- u32 lli_vlan_pri;
-#endif /* IXGBE_NO_LLI */
-
- u32 *config_space;
- u64 tx_busy;
- unsigned int tx_ring_count;
- unsigned int rx_ring_count;
-
- u32 link_speed;
- bool link_up;
- unsigned long link_check_timeout;
-
- struct timer_list service_timer;
- struct work_struct service_task;
-
- struct hlist_head fdir_filter_list;
- unsigned long fdir_overflow; /* number of times ATR was backed off */
- union ixgbe_atr_input fdir_mask;
- int fdir_filter_count;
- u32 fdir_pballoc;
- u32 atr_sample_rate;
- spinlock_t fdir_perfect_lock;
-
-#ifdef IXGBE_FCOE
- struct ixgbe_fcoe fcoe;
-#endif /* IXGBE_FCOE */
- u32 wol;
-
- u16 bd_number;
-
- char eeprom_id[32];
- u16 eeprom_cap;
- bool netdev_registered;
- u32 interrupt_event;
-#ifdef HAVE_ETHTOOL_SET_PHYS_ID
- u32 led_reg;
-#endif
-
- DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
- unsigned int num_vfs;
- struct vf_data_storage *vfinfo;
- int vf_rate_link_speed;
- struct vf_macvlans vf_mvs;
- struct vf_macvlans *mv_list;
-#ifdef CONFIG_PCI_IOV
- u32 timer_event_accumulator;
- u32 vferr_refcount;
-#endif
- struct ixgbe_mac_addr *mac_table;
-#ifdef IXGBE_SYSFS
- struct kobject *info_kobj;
- struct kobject *therm_kobj[IXGBE_MAX_SENSORS];
-#else /* IXGBE_SYSFS */
-#ifdef IXGBE_PROCFS
- struct proc_dir_entry *eth_dir;
- struct proc_dir_entry *info_dir;
- struct proc_dir_entry *therm_dir[IXGBE_MAX_SENSORS];
- struct ixgbe_therm_proc_data therm_data[IXGBE_MAX_SENSORS];
-#endif /* IXGBE_PROCFS */
-#endif /* IXGBE_SYSFS */
-};
-
-struct ixgbe_fdir_filter {
- struct hlist_node fdir_node;
- union ixgbe_atr_input filter;
- u16 sw_idx;
- u16 action;
-};
-
-enum ixgbe_state_t {
- __IXGBE_TESTING,
- __IXGBE_RESETTING,
- __IXGBE_DOWN,
- __IXGBE_SERVICE_SCHED,
- __IXGBE_IN_SFP_INIT,
-};
-
-struct ixgbe_cb {
-#ifdef CONFIG_IXGBE_DISABLE_PACKET_SPLIT
- union { /* Union defining head/tail partner */
- struct sk_buff *head;
- struct sk_buff *tail;
- };
-#endif
- dma_addr_t dma;
-#ifndef IXGBE_NO_LRO
- __be32 tsecr; /* timestamp echo response */
- u32 tsval; /* timestamp value in host order */
- u32 next_seq; /* next expected sequence number */
- u16 free; /* 65521 minus total size */
- u16 mss; /* size of data portion of packet */
-#endif /* IXGBE_NO_LRO */
-#ifdef HAVE_VLAN_RX_REGISTER
- u16 vid; /* VLAN tag */
-#endif
- u16 append_cnt; /* number of skb's appended */
-#ifndef CONFIG_IXGBE_DISABLE_PACKET_SPLIT
- bool page_released;
-#endif
-};
-#define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
-
-#ifdef IXGBE_SYSFS
-void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
-int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
-#endif /* IXGBE_SYSFS */
-#ifdef IXGBE_PROCFS
-void ixgbe_procfs_exit(struct ixgbe_adapter *adapter);
-int ixgbe_procfs_init(struct ixgbe_adapter *adapter);
-int ixgbe_procfs_topdir_init(void);
-void ixgbe_procfs_topdir_exit(void);
-#endif /* IXGBE_PROCFS */
-
-extern struct dcbnl_rtnl_ops dcbnl_ops;
-extern int ixgbe_copy_dcb_cfg(struct ixgbe_adapter *adapter, int tc_max);
-
-extern u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 index);
-
-/* needed by ixgbe_main.c */
-extern int ixgbe_validate_mac_addr(u8 *mc_addr);
-extern void ixgbe_check_options(struct ixgbe_adapter *adapter);
-extern void ixgbe_assign_netdev_ops(struct net_device *netdev);
-
-/* needed by ixgbe_ethtool.c */
-extern char ixgbe_driver_name[];
-extern const char ixgbe_driver_version[];
-
-extern void ixgbe_up(struct ixgbe_adapter *adapter);
-extern void ixgbe_down(struct ixgbe_adapter *adapter);
-extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
-extern void ixgbe_reset(struct ixgbe_adapter *adapter);
-extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
-extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
-extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
-extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
-extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
-extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,
- struct ixgbe_ring *);
-extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,
- struct ixgbe_ring *);
-extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
-extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
-extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
-extern bool ixgbe_is_ixgbe(struct pci_dev *pcidev);
-extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
- struct ixgbe_adapter *,
- struct ixgbe_ring *);
-extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
- struct ixgbe_tx_buffer *);
-extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
-extern void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
- struct ixgbe_ring *);
-extern void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
- struct ixgbe_ring *);
-extern void ixgbe_set_rx_mode(struct net_device *netdev);
-extern int ixgbe_write_mc_addr_list(struct net_device *netdev);
-extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
-#ifdef IXGBE_FCOE
-extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
-#endif /* IXGBE_FCOE */
-extern void ixgbe_do_reset(struct net_device *netdev);
-extern void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector);
-extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
- struct ixgbe_ring *);
-extern void ixgbe_vlan_stripping_enable(struct ixgbe_adapter *adapter);
-extern void ixgbe_vlan_stripping_disable(struct ixgbe_adapter *adapter);
-#ifdef ETHTOOL_OPS_COMPAT
-extern int ethtool_ioctl(struct ifreq *ifr);
-#endif
-
-#ifdef IXGBE_FCOE
-extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
-extern int ixgbe_fso(struct ixgbe_ring *tx_ring,
- struct ixgbe_tx_buffer *first,
- u8 *hdr_len);
-extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
-extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
- union ixgbe_adv_rx_desc *rx_desc,
- struct sk_buff *skb);
-extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
- struct scatterlist *sgl, unsigned int sgc);
-#ifdef HAVE_NETDEV_OPS_FCOE_DDP_TARGET
-extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
- struct scatterlist *sgl, unsigned int sgc);
-#endif /* HAVE_NETDEV_OPS_FCOE_DDP_TARGET */
-extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
-#ifdef HAVE_NETDEV_OPS_FCOE_ENABLE
-extern int ixgbe_fcoe_enable(struct net_device *netdev);
-extern int ixgbe_fcoe_disable(struct net_device *netdev);
-#endif /* HAVE_NETDEV_OPS_FCOE_ENABLE */
-#ifdef CONFIG_DCB
-#ifdef HAVE_DCBNL_OPS_GETAPP
-extern u8 ixgbe_fcoe_getapp(struct net_device *netdev);
-#endif /* HAVE_DCBNL_OPS_GETAPP */
-extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
-#endif /* CONFIG_DCB */
-#ifdef HAVE_NETDEV_OPS_FCOE_GETWWN
-extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
-#endif
-#endif /* IXGBE_FCOE */
-
-#ifdef CONFIG_DCB
-#ifdef HAVE_DCBNL_IEEE
-s32 ixgbe_dcb_hw_ets(struct ixgbe_hw *hw, struct ieee_ets *ets, int max_frame);
-#endif /* HAVE_DCBNL_IEEE */
-#endif /* CONFIG_DCB */
-
-extern void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring);
-#ifndef ETHTOOL_GLINKSETTINGS
-extern int ixgbe_get_settings(struct net_device *netdev,
- struct ethtool_cmd *ecmd);
-#endif
-extern int ixgbe_write_uc_addr_list(struct ixgbe_adapter *adapter,
- struct net_device *netdev, unsigned int vfn);
-extern void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter);
-extern int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
- u8 *addr, u16 queue);
-extern int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
- u8 *addr, u16 queue);
-extern int ixgbe_available_rars(struct ixgbe_adapter *adapter);
-#ifndef HAVE_VLAN_RX_REGISTER
-extern void ixgbe_vlan_mode(struct net_device *, u32);
-#endif
-#ifndef ixgbe_get_netdev_tc_txq
-#define ixgbe_get_netdev_tc_txq(dev, tc) (&dev->tc_to_txq[tc])
-#endif
-extern void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
-#endif /* _IXGBE_H_ */
diff --git a/kernel/linux/kni/ethtool/ixgbe/ixgbe_82598.c b/kernel/linux/kni/ethtool/ixgbe/ixgbe_82598.c
deleted file mode 100644
index 242de67..0000000
--- a/kernel/linux/kni/ethtool/ixgbe/ixgbe_82598.c
+++ /dev/null
@@ -1,1281 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*******************************************************************************
-
- Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2012 Intel Corporation.
-
- Contact Information:
- e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
- Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-
-#include "ixgbe_type.h"
-#include "ixgbe_82598.h"
-#include "ixgbe_api.h"
-#include "ixgbe_common.h"
-#include "ixgbe_phy.h"
-
-static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed,
- bool *autoneg);
-static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
-static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
- bool autoneg_wait_to_complete);
-static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed, bool *link_up,
- bool link_up_wait_to_complete);
-static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
- ixgbe_link_speed speed,
- bool autoneg,
- bool autoneg_wait_to_complete);
-static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
- ixgbe_link_speed speed,
- bool autoneg,
- bool autoneg_wait_to_complete);
-static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
-static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
-static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
-static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
- u32 headroom, int strategy);
-
-/**
- * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
- * @hw: pointer to the HW structure
- *
- * The defaults for 82598 should be in the range of 50us to 50ms,
- * however the hardware default for these parts is 500us to 1ms which is less
- * than the 10ms recommended by the pci-e spec. To address this we need to
- * increase the value to either 10ms to 250ms for capability version 1 config,
- * or 16ms to 55ms for version 2.
- **/
-void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
-{
- u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
- u16 pcie_devctl2;
-
- /* only take action if timeout value is defaulted to 0 */
- if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
- goto out;
-
- /*
- * if capababilities version is type 1 we can write the
- * timeout of 10ms to 250ms through the GCR register
- */
- if (!(gcr & IXGBE_GCR_CAP_VER2)) {
- gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
- goto out;
- }
-
- /*
- * for version 2 capabilities we need to write the config space
- * directly in order to set the completion timeout value for
- * 16ms to 55ms
- */
- pcie_devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
- pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
- IXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
-out:
- /* disable completion timeout resend */
- gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
- IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
-}
-
-/**
- * ixgbe_init_ops_82598 - Inits func ptrs and MAC type
- * @hw: pointer to hardware structure
- *
- * Initialize the function pointers and assign the MAC type for 82598.
- * Does not touch the hardware.
- **/
-s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
-{
- struct ixgbe_mac_info *mac = &hw->mac;
- struct ixgbe_phy_info *phy = &hw->phy;
- s32 ret_val;
-
- ret_val = ixgbe_init_phy_ops_generic(hw);
- ret_val = ixgbe_init_ops_generic(hw);
-
- /* PHY */
- phy->ops.init = &ixgbe_init_phy_ops_82598;
-
- /* MAC */
- mac->ops.start_hw = &ixgbe_start_hw_82598;
- mac->ops.reset_hw = &ixgbe_reset_hw_82598;
- mac->ops.get_media_type = &ixgbe_get_media_type_82598;
- mac->ops.get_supported_physical_layer =
- &ixgbe_get_supported_physical_layer_82598;
- mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598;
- mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598;
- mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598;
-
- /* RAR, Multicast, VLAN */
- mac->ops.set_vmdq = &ixgbe_set_vmdq_82598;
- mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598;
- mac->ops.set_vfta = &ixgbe_set_vfta_82598;
- mac->ops.set_vlvf = NULL;
- mac->ops.clear_vfta = &ixgbe_clear_vfta_82598;
-
- /* Flow Control */
- mac->ops.fc_enable = &ixgbe_fc_enable_82598;
-
- mac->mcft_size = 128;
- mac->vft_size = 128;
- mac->num_rar_entries = 16;
- mac->rx_pb_size = 512;
- mac->max_tx_queues = 32;
- mac->max_rx_queues = 64;
- mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
-
- /* SFP+ Module */
- phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
-
- /* Link */
- mac->ops.check_link = &ixgbe_check_mac_link_82598;
- mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
- mac->ops.flap_tx_laser = NULL;
- mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82598;
- mac->ops.setup_rxpba = &ixgbe_set_rxpba_82598;
-
- /* Manageability interface */
- mac->ops.set_fw_drv_ver = NULL;
-
- return ret_val;
-}
-
-/**
- * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
- * @hw: pointer to hardware structure
- *
- * Initialize any function pointers that were not able to be
- * set during init_shared_code because the PHY/SFP type was
- * not known. Perform the SFP init if necessary.
- *
- **/
-s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
-{
- struct ixgbe_mac_info *mac = &hw->mac;
- struct ixgbe_phy_info *phy = &hw->phy;
- s32 ret_val = 0;
- u16 list_offset, data_offset;
-
- /* Identify the PHY */
- phy->ops.identify(hw);
-
- /* Overwrite the link function pointers if copper PHY */
- if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
- mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
- mac->ops.get_link_capabilities =
- &ixgbe_get_copper_link_capabilities_generic;
- }
-
- switch (hw->phy.type) {
- case ixgbe_phy_tn:
- phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
- phy->ops.check_link = &ixgbe_check_phy_link_tnx;
- phy->ops.get_firmware_version =
- &ixgbe_get_phy_firmware_version_tnx;
- break;
- case ixgbe_phy_nl:
- phy->ops.reset = &ixgbe_reset_phy_nl;
-
- /* Call SFP+ identify routine to get the SFP+ module type */
- ret_val = phy->ops.identify_sfp(hw);
- if (ret_val != 0)
- goto out;
- else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
- ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
- goto out;
- }
-
- /* Check to see if SFP+ module is supported */
- ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
- &list_offset,
- &data_offset);
- if (ret_val != 0) {
- ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
- goto out;
- }
- break;
- default:
- break;
- }
-
-out:
- return ret_val;
-}
-
-/**
- * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
- * @hw: pointer to hardware structure
- *
- * Starts the hardware using the generic start_hw function.
- * Disables relaxed ordering Then set pcie completion timeout
- *
- **/
-s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
-{
- u32 regval;
- u32 i;
- s32 ret_val = 0;
-
- ret_val = ixgbe_start_hw_generic(hw);
-
- /* Disable relaxed ordering */
- for (i = 0; ((i < hw->mac.max_tx_queues) &&
- (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
- regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
- regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
- IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
- }
-
- for (i = 0; ((i < hw->mac.max_rx_queues) &&
- (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
- regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
- regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
- IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
- IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
- }
-
- /* set the completion timeout for interface */
- if (ret_val == 0)
- ixgbe_set_pcie_completion_timeout(hw);
-
- return ret_val;
-}
-
-/**
- * ixgbe_get_link_capabilities_82598 - Determines link capabilities
- * @hw: pointer to hardware structure
- * @speed: pointer to link speed
- * @autoneg: boolean auto-negotiation value
- *
- * Determines the link capabilities by reading the AUTOC register.
- **/
-static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed,
- bool *autoneg)
-{
- s32 status = 0;
- u32 autoc = 0;
-
- /*
- * Determine link capabilities based on the stored value of AUTOC,
- * which represents EEPROM defaults. If AUTOC value has not been
- * stored, use the current register value.
- */
- if (hw->mac.orig_link_settings_stored)
- autoc = hw->mac.orig_autoc;
- else
- autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
-
- switch (autoc & IXGBE_AUTOC_LMS_MASK) {
- case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
- *speed = IXGBE_LINK_SPEED_1GB_FULL;
- *autoneg = false;
- break;
-
- case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
- *speed = IXGBE_LINK_SPEED_10GB_FULL;
- *autoneg = false;
- break;
-
- case IXGBE_AUTOC_LMS_1G_AN:
- *speed = IXGBE_LINK_SPEED_1GB_FULL;
- *autoneg = true;
- break;
-
- case IXGBE_AUTOC_LMS_KX4_AN:
- case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
- *speed = IXGBE_LINK_SPEED_UNKNOWN;
- if (autoc & IXGBE_AUTOC_KX4_SUPP)
- *speed |= IXGBE_LINK_SPEED_10GB_FULL;
- if (autoc & IXGBE_AUTOC_KX_SUPP)
- *speed |= IXGBE_LINK_SPEED_1GB_FULL;
- *autoneg = true;
- break;
-
- default:
- status = IXGBE_ERR_LINK_SETUP;
- break;
- }
-
- return status;
-}
-
-/**
- * ixgbe_get_media_type_82598 - Determines media type
- * @hw: pointer to hardware structure
- *
- * Returns the media type (fiber, copper, backplane)
- **/
-static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
-{
- enum ixgbe_media_type media_type;
-
- /* Detect if there is a copper PHY attached. */
- switch (hw->phy.type) {
- case ixgbe_phy_cu_unknown:
- case ixgbe_phy_tn:
- media_type = ixgbe_media_type_copper;
- goto out;
- default:
- break;
- }
-
- /* Media type for I82598 is based on device ID */
- switch (hw->device_id) {
- case IXGBE_DEV_ID_82598:
- case IXGBE_DEV_ID_82598_BX:
- /* Default device ID is mezzanine card KX/KX4 */
- media_type = ixgbe_media_type_backplane;
- break;
- case IXGBE_DEV_ID_82598AF_DUAL_PORT:
- case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
- case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
- case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
- case IXGBE_DEV_ID_82598EB_XF_LR:
- case IXGBE_DEV_ID_82598EB_SFP_LOM:
- media_type = ixgbe_media_type_fiber;
- break;
- case IXGBE_DEV_ID_82598EB_CX4:
- case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
- media_type = ixgbe_media_type_cx4;
- break;
- case IXGBE_DEV_ID_82598AT:
- case IXGBE_DEV_ID_82598AT2:
- media_type = ixgbe_media_type_copper;
- break;
- default:
- media_type = ixgbe_media_type_unknown;
- break;
- }
-out:
- return media_type;
-}
-
-/**
- * ixgbe_fc_enable_82598 - Enable flow control
- * @hw: pointer to hardware structure
- *
- * Enable flow control according to the current settings.
- **/
-s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)
-{
- s32 ret_val = 0;
- u32 fctrl_reg;
- u32 rmcs_reg;
- u32 reg;
- u32 fcrtl, fcrth;
- u32 link_speed = 0;
- int i;
- bool link_up;
-
- /* Validate the water mark configuration */
- if (!hw->fc.pause_time) {
- ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
- goto out;
- }
-
- /* Low water mark of zero causes XOFF floods */
- for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
- if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
- hw->fc.high_water[i]) {
- if (!hw->fc.low_water[i] ||
- hw->fc.low_water[i] >= hw->fc.high_water[i]) {
- hw_dbg(hw, "Invalid water mark configuration\n");
- ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
- goto out;
- }
- }
- }
-
- /*
- * On 82598 having Rx FC on causes resets while doing 1G
- * so if it's on turn it off once we know link_speed. For
- * more details see 82598 Specification update.
- */
- hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
- if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
- switch (hw->fc.requested_mode) {
- case ixgbe_fc_full:
- hw->fc.requested_mode = ixgbe_fc_tx_pause;
- break;
- case ixgbe_fc_rx_pause:
- hw->fc.requested_mode = ixgbe_fc_none;
- break;
- default:
- /* no change */
- break;
- }
- }
-
- /* Negotiate the fc mode to use */
- ixgbe_fc_autoneg(hw);
-
- /* Disable any previous flow control settings */
- fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
- fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
-
- rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
- rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
-
- /*
- * The possible values of fc.current_mode are:
- * 0: Flow control is completely disabled
- * 1: Rx flow control is enabled (we can receive pause frames,
- * but not send pause frames).
- * 2: Tx flow control is enabled (we can send pause frames but
- * we do not support receiving pause frames).
- * 3: Both Rx and Tx flow control (symmetric) are enabled.
- * other: Invalid.
- */
- switch (hw->fc.current_mode) {
- case ixgbe_fc_none:
- /*
- * Flow control is disabled by software override or autoneg.
- * The code below will actually disable it in the HW.
- */
- break;
- case ixgbe_fc_rx_pause:
- /*
- * Rx Flow control is enabled and Tx Flow control is
- * disabled by software override. Since there really
- * isn't a way to advertise that we are capable of RX
- * Pause ONLY, we will advertise that we support both
- * symmetric and asymmetric Rx PAUSE. Later, we will
- * disable the adapter's ability to send PAUSE frames.
- */
- fctrl_reg |= IXGBE_FCTRL_RFCE;
- break;
- case ixgbe_fc_tx_pause:
- /*
- * Tx Flow control is enabled, and Rx Flow control is
- * disabled by software override.
- */
- rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
- break;
- case ixgbe_fc_full:
- /* Flow control (both Rx and Tx) is enabled by SW override. */
- fctrl_reg |= IXGBE_FCTRL_RFCE;
- rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
- break;
- default:
- hw_dbg(hw, "Flow control param set incorrectly\n");
- ret_val = IXGBE_ERR_CONFIG;
- goto out;
- break;
- }
-
- /* Set 802.3x based flow control settings. */
- fctrl_reg |= IXGBE_FCTRL_DPF;
- IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
- IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
-
- /* Set up and enable Rx high/low water mark thresholds, enable XON. */
- for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
- if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
- hw->fc.high_water[i]) {
- fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
- fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
- IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
- IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);
- } else {
- IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
- IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
- }
-
- }
-
- /* Configure pause time (2 TCs per register) */
- reg = hw->fc.pause_time * 0x00010001;
- for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
- IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
-
- /* Configure flow control refresh threshold value */
- IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
-
-out:
- return ret_val;
-}
-
-/**
- * ixgbe_start_mac_link_82598 - Configures MAC link settings
- * @hw: pointer to hardware structure
- *
- * Configures link settings based on values in the ixgbe_hw struct.
- * Restarts the link. Performs autonegotiation if needed.
- **/
-static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
- bool autoneg_wait_to_complete)
-{
- u32 autoc_reg;
- u32 links_reg;
- u32 i;
- s32 status = 0;
-
- /* Restart link */
- autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
- autoc_reg |= IXGBE_AUTOC_AN_RESTART;
- IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
-
- /* Only poll for autoneg to complete if specified to do so */
- if (autoneg_wait_to_complete) {
- if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
- IXGBE_AUTOC_LMS_KX4_AN ||
- (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
- IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
- links_reg = 0; /* Just in case Autoneg time = 0 */
- for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
- links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
- if (links_reg & IXGBE_LINKS_KX_AN_COMP)
- break;
- msleep(100);
- }
- if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
- status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
- hw_dbg(hw, "Autonegotiation did not complete.\n");
- }
- }
- }
-
- /* Add delay to filter out noises during initial link setup */
- msleep(50);
-
- return status;
-}
-
-/**
- * ixgbe_validate_link_ready - Function looks for phy link
- * @hw: pointer to hardware structure
- *
- * Function indicates success when phy link is available. If phy is not ready
- * within 5 seconds of MAC indicating link, the function returns error.
- **/
-static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)
-{
- u32 timeout;
- u16 an_reg;
-
- if (hw->device_id != IXGBE_DEV_ID_82598AT2)
- return 0;
-
- for (timeout = 0;
- timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
- hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg);
-
- if ((an_reg & IXGBE_MII_AUTONEG_COMPLETE) &&
- (an_reg & IXGBE_MII_AUTONEG_LINK_UP))
- break;
-
- msleep(100);
- }
-
- if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {
- hw_dbg(hw, "Link was indicated but link is down\n");
- return IXGBE_ERR_LINK_SETUP;
- }
-
- return 0;
-}
-
-/**
- * ixgbe_check_mac_link_82598 - Get link/speed status
- * @hw: pointer to hardware structure
- * @speed: pointer to link speed
- * @link_up: true is link is up, false otherwise
- * @link_up_wait_to_complete: bool used to wait for link up or not
- *
- * Reads the links register to determine if link is up and the current speed
- **/
-static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed, bool *link_up,
- bool link_up_wait_to_complete)
-{
- u32 links_reg;
- u32 i;
- u16 link_reg, adapt_comp_reg;
-
- /*
- * SERDES PHY requires us to read link status from undocumented
- * register 0xC79F. Bit 0 set indicates link is up/ready; clear
- * indicates link down. OxC00C is read to check that the XAUI lanes
- * are active. Bit 0 clear indicates active; set indicates inactive.
- */
- if (hw->phy.type == ixgbe_phy_nl) {
- hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
- hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
- hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
- &adapt_comp_reg);
- if (link_up_wait_to_complete) {
- for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
- if ((link_reg & 1) &&
- ((adapt_comp_reg & 1) == 0)) {
- *link_up = true;
- break;
- } else {
- *link_up = false;
- }
- msleep(100);
- hw->phy.ops.read_reg(hw, 0xC79F,
- IXGBE_TWINAX_DEV,
- &link_reg);
- hw->phy.ops.read_reg(hw, 0xC00C,
- IXGBE_TWINAX_DEV,
- &adapt_comp_reg);
- }
- } else {
- if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
- *link_up = true;
- else
- *link_up = false;
- }
-
- if (*link_up == false)
- goto out;
- }
-
- links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
- if (link_up_wait_to_complete) {
- for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
- if (links_reg & IXGBE_LINKS_UP) {
- *link_up = true;
- break;
- } else {
- *link_up = false;
- }
- msleep(100);
- links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
- }
- } else {
- if (links_reg & IXGBE_LINKS_UP)
- *link_up = true;
- else
- *link_up = false;
- }
-
- if (links_reg & IXGBE_LINKS_SPEED)
- *speed = IXGBE_LINK_SPEED_10GB_FULL;
- else
- *speed = IXGBE_LINK_SPEED_1GB_FULL;
-
- if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == true) &&
- (ixgbe_validate_link_ready(hw) != 0))
- *link_up = false;
-
-out:
- return 0;
-}
-
-/**
- * ixgbe_setup_mac_link_82598 - Set MAC link speed
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg: true if autonegotiation enabled
- * @autoneg_wait_to_complete: true when waiting for completion is needed
- *
- * Set the link speed in the AUTOC register and restarts link.
- **/
-static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
- ixgbe_link_speed speed, bool autoneg,
- bool autoneg_wait_to_complete)
-{
- s32 status = 0;
- ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
- u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
- u32 autoc = curr_autoc;
- u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
-
- /* Check to see if speed passed in is supported. */
- ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
- speed &= link_capabilities;
-
- if (speed == IXGBE_LINK_SPEED_UNKNOWN)
- status = IXGBE_ERR_LINK_SETUP;
-
- /* Set KX4/KX support according to speed requested */
- else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
- link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
- autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
- if (speed & IXGBE_LINK_SPEED_10GB_FULL)
- autoc |= IXGBE_AUTOC_KX4_SUPP;
- if (speed & IXGBE_LINK_SPEED_1GB_FULL)
- autoc |= IXGBE_AUTOC_KX_SUPP;
- if (autoc != curr_autoc)
- IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
- }
-
- if (status == 0) {
- /*
- * Setup and restart the link based on the new values in
- * ixgbe_hw This will write the AUTOC register based on the new
- * stored values
- */
- status = ixgbe_start_mac_link_82598(hw,
- autoneg_wait_to_complete);
- }
-
- return status;
-}
-
-
-/**
- * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg: true if autonegotiation enabled
- * @autoneg_wait_to_complete: true if waiting is needed to complete
- *
- * Sets the link speed in the AUTOC register in the MAC and restarts link.
- **/
-static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
- ixgbe_link_speed speed,
- bool autoneg,
- bool autoneg_wait_to_complete)
-{
- s32 status;
-
- /* Setup the PHY according to input speed */
- status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
- autoneg_wait_to_complete);
- /* Set up MAC */
- ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
-
- return status;
-}
-
-/**
- * ixgbe_reset_hw_82598 - Performs hardware reset
- * @hw: pointer to hardware structure
- *
- * Resets the hardware by resetting the transmit and receive units, masks and
- * clears all interrupts, performing a PHY reset, and performing a link (MAC)
- * reset.
- **/
-static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
-{
- s32 status = 0;
- s32 phy_status = 0;
- u32 ctrl;
- u32 gheccr;
- u32 i;
- u32 autoc;
- u8 analog_val;
-
- /* Call adapter stop to disable tx/rx and clear interrupts */
- status = hw->mac.ops.stop_adapter(hw);
- if (status != 0)
- goto reset_hw_out;
-
- /*
- * Power up the Atlas Tx lanes if they are currently powered down.
- * Atlas Tx lanes are powered down for MAC loopback tests, but
- * they are not automatically restored on reset.
- */
- hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
- if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
- /* Enable Tx Atlas so packets can be transmitted again */
- hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
- &analog_val);
- analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
- hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
- analog_val);
-
- hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
- &analog_val);
- analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
- hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
- analog_val);
-
- hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
- &analog_val);
- analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
- hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
- analog_val);
-
- hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
- &analog_val);
- analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
- hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
- analog_val);
- }
-
- /* Reset PHY */
- if (hw->phy.reset_disable == false) {
- /* PHY ops must be identified and initialized prior to reset */
-
- /* Init PHY and function pointers, perform SFP setup */
- phy_status = hw->phy.ops.init(hw);
- if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
- goto reset_hw_out;
- if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
- goto mac_reset_top;
-
- hw->phy.ops.reset(hw);
- }
-
-mac_reset_top:
- /*
- * Issue global reset to the MAC. This needs to be a SW reset.
- * If link reset is used, it might reset the MAC when mng is using it
- */
- ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;
- IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
- IXGBE_WRITE_FLUSH(hw);
-
- /* Poll for reset bit to self-clear indicating reset is complete */
- for (i = 0; i < 10; i++) {
- udelay(1);
- ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
- if (!(ctrl & IXGBE_CTRL_RST))
- break;
- }
- if (ctrl & IXGBE_CTRL_RST) {
- status = IXGBE_ERR_RESET_FAILED;
- hw_dbg(hw, "Reset polling failed to complete.\n");
- }
-
- msleep(50);
-
- /*
- * Double resets are required for recovery from certain error
- * conditions. Between resets, it is necessary to stall to allow time
- * for any pending HW events to complete.
- */
- if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
- hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
- goto mac_reset_top;
- }
-
- gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
- gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
- IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
-
- /*
- * Store the original AUTOC value if it has not been
- * stored off yet. Otherwise restore the stored original
- * AUTOC value since the reset operation sets back to deaults.
- */
- autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
- if (hw->mac.orig_link_settings_stored == false) {
- hw->mac.orig_autoc = autoc;
- hw->mac.orig_link_settings_stored = true;
- } else if (autoc != hw->mac.orig_autoc) {
- IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
- }
-
- /* Store the permanent mac address */
- hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
-
- /*
- * Store MAC address from RAR0, clear receive address registers, and
- * clear the multicast table
- */
- hw->mac.ops.init_rx_addrs(hw);
-
-reset_hw_out:
- if (phy_status != 0)
- status = phy_status;
-
- return status;
-}
-
-/**
- * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
- * @hw: pointer to hardware struct
- * @rar: receive address register index to associate with a VMDq index
- * @vmdq: VMDq set index
- **/
-s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
-{
- u32 rar_high;
- u32 rar_entries = hw->mac.num_rar_entries;
-
- /* Make sure we are using a valid rar index range */
- if (rar >= rar_entries) {
- hw_dbg(hw, "RAR index %d is out of range.\n", rar);
- return IXGBE_ERR_INVALID_ARGUMENT;
- }
-
- rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
- rar_high &= ~IXGBE_RAH_VIND_MASK;
- rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
- IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
- return 0;
-}
-
-/**
- * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
- * @hw: pointer to hardware struct
- * @rar: receive address register index to associate with a VMDq index
- * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
- **/
-static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
-{
- u32 rar_high;
- u32 rar_entries = hw->mac.num_rar_entries;
-
-
- /* Make sure we are using a valid rar index range */
- if (rar >= rar_entries) {
- hw_dbg(hw, "RAR index %d is out of range.\n", rar);
- return IXGBE_ERR_INVALID_ARGUMENT;
- }
-
- rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
- if (rar_high & IXGBE_RAH_VIND_MASK) {
- rar_high &= ~IXGBE_RAH_VIND_MASK;
- IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
- }
-
- return 0;
-}
-
-/**
- * ixgbe_set_vfta_82598 - Set VLAN filter table
- * @hw: pointer to hardware structure
- * @vlan: VLAN id to write to VLAN filter
- * @vind: VMDq output index that maps queue to VLAN id in VFTA
- * @vlan_on: boolean flag to turn on/off VLAN in VFTA
- *
- * Turn on/off specified VLAN in the VLAN filter table.
- **/
-s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
- bool vlan_on)
-{
- u32 regindex;
- u32 bitindex;
- u32 bits;
- u32 vftabyte;
-
- if (vlan > 4095)
- return IXGBE_ERR_PARAM;
-
- /* Determine 32-bit word position in array */
- regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
-
- /* Determine the location of the (VMD) queue index */
- vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
- bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
-
- /* Set the nibble for VMD queue index */
- bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
- bits &= (~(0x0F << bitindex));
- bits |= (vind << bitindex);
- IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
-
- /* Determine the location of the bit for this VLAN id */
- bitindex = vlan & 0x1F; /* lower five bits */
-
- bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
- if (vlan_on)
- /* Turn on this VLAN id */
- bits |= (1 << bitindex);
- else
- /* Turn off this VLAN id */
- bits &= ~(1 << bitindex);
- IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
-
- return 0;
-}
-
-/**
- * ixgbe_clear_vfta_82598 - Clear VLAN filter table
- * @hw: pointer to hardware structure
- *
- * Clears the VLAN filer table, and the VMDq index associated with the filter
- **/
-static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
-{
- u32 offset;
- u32 vlanbyte;
-
- for (offset = 0; offset < hw->mac.vft_size; offset++)
- IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
-
- for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
- for (offset = 0; offset < hw->mac.vft_size; offset++)
- IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
- 0);
-
- return 0;
-}
-
-/**
- * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
- * @hw: pointer to hardware structure
- * @reg: analog register to read
- * @val: read value
- *
- * Performs read operation to Atlas analog register specified.
- **/
-s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
-{
- u32 atlas_ctl;
-
- IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
- IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
- IXGBE_WRITE_FLUSH(hw);
- udelay(10);
- atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
- *val = (u8)atlas_ctl;
-
- return 0;
-}
-
-/**
- * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
- * @hw: pointer to hardware structure
- * @reg: atlas register to write
- * @val: value to write
- *
- * Performs write operation to Atlas analog register specified.
- **/
-s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
-{
- u32 atlas_ctl;
-
- atlas_ctl = (reg << 8) | val;
- IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
- IXGBE_WRITE_FLUSH(hw);
- udelay(10);
-
- return 0;
-}
-
-/**
- * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
- * @hw: pointer to hardware structure
- * @byte_offset: EEPROM byte offset to read
- * @eeprom_data: value read
- *
- * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
- **/
-s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
- u8 *eeprom_data)
-{
- s32 status = 0;
- u16 sfp_addr = 0;
- u16 sfp_data = 0;
- u16 sfp_stat = 0;
- u32 i;
-
- if (hw->phy.type == ixgbe_phy_nl) {
- /*
- * NetLogic phy SDA/SCL registers are at addresses 0xC30A to
- * 0xC30D. These registers are used to talk to the SFP+
- * module's EEPROM through the SDA/SCL (I2C) interface.
- */
- sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
- sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
- hw->phy.ops.write_reg(hw,
- IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
- IXGBE_MDIO_PMA_PMD_DEV_TYPE,
- sfp_addr);
-
- /* Poll status */
- for (i = 0; i < 100; i++) {
- hw->phy.ops.read_reg(hw,
- IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
- IXGBE_MDIO_PMA_PMD_DEV_TYPE,
- &sfp_stat);
- sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
- if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
- break;
- msleep(10);
- }
-
- if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
- hw_dbg(hw, "EEPROM read did not pass.\n");
- status = IXGBE_ERR_SFP_NOT_PRESENT;
- goto out;
- }
-
- /* Read data */
- hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
- IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
-
- *eeprom_data = (u8)(sfp_data >> 8);
- } else {
- status = IXGBE_ERR_PHY;
- goto out;
- }
-
-out:
- return status;
-}
-
-/**
- * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
- * @hw: pointer to hardware structure
- *
- * Determines physical layer capabilities of the current configuration.
- **/
-u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
-{
- u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
- u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
- u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
- u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
- u16 ext_ability = 0;
-
- hw->phy.ops.identify(hw);
-
- /* Copper PHY must be checked before AUTOC LMS to determine correct
- * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
- switch (hw->phy.type) {
- case ixgbe_phy_tn:
- case ixgbe_phy_cu_unknown:
- hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
- IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
- if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
- physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
- if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
- physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
- if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
- physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
- goto out;
- default:
- break;
- }
-
- switch (autoc & IXGBE_AUTOC_LMS_MASK) {
- case IXGBE_AUTOC_LMS_1G_AN:
- case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
- if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
- physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
- else
- physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
- break;
- case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
- if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)
- physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
- else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)
- physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
- else /* XAUI */
- physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
- break;
- case IXGBE_AUTOC_LMS_KX4_AN:
- case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
- if (autoc & IXGBE_AUTOC_KX_SUPP)
- physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
- if (autoc & IXGBE_AUTOC_KX4_SUPP)
- physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
- break;
- default:
- break;
- }
-
- if (hw->phy.type == ixgbe_phy_nl) {
- hw->phy.ops.identify_sfp(hw);
-
- switch (hw->phy.sfp_type) {
- case ixgbe_sfp_type_da_cu:
- physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
- break;
- case ixgbe_sfp_type_sr:
- physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
- break;
- case ixgbe_sfp_type_lr:
- physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
- break;
- default:
- physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
- break;
- }
- }
-
- switch (hw->device_id) {
- case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
- physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
- break;
- case IXGBE_DEV_ID_82598AF_DUAL_PORT:
- case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
- case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
- physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
- break;
- case IXGBE_DEV_ID_82598EB_XF_LR:
- physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
- break;
- default:
- break;
- }
-
-out:
- return physical_layer;
-}
-
-/**
- * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
- * port devices.
- * @hw: pointer to the HW structure
- *
- * Calls common function and corrects issue with some single port devices
- * that enable LAN1 but not LAN0.
- **/
-void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
-{
- struct ixgbe_bus_info *bus = &hw->bus;
- u16 pci_gen = 0;
- u16 pci_ctrl2 = 0;
-
- ixgbe_set_lan_id_multi_port_pcie(hw);
-
- /* check if LAN0 is disabled */
- hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);
- if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
-
- hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);
-
- /* if LAN0 is completely disabled force function to 0 */
- if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&
- !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&
- !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {
-
- bus->func = 0;
- }
- }
-}
-
-/**
- * ixgbe_set_rxpba_82598 - Initialize RX packet buffer
- * @hw: pointer to hardware structure
- * @num_pb: number of packet buffers to allocate
- * @headroom: reserve n KB of headroom
- * @strategy: packet buffer allocation strategy
- **/
-static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
- u32 headroom, int strategy)
-{
- u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
- u8 i = 0;
-
- if (!num_pb)
- return;
-
- /* Setup Rx packet buffer sizes */
- switch (strategy) {
- case PBA_STRATEGY_WEIGHTED:
- /* Setup the first four at 80KB */
- rxpktsize = IXGBE_RXPBSIZE_80KB;
- for (; i < 4; i++)
- IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
- /* Setup the last four at 48KB...don't re-init i */
- rxpktsize = IXGBE_RXPBSIZE_48KB;
- /* Fall Through */
- case PBA_STRATEGY_EQUAL:
- default:
- /* Divide the remaining Rx packet buffer evenly among the TCs */
- for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
- IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
- break;
- }
-
- /* Setup Tx packet buffer sizes */
- for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
- IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
-
- return;
-}
diff --git a/kernel/linux/kni/ethtool/ixgbe/ixgbe_82598.h b/kernel/linux/kni/ethtool/ixgbe/ixgbe_82598.h
deleted file mode 100644
index 9a8c670..0000000
--- a/kernel/linux/kni/ethtool/ixgbe/ixgbe_82598.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*******************************************************************************
-
- Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2012 Intel Corporation.
-
- Contact Information:
- e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
- Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-
-#ifndef _IXGBE_82598_H_
-#define _IXGBE_82598_H_
-
-u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw);
-s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw);
-s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw);
-s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
-s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on);
-s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);
-s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);
-s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
- u8 *eeprom_data);
-u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);
-s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw);
-void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw);
-void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw);
-#endif /* _IXGBE_82598_H_ */
diff --git a/kernel/linux/kni/ethtool/ixgbe/ixgbe_82599.c b/kernel/linux/kni/ethtool/ixgbe/ixgbe_82599.c
deleted file mode 100644
index 3f15912..0000000
--- a/kernel/linux/kni/ethtool/ixgbe/ixgbe_82599.c
+++ /dev/null
@@ -1,2299 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*******************************************************************************
-
- Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2012 Intel Corporation.
-
- Contact Information:
- e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
- Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-
-#include "ixgbe_type.h"
-#include "ixgbe_82599.h"
-#include "ixgbe_api.h"
-#include "ixgbe_common.h"
-#include "ixgbe_phy.h"
-
-static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
- ixgbe_link_speed speed,
- bool autoneg,
- bool autoneg_wait_to_complete);
-static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
-static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
- u16 offset, u16 *data);
-static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
- u16 words, u16 *data);
-static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
- u8 dev_addr, u8 *data);
-static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
- u8 dev_addr, u8 data);
-
-void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
-{
- struct ixgbe_mac_info *mac = &hw->mac;
-
- /* enable the laser control functions for SFP+ fiber */
- if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
- mac->ops.disable_tx_laser =
- &ixgbe_disable_tx_laser_multispeed_fiber;
- mac->ops.enable_tx_laser =
- &ixgbe_enable_tx_laser_multispeed_fiber;
- mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
-
- } else {
- mac->ops.disable_tx_laser = NULL;
- mac->ops.enable_tx_laser = NULL;
- mac->ops.flap_tx_laser = NULL;
- }
-
- if (hw->phy.multispeed_fiber) {
- /* Set up dual speed SFP+ support */
- mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
- } else {
- if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
- (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
- hw->phy.smart_speed == ixgbe_smart_speed_on) &&
- !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
- mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
- } else {
- mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
- }
- }
-}
-
-/**
- * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
- * @hw: pointer to hardware structure
- *
- * Initialize any function pointers that were not able to be
- * set during init_shared_code because the PHY/SFP type was
- * not known. Perform the SFP init if necessary.
- *
- **/
-s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
-{
- struct ixgbe_mac_info *mac = &hw->mac;
- struct ixgbe_phy_info *phy = &hw->phy;
- s32 ret_val = 0;
- u32 esdp;
-
- if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
- /* Store flag indicating I2C bus access control unit. */
- hw->phy.qsfp_shared_i2c_bus = TRUE;
-
- /* Initialize access to QSFP+ I2C bus */
- esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
- esdp |= IXGBE_ESDP_SDP0_DIR;
- esdp &= ~IXGBE_ESDP_SDP1_DIR;
- esdp &= ~IXGBE_ESDP_SDP0;
- esdp &= ~IXGBE_ESDP_SDP0_NATIVE;
- esdp &= ~IXGBE_ESDP_SDP1_NATIVE;
- IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
- IXGBE_WRITE_FLUSH(hw);
-
- phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_82599;
- phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_82599;
- }
- /* Identify the PHY or SFP module */
- ret_val = phy->ops.identify(hw);
- if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
- goto init_phy_ops_out;
-
- /* Setup function pointers based on detected SFP module and speeds */
- ixgbe_init_mac_link_ops_82599(hw);
- if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
- hw->phy.ops.reset = NULL;
-
- /* If copper media, overwrite with copper function pointers */
- if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
- mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
- mac->ops.get_link_capabilities =
- &ixgbe_get_copper_link_capabilities_generic;
- }
-
- /* Set necessary function pointers based on phy type */
- switch (hw->phy.type) {
- case ixgbe_phy_tn:
- phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
- phy->ops.check_link = &ixgbe_check_phy_link_tnx;
- phy->ops.get_firmware_version =
- &ixgbe_get_phy_firmware_version_tnx;
- break;
- default:
- break;
- }
-init_phy_ops_out:
- return ret_val;
-}
-
-s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
-{
- s32 ret_val = 0;
- u32 reg_anlp1 = 0;
- u32 i = 0;
- u16 list_offset, data_offset, data_value;
-
- if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
- ixgbe_init_mac_link_ops_82599(hw);
-
- hw->phy.ops.reset = NULL;
-
- ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
- &data_offset);
- if (ret_val != 0)
- goto setup_sfp_out;
-
- /* PHY config will finish before releasing the semaphore */
- ret_val = hw->mac.ops.acquire_swfw_sync(hw,
- IXGBE_GSSR_MAC_CSR_SM);
- if (ret_val != 0) {
- ret_val = IXGBE_ERR_SWFW_SYNC;
- goto setup_sfp_out;
- }
-
- hw->eeprom.ops.read(hw, ++data_offset, &data_value);
- while (data_value != 0xffff) {
- IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
- IXGBE_WRITE_FLUSH(hw);
- hw->eeprom.ops.read(hw, ++data_offset, &data_value);
- }
-
- /* Release the semaphore */
- hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
- /* Delay obtaining semaphore again to allow FW access */
- msleep(hw->eeprom.semaphore_delay);
-
- /* Now restart DSP by setting Restart_AN and clearing LMS */
- IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
- IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
- IXGBE_AUTOC_AN_RESTART));
-
- /* Wait for AN to leave state 0 */
- for (i = 0; i < 10; i++) {
- msleep(4);
- reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
- if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
- break;
- }
- if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
- hw_dbg(hw, "sfp module setup not complete\n");
- ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
- goto setup_sfp_out;
- }
-
- /* Restart DSP by setting Restart_AN and return to SFI mode */
- IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
- IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
- IXGBE_AUTOC_AN_RESTART));
- }
-
-setup_sfp_out:
- return ret_val;
-}
-
-/**
- * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
- * @hw: pointer to hardware structure
- *
- * Initialize the function pointers and assign the MAC type for 82599.
- * Does not touch the hardware.
- **/
-
-s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
-{
- struct ixgbe_mac_info *mac = &hw->mac;
- struct ixgbe_phy_info *phy = &hw->phy;
- struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
- s32 ret_val;
-
- ixgbe_init_phy_ops_generic(hw);
- ret_val = ixgbe_init_ops_generic(hw);
-
- /* PHY */
- phy->ops.identify = &ixgbe_identify_phy_82599;
- phy->ops.init = &ixgbe_init_phy_ops_82599;
-
- /* MAC */
- mac->ops.reset_hw = &ixgbe_reset_hw_82599;
- mac->ops.get_media_type = &ixgbe_get_media_type_82599;
- mac->ops.get_supported_physical_layer =
- &ixgbe_get_supported_physical_layer_82599;
- mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
- mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
- mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
- mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
- mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
- mac->ops.start_hw = &ixgbe_start_hw_82599;
- mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
- mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
- mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
- mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
- mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
-
- /* RAR, Multicast, VLAN */
- mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
- mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
- mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
- mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
- mac->rar_highwater = 1;
- mac->ops.set_vfta = &ixgbe_set_vfta_generic;
- mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
- mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
- mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
- mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
- mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
- mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
-
- /* Link */
- mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
- mac->ops.check_link = &ixgbe_check_mac_link_generic;
- mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
- ixgbe_init_mac_link_ops_82599(hw);
-
- mac->mcft_size = 128;
- mac->vft_size = 128;
- mac->num_rar_entries = 128;
- mac->rx_pb_size = 512;
- mac->max_tx_queues = 128;
- mac->max_rx_queues = 128;
- mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
-
- mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
- IXGBE_FWSM_MODE_MASK) ? true : false;
-
- //hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
-
- /* EEPROM */
- eeprom->ops.read = &ixgbe_read_eeprom_82599;
- eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
-
- /* Manageability interface */
- mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
-
- mac->ops.get_thermal_sensor_data =
- &ixgbe_get_thermal_sensor_data_generic;
- mac->ops.init_thermal_sensor_thresh =
- &ixgbe_init_thermal_sensor_thresh_generic;
-
- return ret_val;
-}
-
-/**
- * ixgbe_get_link_capabilities_82599 - Determines link capabilities
- * @hw: pointer to hardware structure
- * @speed: pointer to link speed
- * @negotiation: true when autoneg or autotry is enabled
- *
- * Determines the link capabilities by reading the AUTOC register.
- **/
-s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed,
- bool *negotiation)
-{
- s32 status = 0;
- u32 autoc = 0;
-
- /* Check if 1G SFP module. */
- if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
- hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
- hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
- hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
- *speed = IXGBE_LINK_SPEED_1GB_FULL;
- *negotiation = true;
- goto out;
- }
-
- /*
- * Determine link capabilities based on the stored value of AUTOC,
- * which represents EEPROM defaults. If AUTOC value has not
- * been stored, use the current register values.
- */
- if (hw->mac.orig_link_settings_stored)
- autoc = hw->mac.orig_autoc;
- else
- autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
-
- switch (autoc & IXGBE_AUTOC_LMS_MASK) {
- case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
- *speed = IXGBE_LINK_SPEED_1GB_FULL;
- *negotiation = false;
- break;
-
- case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
- *speed = IXGBE_LINK_SPEED_10GB_FULL;
- *negotiation = false;
- break;
-
- case IXGBE_AUTOC_LMS_1G_AN:
- *speed = IXGBE_LINK_SPEED_1GB_FULL;
- *negotiation = true;
- break;
-
- case IXGBE_AUTOC_LMS_10G_SERIAL:
- *speed = IXGBE_LINK_SPEED_10GB_FULL;
- *negotiation = false;
- break;
-
- case IXGBE_AUTOC_LMS_KX4_KX_KR:
- case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
- *speed = IXGBE_LINK_SPEED_UNKNOWN;
- if (autoc & IXGBE_AUTOC_KR_SUPP)
- *speed |= IXGBE_LINK_SPEED_10GB_FULL;
- if (autoc & IXGBE_AUTOC_KX4_SUPP)
- *speed |= IXGBE_LINK_SPEED_10GB_FULL;
- if (autoc & IXGBE_AUTOC_KX_SUPP)
- *speed |= IXGBE_LINK_SPEED_1GB_FULL;
- *negotiation = true;
- break;
-
- case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
- *speed = IXGBE_LINK_SPEED_100_FULL;
- if (autoc & IXGBE_AUTOC_KR_SUPP)
- *speed |= IXGBE_LINK_SPEED_10GB_FULL;
- if (autoc & IXGBE_AUTOC_KX4_SUPP)
- *speed |= IXGBE_LINK_SPEED_10GB_FULL;
- if (autoc & IXGBE_AUTOC_KX_SUPP)
- *speed |= IXGBE_LINK_SPEED_1GB_FULL;
- *negotiation = true;
- break;
-
- case IXGBE_AUTOC_LMS_SGMII_1G_100M:
- *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
- *negotiation = false;
- break;
-
- default:
- status = IXGBE_ERR_LINK_SETUP;
- goto out;
- break;
- }
-
- if (hw->phy.multispeed_fiber) {
- *speed |= IXGBE_LINK_SPEED_10GB_FULL |
- IXGBE_LINK_SPEED_1GB_FULL;
- *negotiation = true;
- }
-
-out:
- return status;
-}
-
-/**
- * ixgbe_get_media_type_82599 - Get media type
- * @hw: pointer to hardware structure
- *
- * Returns the media type (fiber, copper, backplane)
- **/
-enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
-{
- enum ixgbe_media_type media_type;
-
- /* Detect if there is a copper PHY attached. */
- switch (hw->phy.type) {
- case ixgbe_phy_cu_unknown:
- case ixgbe_phy_tn:
- media_type = ixgbe_media_type_copper;
- goto out;
- default:
- break;
- }
-
- switch (hw->device_id) {
- case IXGBE_DEV_ID_82599_KX4:
- case IXGBE_DEV_ID_82599_KX4_MEZZ:
- case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
- case IXGBE_DEV_ID_82599_KR:
- case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
- case IXGBE_DEV_ID_82599_XAUI_LOM:
- /* Default device ID is mezzanine card KX/KX4 */
- media_type = ixgbe_media_type_backplane;
- break;
- case IXGBE_DEV_ID_82599_SFP:
- case IXGBE_DEV_ID_82599_SFP_FCOE:
- case IXGBE_DEV_ID_82599_SFP_EM:
- case IXGBE_DEV_ID_82599_SFP_SF2:
- case IXGBE_DEV_ID_82599EN_SFP:
- media_type = ixgbe_media_type_fiber;
- break;
- case IXGBE_DEV_ID_82599_CX4:
- media_type = ixgbe_media_type_cx4;
- break;
- case IXGBE_DEV_ID_82599_T3_LOM:
- media_type = ixgbe_media_type_copper;
- break;
- case IXGBE_DEV_ID_82599_LS:
- media_type = ixgbe_media_type_fiber_lco;
- break;
- case IXGBE_DEV_ID_82599_QSFP_SF_QP:
- media_type = ixgbe_media_type_fiber_qsfp;
- break;
- default:
- media_type = ixgbe_media_type_unknown;
- break;
- }
-out:
- return media_type;
-}
-
-/**
- * ixgbe_start_mac_link_82599 - Setup MAC link settings
- * @hw: pointer to hardware structure
- * @autoneg_wait_to_complete: true when waiting for completion is needed
- *
- * Configures link settings based on values in the ixgbe_hw struct.
- * Restarts the link. Performs autonegotiation if needed.
- **/
-s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
- bool autoneg_wait_to_complete)
-{
- u32 autoc_reg;
- u32 links_reg = 0;
- u32 i;
- s32 status = 0;
-
- /* Restart link */
- autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
- autoc_reg |= IXGBE_AUTOC_AN_RESTART;
- IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
-
- /* Only poll for autoneg to complete if specified to do so */
- if (autoneg_wait_to_complete) {
- if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
- IXGBE_AUTOC_LMS_KX4_KX_KR ||
- (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
- IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
- (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
- IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
- for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
- links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
- if (links_reg & IXGBE_LINKS_KX_AN_COMP)
- break;
- msleep(100);
- }
- if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
- status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
- hw_dbg(hw, "Autoneg did not complete.\n");
- }
- }
- }
-
- /* Add delay to filter out noises during initial link setup */
- msleep(50);
-
- return status;
-}
-
-/**
- * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
- * @hw: pointer to hardware structure
- *
- * The base drivers may require better control over SFP+ module
- * PHY states. This includes selectively shutting down the Tx
- * laser on the PHY, effectively halting physical link.
- **/
-void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
-{
- u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
-
- /* Disable tx laser; allow 100us to go dark per spec */
- esdp_reg |= IXGBE_ESDP_SDP3;
- IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
- IXGBE_WRITE_FLUSH(hw);
- udelay(100);
-}
-
-/**
- * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
- * @hw: pointer to hardware structure
- *
- * The base drivers may require better control over SFP+ module
- * PHY states. This includes selectively turning on the Tx
- * laser on the PHY, effectively starting physical link.
- **/
-void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
-{
- u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
-
- /* Enable tx laser; allow 100ms to light up */
- esdp_reg &= ~IXGBE_ESDP_SDP3;
- IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
- IXGBE_WRITE_FLUSH(hw);
- msleep(100);
-}
-
-/**
- * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
- * @hw: pointer to hardware structure
- *
- * When the driver changes the link speeds that it can support,
- * it sets autotry_restart to true to indicate that we need to
- * initiate a new autotry session with the link partner. To do
- * so, we set the speed then disable and re-enable the tx laser, to
- * alert the link partner that it also needs to restart autotry on its
- * end. This is consistent with true clause 37 autoneg, which also
- * involves a loss of signal.
- **/
-void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
-{
- if (hw->mac.autotry_restart) {
- ixgbe_disable_tx_laser_multispeed_fiber(hw);
- ixgbe_enable_tx_laser_multispeed_fiber(hw);
- hw->mac.autotry_restart = false;
- }
-}
-
-/**
- * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg: true if autonegotiation enabled
- * @autoneg_wait_to_complete: true when waiting for completion is needed
- *
- * Set the link speed in the AUTOC register and restarts link.
- **/
-s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
- ixgbe_link_speed speed, bool autoneg,
- bool autoneg_wait_to_complete)
-{
- s32 status = 0;
- ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
- ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
- u32 speedcnt = 0;
- u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
- u32 i = 0;
- bool link_up = false;
- bool negotiation;
-
- /* Mask off requested but non-supported speeds */
- status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation);
- if (status != 0)
- return status;
-
- speed &= link_speed;
-
- /*
- * Try each speed one by one, highest priority first. We do this in
- * software because 10gb fiber doesn't support speed autonegotiation.
- */
- if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
- speedcnt++;
- highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
-
- /* If we already have link at this speed, just jump out */
- status = ixgbe_check_link(hw, &link_speed, &link_up, false);
- if (status != 0)
- return status;
-
- if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
- goto out;
-
- /* Set the module link speed */
- esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
- IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
- IXGBE_WRITE_FLUSH(hw);
-
- /* Allow module to change analog characteristics (1G->10G) */
- msleep(40);
-
- status = ixgbe_setup_mac_link_82599(hw,
- IXGBE_LINK_SPEED_10GB_FULL,
- autoneg,
- autoneg_wait_to_complete);
- if (status != 0)
- return status;
-
- /* Flap the tx laser if it has not already been done */
- ixgbe_flap_tx_laser(hw);
-
- /*
- * Wait for the controller to acquire link. Per IEEE 802.3ap,
- * Section 73.10.2, we may have to wait up to 500ms if KR is
- * attempted. 82599 uses the same timing for 10g SFI.
- */
- for (i = 0; i < 5; i++) {
- /* Wait for the link partner to also set speed */
- msleep(100);
-
- /* If we have link, just jump out */
- status = ixgbe_check_link(hw, &link_speed,
- &link_up, false);
- if (status != 0)
- return status;
-
- if (link_up)
- goto out;
- }
- }
-
- if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
- speedcnt++;
- if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
- highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
-
- /* If we already have link at this speed, just jump out */
- status = ixgbe_check_link(hw, &link_speed, &link_up, false);
- if (status != 0)
- return status;
-
- if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
- goto out;
-
- /* Set the module link speed */
- esdp_reg &= ~IXGBE_ESDP_SDP5;
- esdp_reg |= IXGBE_ESDP_SDP5_DIR;
- IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
- IXGBE_WRITE_FLUSH(hw);
-
- /* Allow module to change analog characteristics (10G->1G) */
- msleep(40);
-
- status = ixgbe_setup_mac_link_82599(hw,
- IXGBE_LINK_SPEED_1GB_FULL,
- autoneg,
- autoneg_wait_to_complete);
- if (status != 0)
- return status;
-
- /* Flap the tx laser if it has not already been done */
- ixgbe_flap_tx_laser(hw);
-
- /* Wait for the link partner to also set speed */
- msleep(100);
-
- /* If we have link, just jump out */
- status = ixgbe_check_link(hw, &link_speed, &link_up, false);
- if (status != 0)
- return status;
-
- if (link_up)
- goto out;
- }
-
- /*
- * We didn't get link. Configure back to the highest speed we tried,
- * (if there was more than one). We call ourselves back with just the
- * single highest speed that the user requested.
- */
- if (speedcnt > 1)
- status = ixgbe_setup_mac_link_multispeed_fiber(hw,
- highest_link_speed, autoneg, autoneg_wait_to_complete);
-
-out:
- /* Set autoneg_advertised value based on input link speed */
- hw->phy.autoneg_advertised = 0;
-
- if (speed & IXGBE_LINK_SPEED_10GB_FULL)
- hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
-
- if (speed & IXGBE_LINK_SPEED_1GB_FULL)
- hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
-
- return status;
-}
-
-/**
- * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg: true if autonegotiation enabled
- * @autoneg_wait_to_complete: true when waiting for completion is needed
- *
- * Implements the Intel SmartSpeed algorithm.
- **/
-s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
- ixgbe_link_speed speed, bool autoneg,
- bool autoneg_wait_to_complete)
-{
- s32 status = 0;
- ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
- s32 i, j;
- bool link_up = false;
- u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
-
- /* Set autoneg_advertised value based on input link speed */
- hw->phy.autoneg_advertised = 0;
-
- if (speed & IXGBE_LINK_SPEED_10GB_FULL)
- hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
-
- if (speed & IXGBE_LINK_SPEED_1GB_FULL)
- hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
-
- if (speed & IXGBE_LINK_SPEED_100_FULL)
- hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
-
- /*
- * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
- * autoneg advertisement if link is unable to be established at the
- * highest negotiated rate. This can sometimes happen due to integrity
- * issues with the physical media connection.
- */
-
- /* First, try to get link with full advertisement */
- hw->phy.smart_speed_active = false;
- for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
- status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
- autoneg_wait_to_complete);
- if (status != 0)
- goto out;
-
- /*
- * Wait for the controller to acquire link. Per IEEE 802.3ap,
- * Section 73.10.2, we may have to wait up to 500ms if KR is
- * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
- * Table 9 in the AN MAS.
- */
- for (i = 0; i < 5; i++) {
- msleep(100);
-
- /* If we have link, just jump out */
- status = ixgbe_check_link(hw, &link_speed, &link_up,
- false);
- if (status != 0)
- goto out;
-
- if (link_up)
- goto out;
- }
- }
-
- /*
- * We didn't get link. If we advertised KR plus one of KX4/KX
- * (or BX4/BX), then disable KR and try again.
- */
- if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
- ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
- goto out;
-
- /* Turn SmartSpeed on to disable KR support */
- hw->phy.smart_speed_active = true;
- status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
- autoneg_wait_to_complete);
- if (status != 0)
- goto out;
-
- /*
- * Wait for the controller to acquire link. 600ms will allow for
- * the AN link_fail_inhibit_timer as well for multiple cycles of
- * parallel detect, both 10g and 1g. This allows for the maximum
- * connect attempts as defined in the AN MAS table 73-7.
- */
- for (i = 0; i < 6; i++) {
- msleep(100);
-
- /* If we have link, just jump out */
- status = ixgbe_check_link(hw, &link_speed, &link_up, false);
- if (status != 0)
- goto out;
-
- if (link_up)
- goto out;
- }
-
- /* We didn't get link. Turn SmartSpeed back off. */
- hw->phy.smart_speed_active = false;
- status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
- autoneg_wait_to_complete);
-
-out:
- if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
- hw_dbg(hw, "Smartspeed has downgraded the link speed "
- "from the maximum advertised\n");
- return status;
-}
-
-/**
- * ixgbe_setup_mac_link_82599 - Set MAC link speed
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg: true if autonegotiation enabled
- * @autoneg_wait_to_complete: true when waiting for completion is needed
- *
- * Set the link speed in the AUTOC register and restarts link.
- **/
-s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
- ixgbe_link_speed speed, bool autoneg,
- bool autoneg_wait_to_complete)
-{
- s32 status = 0;
- u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
- u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
- u32 start_autoc = autoc;
- u32 orig_autoc = 0;
- u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
- u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
- u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
- u32 links_reg = 0;
- u32 i;
- ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
-
- /* Check to see if speed passed in is supported. */
- status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
- if (status != 0)
- goto out;
-
- speed &= link_capabilities;
-
- if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
- status = IXGBE_ERR_LINK_SETUP;
- goto out;
- }
-
- /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
- if (hw->mac.orig_link_settings_stored)
- orig_autoc = hw->mac.orig_autoc;
- else
- orig_autoc = autoc;
-
- if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
- link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
- link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
- /* Set KX4/KX/KR support according to speed requested */
- autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
- if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
- if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
- autoc |= IXGBE_AUTOC_KX4_SUPP;
- if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
- (hw->phy.smart_speed_active == false))
- autoc |= IXGBE_AUTOC_KR_SUPP;
- }
- if (speed & IXGBE_LINK_SPEED_1GB_FULL)
- autoc |= IXGBE_AUTOC_KX_SUPP;
- } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
- (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
- link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
- /* Switch from 1G SFI to 10G SFI if requested */
- if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
- (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
- autoc &= ~IXGBE_AUTOC_LMS_MASK;
- autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
- }
- } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
- (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
- /* Switch from 10G SFI to 1G SFI if requested */
- if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
- (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
- autoc &= ~IXGBE_AUTOC_LMS_MASK;
- if (autoneg)
- autoc |= IXGBE_AUTOC_LMS_1G_AN;
- else
- autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
- }
- }
-
- if (autoc != start_autoc) {
- /* Restart link */
- autoc |= IXGBE_AUTOC_AN_RESTART;
- IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
-
- /* Only poll for autoneg to complete if specified to do so */
- if (autoneg_wait_to_complete) {
- if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
- link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
- link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
- for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
- links_reg =
- IXGBE_READ_REG(hw, IXGBE_LINKS);
- if (links_reg & IXGBE_LINKS_KX_AN_COMP)
- break;
- msleep(100);
- }
- if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
- status =
- IXGBE_ERR_AUTONEG_NOT_COMPLETE;
- hw_dbg(hw, "Autoneg did not complete.\n");
- }
- }
- }
-
- /* Add delay to filter out noises during initial link setup */
- msleep(50);
- }
-
-out:
- return status;
-}
-
-/**
- * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg: true if autonegotiation enabled
- * @autoneg_wait_to_complete: true if waiting is needed to complete
- *
- * Restarts link on PHY and MAC based on settings passed in.
- **/
-static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
- ixgbe_link_speed speed,
- bool autoneg,
- bool autoneg_wait_to_complete)
-{
- s32 status;
-
- /* Setup the PHY according to input speed */
- status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
- autoneg_wait_to_complete);
- /* Set up MAC */
- ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
-
- return status;
-}
-
-/**
- * ixgbe_reset_hw_82599 - Perform hardware reset
- * @hw: pointer to hardware structure
- *
- * Resets the hardware by resetting the transmit and receive units, masks
- * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
- * reset.
- **/
-s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
-{
-// ixgbe_link_speed link_speed;
- s32 status = 0;
-// u32 ctrl, i, autoc, autoc2;
-// bool link_up = false;
-
-#if 0
- /* Call adapter stop to disable tx/rx and clear interrupts */
- status = hw->mac.ops.stop_adapter(hw);
- if (status != 0)
- goto reset_hw_out;
-
- /* flush pending Tx transactions */
- ixgbe_clear_tx_pending(hw);
-
- /* PHY ops must be identified and initialized prior to reset */
-
- /* Identify PHY and related function pointers */
- status = hw->phy.ops.init(hw);
-
- if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
- goto reset_hw_out;
-
- /* Setup SFP module if there is one present. */
- if (hw->phy.sfp_setup_needed) {
- status = hw->mac.ops.setup_sfp(hw);
- hw->phy.sfp_setup_needed = false;
- }
-
- if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
- goto reset_hw_out;
-
- /* Reset PHY */
- if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
- hw->phy.ops.reset(hw);
-
-mac_reset_top:
- /*
- * Issue global reset to the MAC. Needs to be SW reset if link is up.
- * If link reset is used when link is up, it might reset the PHY when
- * mng is using it. If link is down or the flag to force full link
- * reset is set, then perform link reset.
- */
- ctrl = IXGBE_CTRL_LNK_RST;
- if (!hw->force_full_reset) {
- hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
- if (link_up)
- ctrl = IXGBE_CTRL_RST;
- }
-
- ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
- IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
- IXGBE_WRITE_FLUSH(hw);
-
- /* Poll for reset bit to self-clear indicating reset is complete */
- for (i = 0; i < 10; i++) {
- udelay(1);
- ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
- if (!(ctrl & IXGBE_CTRL_RST_MASK))
- break;
- }
-
- if (ctrl & IXGBE_CTRL_RST_MASK) {
- status = IXGBE_ERR_RESET_FAILED;
- hw_dbg(hw, "Reset polling failed to complete.\n");
- }
-
- msleep(50);
-
- /*
- * Double resets are required for recovery from certain error
- * conditions. Between resets, it is necessary to stall to allow time
- * for any pending HW events to complete.
- */
- if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
- hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
- goto mac_reset_top;
- }
-
- /*
- * Store the original AUTOC/AUTOC2 values if they have not been
- * stored off yet. Otherwise restore the stored original
- * values since the reset operation sets back to defaults.
- */
- autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
- autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
- if (hw->mac.orig_link_settings_stored == false) {
- hw->mac.orig_autoc = autoc;
- hw->mac.orig_autoc2 = autoc2;
- hw->mac.orig_link_settings_stored = true;
- } else {
- if (autoc != hw->mac.orig_autoc)
- IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
- IXGBE_AUTOC_AN_RESTART));
-
- if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
- (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
- autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
- autoc2 |= (hw->mac.orig_autoc2 &
- IXGBE_AUTOC2_UPPER_MASK);
- IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
- }
- }
-#endif
-
- /* Store the permanent mac address */
- hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
-
- /*
- * Store MAC address from RAR0, clear receive address registers, and
- * clear the multicast table. Also reset num_rar_entries to 128,
- * since we modify this value when programming the SAN MAC address.
- */
- hw->mac.num_rar_entries = 128;
- hw->mac.ops.init_rx_addrs(hw);
-
- /* Store the permanent SAN mac address */
- hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
-
- /* Add the SAN MAC address to the RAR only if it's a valid address */
- if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
- hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
- hw->mac.san_addr, 0, IXGBE_RAH_AV);
-
- /* Save the SAN MAC RAR index */
- hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
-
- /* Reserve the last RAR for the SAN MAC address */
- hw->mac.num_rar_entries--;
- }
-
- /* Store the alternative WWNN/WWPN prefix */
- hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
- &hw->mac.wwpn_prefix);
-
-//reset_hw_out:
- return status;
-}
-
-/**
- * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
- * @hw: pointer to hardware structure
- **/
-s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
-{
- int i;
- u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
- fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
-
- /*
- * Before starting reinitialization process,
- * FDIRCMD.CMD must be zero.
- */
- for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
- if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
- IXGBE_FDIRCMD_CMD_MASK))
- break;
- udelay(10);
- }
- if (i >= IXGBE_FDIRCMD_CMD_POLL) {
- hw_dbg(hw, "Flow Director previous command isn't complete, "
- "aborting table re-initialization.\n");
- return IXGBE_ERR_FDIR_REINIT_FAILED;
- }
-
- IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
- IXGBE_WRITE_FLUSH(hw);
- /*
- * 82599 adapters flow director init flow cannot be restarted,
- * Workaround 82599 silicon errata by performing the following steps
- * before re-writing the FDIRCTRL control register with the same value.
- * - write 1 to bit 8 of FDIRCMD register &
- * - write 0 to bit 8 of FDIRCMD register
- */
- IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
- (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
- IXGBE_FDIRCMD_CLEARHT));
- IXGBE_WRITE_FLUSH(hw);
- IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
- (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
- ~IXGBE_FDIRCMD_CLEARHT));
- IXGBE_WRITE_FLUSH(hw);
- /*
- * Clear FDIR Hash register to clear any leftover hashes
- * waiting to be programmed.
- */
- IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
- IXGBE_WRITE_FLUSH(hw);
-
- IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
- IXGBE_WRITE_FLUSH(hw);
-
- /* Poll init-done after we write FDIRCTRL register */
- for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
- if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
- IXGBE_FDIRCTRL_INIT_DONE)
- break;
- udelay(10);
- }
- if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
- hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
- return IXGBE_ERR_FDIR_REINIT_FAILED;
- }
-
- /* Clear FDIR statistics registers (read to clear) */
- IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
- IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
- IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
- IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
- IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
-
- return 0;
-}
-
-/**
- * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
- * @hw: pointer to hardware structure
- * @fdirctrl: value to write to flow director control register
- **/
-static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
-{
- int i;
-
- /* Prime the keys for hashing */
- IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
- IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
-
- /*
- * Poll init-done after we write the register. Estimated times:
- * 10G: PBALLOC = 11b, timing is 60us
- * 1G: PBALLOC = 11b, timing is 600us
- * 100M: PBALLOC = 11b, timing is 6ms
- *
- * Multiple these timings by 4 if under full Rx load
- *
- * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
- * 1 msec per poll time. If we're at line rate and drop to 100M, then
- * this might not finish in our poll time, but we can live with that
- * for now.
- */
- IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
- IXGBE_WRITE_FLUSH(hw);
- for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
- if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
- IXGBE_FDIRCTRL_INIT_DONE)
- break;
- msleep(1);
- }
-
- if (i >= IXGBE_FDIR_INIT_DONE_POLL)
- hw_dbg(hw, "Flow Director poll time exceeded!\n");
-}
-
-/**
- * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
- * @hw: pointer to hardware structure
- * @fdirctrl: value to write to flow director control register, initially
- * contains just the value of the Rx packet buffer allocation
- **/
-s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
-{
- /*
- * Continue setup of fdirctrl register bits:
- * Move the flexible bytes to use the ethertype - shift 6 words
- * Set the maximum length per hash bucket to 0xA filters
- * Send interrupt when 64 filters are left
- */
- fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
- (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
- (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
-
- /* write hashes and fdirctrl register, poll for completion */
- ixgbe_fdir_enable_82599(hw, fdirctrl);
-
- return 0;
-}
-
-/**
- * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
- * @hw: pointer to hardware structure
- * @fdirctrl: value to write to flow director control register, initially
- * contains just the value of the Rx packet buffer allocation
- **/
-s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
-{
- /*
- * Continue setup of fdirctrl register bits:
- * Turn perfect match filtering on
- * Report hash in RSS field of Rx wb descriptor
- * Initialize the drop queue
- * Move the flexible bytes to use the ethertype - shift 6 words
- * Set the maximum length per hash bucket to 0xA filters
- * Send interrupt when 64 (0x4 * 16) filters are left
- */
- fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
- IXGBE_FDIRCTRL_REPORT_STATUS |
- (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
- (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
- (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
- (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
-
- /* write hashes and fdirctrl register, poll for completion */
- ixgbe_fdir_enable_82599(hw, fdirctrl);
-
- return 0;
-}
-
-/*
- * These defines allow us to quickly generate all of the necessary instructions
- * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
- * for values 0 through 15
- */
-#define IXGBE_ATR_COMMON_HASH_KEY \
- (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
-#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
-do { \
- u32 n = (_n); \
- if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
- common_hash ^= lo_hash_dword >> n; \
- else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
- bucket_hash ^= lo_hash_dword >> n; \
- else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
- sig_hash ^= lo_hash_dword << (16 - n); \
- if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
- common_hash ^= hi_hash_dword >> n; \
- else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
- bucket_hash ^= hi_hash_dword >> n; \
- else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
- sig_hash ^= hi_hash_dword << (16 - n); \
-} while (0);
-
-/**
- * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
- * @stream: input bitstream to compute the hash on
- *
- * This function is almost identical to the function above but contains
- * several optomizations such as unwinding all of the loops, letting the
- * compiler work out all of the conditional ifs since the keys are static
- * defines, and computing two keys at once since the hashed dword stream
- * will be the same for both keys.
- **/
-u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
- union ixgbe_atr_hash_dword common)
-{
- u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
- u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
-
- /* record the flow_vm_vlan bits as they are a key part to the hash */
- flow_vm_vlan = IXGBE_NTOHL(input.dword);
-
- /* generate common hash dword */
- hi_hash_dword = IXGBE_NTOHL(common.dword);
-
- /* low dword is word swapped version of common */
- lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
-
- /* apply flow ID/VM pool/VLAN ID bits to hash words */
- hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
-
- /* Process bits 0 and 16 */
- IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
-
- /*
- * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
- * delay this because bit 0 of the stream should not be processed
- * so we do not add the vlan until after bit 0 was processed
- */
- lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
-
- /* Process remaining 30 bit of the key */
- IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
- IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
- IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
- IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
- IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
- IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
- IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
- IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
- IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
- IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
- IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
- IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
- IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
- IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
- IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
-
- /* combine common_hash result with signature and bucket hashes */
- bucket_hash ^= common_hash;
- bucket_hash &= IXGBE_ATR_HASH_MASK;
-
- sig_hash ^= common_hash << 16;
- sig_hash &= IXGBE_ATR_HASH_MASK << 16;
-
- /* return completed signature hash */
- return sig_hash ^ bucket_hash;
-}
-
-/**
- * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
- * @hw: pointer to hardware structure
- * @input: unique input dword
- * @common: compressed common input dword
- * @queue: queue index to direct traffic to
- **/
-s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
- union ixgbe_atr_hash_dword input,
- union ixgbe_atr_hash_dword common,
- u8 queue)
-{
- u64 fdirhashcmd;
- u32 fdircmd;
-
- /*
- * Get the flow_type in order to program FDIRCMD properly
- * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
- */
- switch (input.formatted.flow_type) {
- case IXGBE_ATR_FLOW_TYPE_TCPV4:
- case IXGBE_ATR_FLOW_TYPE_UDPV4:
- case IXGBE_ATR_FLOW_TYPE_SCTPV4:
- case IXGBE_ATR_FLOW_TYPE_TCPV6:
- case IXGBE_ATR_FLOW_TYPE_UDPV6:
- case IXGBE_ATR_FLOW_TYPE_SCTPV6:
- break;
- default:
- hw_dbg(hw, " Error on flow type input\n");
- return IXGBE_ERR_CONFIG;
- }
-
- /* configure FDIRCMD register */
- fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
- IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
- fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
- fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
-
- /*
- * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
- * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
- */
- fdirhashcmd = (u64)fdircmd << 32;
- fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
- IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
-
- hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
-
- return 0;
-}
-
-#define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
-do { \
- u32 n = (_n); \
- if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
- bucket_hash ^= lo_hash_dword >> n; \
- if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
- bucket_hash ^= hi_hash_dword >> n; \
-} while (0);
-
-/**
- * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
- * @atr_input: input bitstream to compute the hash on
- * @input_mask: mask for the input bitstream
- *
- * This function serves two main purposes. First it applys the input_mask
- * to the atr_input resulting in a cleaned up atr_input data stream.
- * Secondly it computes the hash and stores it in the bkt_hash field at
- * the end of the input byte stream. This way it will be available for
- * future use without needing to recompute the hash.
- **/
-void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
- union ixgbe_atr_input *input_mask)
-{
-
- u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
- u32 bucket_hash = 0;
-
- /* Apply masks to input data */
- input->dword_stream[0] &= input_mask->dword_stream[0];
- input->dword_stream[1] &= input_mask->dword_stream[1];
- input->dword_stream[2] &= input_mask->dword_stream[2];
- input->dword_stream[3] &= input_mask->dword_stream[3];
- input->dword_stream[4] &= input_mask->dword_stream[4];
- input->dword_stream[5] &= input_mask->dword_stream[5];
- input->dword_stream[6] &= input_mask->dword_stream[6];
- input->dword_stream[7] &= input_mask->dword_stream[7];
- input->dword_stream[8] &= input_mask->dword_stream[8];
- input->dword_stream[9] &= input_mask->dword_stream[9];
- input->dword_stream[10] &= input_mask->dword_stream[10];
-
- /* record the flow_vm_vlan bits as they are a key part to the hash */
- flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
-
- /* generate common hash dword */
- hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^
- input->dword_stream[2] ^
- input->dword_stream[3] ^
- input->dword_stream[4] ^
- input->dword_stream[5] ^
- input->dword_stream[6] ^
- input->dword_stream[7] ^
- input->dword_stream[8] ^
- input->dword_stream[9] ^
- input->dword_stream[10]);
-
- /* low dword is word swapped version of common */
- lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
-
- /* apply flow ID/VM pool/VLAN ID bits to hash words */
- hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
-
- /* Process bits 0 and 16 */
- IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
-
- /*
- * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
- * delay this because bit 0 of the stream should not be processed
- * so we do not add the vlan until after bit 0 was processed
- */
- lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
-
- /* Process remaining 30 bit of the key */
- IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
- IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
- IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
- IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
- IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
- IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
- IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
- IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
- IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
- IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
- IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
- IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
- IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
- IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
- IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
-
- /*
- * Limit hash to 13 bits since max bucket count is 8K.
- * Store result at the end of the input stream.
- */
- input->formatted.bkt_hash = bucket_hash & 0x1FFF;
-}
-
-/**
- * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
- * @input_mask: mask to be bit swapped
- *
- * The source and destination port masks for flow director are bit swapped
- * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
- * generate a correctly swapped value we need to bit swap the mask and that
- * is what is accomplished by this function.
- **/
-static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
-{
- u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
- mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
- mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
- mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
- mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
- mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
- return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
-}
-
-/*
- * These two macros are meant to address the fact that we have registers
- * that are either all or in part big-endian. As a result on big-endian
- * systems we will end up byte swapping the value to little-endian before
- * it is byte swapped again and written to the hardware in the original
- * big-endian format.
- */
-#define IXGBE_STORE_AS_BE32(_value) \
- (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
- (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
-
-#define IXGBE_WRITE_REG_BE32(a, reg, value) \
- IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
-
-#define IXGBE_STORE_AS_BE16(_value) \
- IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
-
-s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
- union ixgbe_atr_input *input_mask)
-{
- /* mask IPv6 since it is currently not supported */
- u32 fdirm = IXGBE_FDIRM_DIPv6;
- u32 fdirtcpm;
-
- /*
- * Program the relevant mask registers. If src/dst_port or src/dst_addr
- * are zero, then assume a full mask for that field. Also assume that
- * a VLAN of 0 is unspecified, so mask that out as well. L4type
- * cannot be masked out in this implementation.
- *
- * This also assumes IPv4 only. IPv6 masking isn't supported at this
- * point in time.
- */
-
- /* verify bucket hash is cleared on hash generation */
- if (input_mask->formatted.bkt_hash)
- hw_dbg(hw, " bucket hash should always be 0 in mask\n");
-
- /* Program FDIRM and verify partial masks */
- switch (input_mask->formatted.vm_pool & 0x7F) {
- case 0x0:
- fdirm |= IXGBE_FDIRM_POOL;
- case 0x7F:
- break;
- default:
- hw_dbg(hw, " Error on vm pool mask\n");
- return IXGBE_ERR_CONFIG;
- }
-
- switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
- case 0x0:
- fdirm |= IXGBE_FDIRM_L4P;
- if (input_mask->formatted.dst_port ||
- input_mask->formatted.src_port) {
- hw_dbg(hw, " Error on src/dst port mask\n");
- return IXGBE_ERR_CONFIG;
- }
- case IXGBE_ATR_L4TYPE_MASK:
- break;
- default:
- hw_dbg(hw, " Error on flow type mask\n");
- return IXGBE_ERR_CONFIG;
- }
-
- switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
- case 0x0000:
- /* mask VLAN ID, fall through to mask VLAN priority */
- fdirm |= IXGBE_FDIRM_VLANID;
- case 0x0FFF:
- /* mask VLAN priority */
- fdirm |= IXGBE_FDIRM_VLANP;
- break;
- case 0xE000:
- /* mask VLAN ID only, fall through */
- fdirm |= IXGBE_FDIRM_VLANID;
- case 0xEFFF:
- /* no VLAN fields masked */
- break;
- default:
- hw_dbg(hw, " Error on VLAN mask\n");
- return IXGBE_ERR_CONFIG;
- }
-
- switch (input_mask->formatted.flex_bytes & 0xFFFF) {
- case 0x0000:
- /* Mask Flex Bytes, fall through */
- fdirm |= IXGBE_FDIRM_FLEX;
- case 0xFFFF:
- break;
- default:
- hw_dbg(hw, " Error on flexible byte mask\n");
- return IXGBE_ERR_CONFIG;
- }
-
- /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
- IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
-
- /* store the TCP/UDP port masks, bit reversed from port layout */
- fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
-
- /* write both the same so that UDP and TCP use the same mask */
- IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
- IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
-
- /* store source and destination IP masks (big-enian) */
- IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
- ~input_mask->formatted.src_ip[0]);
- IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
- ~input_mask->formatted.dst_ip[0]);
-
- return 0;
-}
-
-s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
- union ixgbe_atr_input *input,
- u16 soft_id, u8 queue)
-{
- u32 fdirport, fdirvlan, fdirhash, fdircmd;
-
- /* currently IPv6 is not supported, must be programmed with 0 */
- IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
- input->formatted.src_ip[0]);
- IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
- input->formatted.src_ip[1]);
- IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
- input->formatted.src_ip[2]);
-
- /* record the source address (big-endian) */
- IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
-
- /* record the first 32 bits of the destination address (big-endian) */
- IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
-
- /* record source and destination port (little-endian)*/
- fdirport = IXGBE_NTOHS(input->formatted.dst_port);
- fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
- fdirport |= IXGBE_NTOHS(input->formatted.src_port);
- IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
-
- /* record vlan (little-endian) and flex_bytes(big-endian) */
- fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
- fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
- fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
- IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
-
- /* configure FDIRHASH register */
- fdirhash = input->formatted.bkt_hash;
- fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
- IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
-
- /*
- * flush all previous writes to make certain registers are
- * programmed prior to issuing the command
- */
- IXGBE_WRITE_FLUSH(hw);
-
- /* configure FDIRCMD register */
- fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
- IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
- if (queue == IXGBE_FDIR_DROP_QUEUE)
- fdircmd |= IXGBE_FDIRCMD_DROP;
- fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
- fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
- fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
-
- IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
-
- return 0;
-}
-
-s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
- union ixgbe_atr_input *input,
- u16 soft_id)
-{
- u32 fdirhash;
- u32 fdircmd = 0;
- u32 retry_count;
- s32 err = 0;
-
- /* configure FDIRHASH register */
- fdirhash = input->formatted.bkt_hash;
- fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
- IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
-
- /* flush hash to HW */
- IXGBE_WRITE_FLUSH(hw);
-
- /* Query if filter is present */
- IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
-
- for (retry_count = 10; retry_count; retry_count--) {
- /* allow 10us for query to process */
- udelay(10);
- /* verify query completed successfully */
- fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
- if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
- break;
- }
-
- if (!retry_count)
- err = IXGBE_ERR_FDIR_REINIT_FAILED;
-
- /* if filter exists in hardware then remove it */
- if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
- IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
- IXGBE_WRITE_FLUSH(hw);
- IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
- IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
- }
-
- return err;
-}
-
-/**
- * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
- * @hw: pointer to hardware structure
- * @input: input bitstream
- * @input_mask: mask for the input bitstream
- * @soft_id: software index for the filters
- * @queue: queue index to direct traffic to
- *
- * Note that the caller to this function must lock before calling, since the
- * hardware writes must be protected from one another.
- **/
-s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
- union ixgbe_atr_input *input,
- union ixgbe_atr_input *input_mask,
- u16 soft_id, u8 queue)
-{
- s32 err = IXGBE_ERR_CONFIG;
-
- /*
- * Check flow_type formatting, and bail out before we touch the hardware
- * if there's a configuration issue
- */
- switch (input->formatted.flow_type) {
- case IXGBE_ATR_FLOW_TYPE_IPV4:
- input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
- if (input->formatted.dst_port || input->formatted.src_port) {
- hw_dbg(hw, " Error on src/dst port\n");
- return IXGBE_ERR_CONFIG;
- }
- break;
- case IXGBE_ATR_FLOW_TYPE_SCTPV4:
- if (input->formatted.dst_port || input->formatted.src_port) {
- hw_dbg(hw, " Error on src/dst port\n");
- return IXGBE_ERR_CONFIG;
- }
- case IXGBE_ATR_FLOW_TYPE_TCPV4:
- case IXGBE_ATR_FLOW_TYPE_UDPV4:
- input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
- IXGBE_ATR_L4TYPE_MASK;
- break;
- default:
- hw_dbg(hw, " Error on flow type input\n");
- return err;
- }
-
- /* program input mask into the HW */
- err = ixgbe_fdir_set_input_mask_82599(hw, input_mask);
- if (err)
- return err;
-
- /* apply mask and compute/store hash */
- ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
-
- /* program filters to filter memory */
- return ixgbe_fdir_write_perfect_filter_82599(hw, input,
- soft_id, queue);
-}
-
-/**
- * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
- * @hw: pointer to hardware structure
- * @reg: analog register to read
- * @val: read value
- *
- * Performs read operation to Omer analog register specified.
- **/
-s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
-{
- u32 core_ctl;
-
- IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
- (reg << 8));
- IXGBE_WRITE_FLUSH(hw);
- udelay(10);
- core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
- *val = (u8)core_ctl;
-
- return 0;
-}
-
-/**
- * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
- * @hw: pointer to hardware structure
- * @reg: atlas register to write
- * @val: value to write
- *
- * Performs write operation to Omer analog register specified.
- **/
-s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
-{
- u32 core_ctl;
-
- core_ctl = (reg << 8) | val;
- IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
- IXGBE_WRITE_FLUSH(hw);
- udelay(10);
-
- return 0;
-}
-
-/**
- * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
- * @hw: pointer to hardware structure
- *
- * Starts the hardware using the generic start_hw function
- * and the generation start_hw function.
- * Then performs revision-specific operations, if any.
- **/
-s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
-{
- s32 ret_val = 0;
-
- ret_val = ixgbe_start_hw_generic(hw);
- if (ret_val != 0)
- goto out;
-
- ret_val = ixgbe_start_hw_gen2(hw);
- if (ret_val != 0)
- goto out;
-
- /* We need to run link autotry after the driver loads */
- hw->mac.autotry_restart = true;
-
- if (ret_val == 0)
- ret_val = ixgbe_verify_fw_version_82599(hw);
-out:
- return ret_val;
-}
-
-/**
- * ixgbe_identify_phy_82599 - Get physical layer module
- * @hw: pointer to hardware structure
- *
- * Determines the physical layer module found on the current adapter.
- * If PHY already detected, maintains current PHY type in hw struct,
- * otherwise executes the PHY detection routine.
- **/
-s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
-{
- s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
-
- /* Detect PHY if not unknown - returns success if already detected. */
- status = ixgbe_identify_phy_generic(hw);
- if (status != 0) {
- /* 82599 10GBASE-T requires an external PHY */
- if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
- goto out;
- else
- status = ixgbe_identify_module_generic(hw);
- }
-
- /* Set PHY type none if no PHY detected */
- if (hw->phy.type == ixgbe_phy_unknown) {
- hw->phy.type = ixgbe_phy_none;
- status = 0;
- }
-
- /* Return error if SFP module has been detected but is not supported */
- if (hw->phy.type == ixgbe_phy_sfp_unsupported)
- status = IXGBE_ERR_SFP_NOT_SUPPORTED;
-
-out:
- return status;
-}
-
-/**
- * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
- * @hw: pointer to hardware structure
- *
- * Determines physical layer capabilities of the current configuration.
- **/
-u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
-{
- u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
- u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
- u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
- u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
- u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
- u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
- u16 ext_ability = 0;
- u8 comp_codes_10g = 0;
- u8 comp_codes_1g = 0;
-
- hw->phy.ops.identify(hw);
-
- switch (hw->phy.type) {
- case ixgbe_phy_tn:
- case ixgbe_phy_cu_unknown:
- hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
- IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
- if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
- physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
- if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
- physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
- if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
- physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
- goto out;
- default:
- break;
- }
-
- switch (autoc & IXGBE_AUTOC_LMS_MASK) {
- case IXGBE_AUTOC_LMS_1G_AN:
- case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
- if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
- physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
- IXGBE_PHYSICAL_LAYER_1000BASE_BX;
- goto out;
- } else
- /* SFI mode so read SFP module */
- goto sfp_check;
- break;
- case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
- if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
- physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
- else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
- physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
- else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
- physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
- goto out;
- break;
- case IXGBE_AUTOC_LMS_10G_SERIAL:
- if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
- physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
- goto out;
- } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
- goto sfp_check;
- break;
- case IXGBE_AUTOC_LMS_KX4_KX_KR:
- case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
- if (autoc & IXGBE_AUTOC_KX_SUPP)
- physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
- if (autoc & IXGBE_AUTOC_KX4_SUPP)
- physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
- if (autoc & IXGBE_AUTOC_KR_SUPP)
- physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
- goto out;
- break;
- default:
- goto out;
- break;
- }
-
-sfp_check:
- /* SFP check must be done last since DA modules are sometimes used to
- * test KR mode - we need to id KR mode correctly before SFP module.
- * Call identify_sfp because the pluggable module may have changed */
- hw->phy.ops.identify_sfp(hw);
- if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
- goto out;
-
- switch (hw->phy.type) {
- case ixgbe_phy_sfp_passive_tyco:
- case ixgbe_phy_sfp_passive_unknown:
- physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
- break;
- case ixgbe_phy_sfp_ftl_active:
- case ixgbe_phy_sfp_active_unknown:
- physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
- break;
- case ixgbe_phy_sfp_avago:
- case ixgbe_phy_sfp_ftl:
- case ixgbe_phy_sfp_intel:
- case ixgbe_phy_sfp_unknown:
- hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
- hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
- if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
- physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
- else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
- physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
- else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
- physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
- else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
- physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
- break;
- default:
- break;
- }
-
-out:
- return physical_layer;
-}
-
-/**
- * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
- * @hw: pointer to hardware structure
- * @regval: register value to write to RXCTRL
- *
- * Enables the Rx DMA unit for 82599
- **/
-s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
-{
-
- /*
- * Workaround for 82599 silicon errata when enabling the Rx datapath.
- * If traffic is incoming before we enable the Rx unit, it could hang
- * the Rx DMA unit. Therefore, make sure the security engine is
- * completely disabled prior to enabling the Rx unit.
- */
-
- hw->mac.ops.disable_sec_rx_path(hw);
-
- IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
-
- hw->mac.ops.enable_sec_rx_path(hw);
-
- return 0;
-}
-
-/**
- * ixgbe_verify_fw_version_82599 - verify fw version for 82599
- * @hw: pointer to hardware structure
- *
- * Verifies that installed the firmware version is 0.6 or higher
- * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
- *
- * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
- * if the FW version is not supported.
- **/
-static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
-{
- s32 status = IXGBE_ERR_EEPROM_VERSION;
- u16 fw_offset, fw_ptp_cfg_offset;
- u16 fw_version = 0;
-
- /* firmware check is only necessary for SFI devices */
- if (hw->phy.media_type != ixgbe_media_type_fiber) {
- status = 0;
- goto fw_version_out;
- }
-
- /* get the offset to the Firmware Module block */
- hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
-
- if ((fw_offset == 0) || (fw_offset == 0xFFFF))
- goto fw_version_out;
-
- /* get the offset to the Pass Through Patch Configuration block */
- hw->eeprom.ops.read(hw, (fw_offset +
- IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
- &fw_ptp_cfg_offset);
-
- if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
- goto fw_version_out;
-
- /* get the firmware version */
- hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
- IXGBE_FW_PATCH_VERSION_4), &fw_version);
-
- if (fw_version > 0x5)
- status = 0;
-
-fw_version_out:
- return status;
-}
-
-/**
- * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
- * @hw: pointer to hardware structure
- *
- * Returns true if the LESM FW module is present and enabled. Otherwise
- * returns false. Smart Speed must be disabled if LESM FW module is enabled.
- **/
-bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
-{
- bool lesm_enabled = false;
- u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
- s32 status;
-
- /* get the offset to the Firmware Module block */
- status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
-
- if ((status != 0) ||
- (fw_offset == 0) || (fw_offset == 0xFFFF))
- goto out;
-
- /* get the offset to the LESM Parameters block */
- status = hw->eeprom.ops.read(hw, (fw_offset +
- IXGBE_FW_LESM_PARAMETERS_PTR),
- &fw_lesm_param_offset);
-
- if ((status != 0) ||
- (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
- goto out;
-
- /* get the lesm state word */
- status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
- IXGBE_FW_LESM_STATE_1),
- &fw_lesm_state);
-
- if ((status == 0) &&
- (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
- lesm_enabled = true;
-
-out:
- return lesm_enabled;
-}
-
-/**
- * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
- * fastest available method
- *
- * @hw: pointer to hardware structure
- * @offset: offset of word in EEPROM to read
- * @words: number of words
- * @data: word(s) read from the EEPROM
- *
- * Retrieves 16 bit word(s) read from EEPROM
- **/
-static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
- u16 words, u16 *data)
-{
- struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
- s32 ret_val = IXGBE_ERR_CONFIG;
-
- /*
- * If EEPROM is detected and can be addressed using 14 bits,
- * use EERD otherwise use bit bang
- */
- if ((eeprom->type == ixgbe_eeprom_spi) &&
- (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
- ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
- data);
- else
- ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
- words,
- data);
-
- return ret_val;
-}
-
-/**
- * ixgbe_read_eeprom_82599 - Read EEPROM word using
- * fastest available method
- *
- * @hw: pointer to hardware structure
- * @offset: offset of word in the EEPROM to read
- * @data: word read from the EEPROM
- *
- * Reads a 16 bit word from the EEPROM
- **/
-static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
- u16 offset, u16 *data)
-{
- struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
- s32 ret_val = IXGBE_ERR_CONFIG;
-
- /*
- * If EEPROM is detected and can be addressed using 14 bits,
- * use EERD otherwise use bit bang
- */
- if ((eeprom->type == ixgbe_eeprom_spi) &&
- (offset <= IXGBE_EERD_MAX_ADDR))
- ret_val = ixgbe_read_eerd_generic(hw, offset, data);
- else
- ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
-
- return ret_val;
-}
-
-/**
- * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
- * @hw: pointer to hardware structure
- * @byte_offset: byte offset to read
- * @data: value read
- *
- * Performs byte read operation to SFP module's EEPROM over I2C interface at
- * a specified device address.
- **/
-static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
- u8 dev_addr, u8 *data)
-{
- u32 esdp;
- s32 status;
- s32 timeout = 200;
-
- if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
- /* Acquire I2C bus ownership. */
- esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
- esdp |= IXGBE_ESDP_SDP0;
- IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
- IXGBE_WRITE_FLUSH(hw);
-
- while (timeout) {
- esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
- if (esdp & IXGBE_ESDP_SDP1)
- break;
-
- msleep(5);
- timeout--;
- }
-
- if (!timeout) {
- hw_dbg(hw, "Driver can't access resource,"
- " acquiring I2C bus timeout.\n");
- status = IXGBE_ERR_I2C;
- goto release_i2c_access;
- }
- }
-
- status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);
-
-release_i2c_access:
-
- if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
- /* Release I2C bus ownership. */
- esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
- esdp &= ~IXGBE_ESDP_SDP0;
- IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
- IXGBE_WRITE_FLUSH(hw);
- }
-
- return status;
-}
-
-/**
- * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
- * @hw: pointer to hardware structure
- * @byte_offset: byte offset to write
- * @data: value to write
- *
- * Performs byte write operation to SFP module's EEPROM over I2C interface at
- * a specified device address.
- **/
-static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
- u8 dev_addr, u8 data)
-{
- u32 esdp;
- s32 status;
- s32 timeout = 200;
-
- if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
- /* Acquire I2C bus ownership. */
- esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
- esdp |= IXGBE_ESDP_SDP0;
- IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
- IXGBE_WRITE_FLUSH(hw);
-
- while (timeout) {
- esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
- if (esdp & IXGBE_ESDP_SDP1)
- break;
-
- msleep(5);
- timeout--;
- }
-
- if (!timeout) {
- hw_dbg(hw, "Driver can't access resource,"
- " acquiring I2C bus timeout.\n");
- status = IXGBE_ERR_I2C;
- goto release_i2c_access;
- }
- }
-
- status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);
-
-release_i2c_access:
-
- if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
- /* Release I2C bus ownership. */
- esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
- esdp &= ~IXGBE_ESDP_SDP0;
- IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
- IXGBE_WRITE_FLUSH(hw);
- }
-
- return status;
-}
diff --git a/kernel/linux/kni/ethtool/ixgbe/ixgbe_82599.h b/kernel/linux/kni/ethtool/ixgbe/ixgbe_82599.h
deleted file mode 100644
index 0305ed7..0000000
--- a/kernel/linux/kni/ethtool/ixgbe/ixgbe_82599.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*******************************************************************************
-
- Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2012 Intel Corporation.
-
- Contact Information:
- e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
- Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-
-#ifndef _IXGBE_82599_H_
-#define _IXGBE_82599_H_
-
-s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed, bool *autoneg);
-enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
-void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
-void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
-void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
-s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
- ixgbe_link_speed speed, bool autoneg,
- bool autoneg_wait_to_complete);
-s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
- ixgbe_link_speed speed, bool autoneg,
- bool autoneg_wait_to_complete);
-s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
- bool autoneg_wait_to_complete);
-s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed speed,
- bool autoneg, bool autoneg_wait_to_complete);
-s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw);
-void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw);
-s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
-s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
-s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
-s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);
-s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
-s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw);
-u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
-s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval);
-bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
-#endif /* _IXGBE_82599_H_ */
diff --git a/kernel/linux/kni/ethtool/ixgbe/ixgbe_api.c b/kernel/linux/kni/ethtool/ixgbe/ixgbe_api.c
deleted file mode 100644
index 1be4c64..0000000
--- a/kernel/linux/kni/ethtool/ixgbe/ixgbe_api.c
+++ /dev/null
@@ -1,1142 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*******************************************************************************
-
- Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2012 Intel Corporation.
-
- Contact Information:
- e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
- Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-
-#include "ixgbe_api.h"
-#include "ixgbe_common.h"
-
-/**
- * ixgbe_init_shared_code - Initialize the shared code
- * @hw: pointer to hardware structure
- *
- * This will assign function pointers and assign the MAC type and PHY code.
- * Does not touch the hardware. This function must be called prior to any
- * other function in the shared code. The ixgbe_hw structure should be
- * memset to 0 prior to calling this function. The following fields in
- * hw structure should be filled in prior to calling this function:
- * hw_addr, back, device_id, vendor_id, subsystem_device_id,
- * subsystem_vendor_id, and revision_id
- **/
-s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
-{
- s32 status;
-
- /*
- * Set the mac type
- */
- ixgbe_set_mac_type(hw);
-
- switch (hw->mac.type) {
- case ixgbe_mac_82598EB:
- status = ixgbe_init_ops_82598(hw);
- break;
- case ixgbe_mac_82599EB:
- status = ixgbe_init_ops_82599(hw);
- break;
- case ixgbe_mac_X540:
- status = ixgbe_init_ops_X540(hw);
- break;
- default:
- status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
- break;
- }
-
- return status;
-}
-
-/**
- * ixgbe_set_mac_type - Sets MAC type
- * @hw: pointer to the HW structure
- *
- * This function sets the mac type of the adapter based on the
- * vendor ID and device ID stored in the hw structure.
- **/
-s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
-{
- s32 ret_val = 0;
-
- if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) {
- switch (hw->device_id) {
- case IXGBE_DEV_ID_82598:
- case IXGBE_DEV_ID_82598_BX:
- case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
- case IXGBE_DEV_ID_82598AF_DUAL_PORT:
- case IXGBE_DEV_ID_82598AT:
- case IXGBE_DEV_ID_82598AT2:
- case IXGBE_DEV_ID_82598EB_CX4:
- case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
- case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
- case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
- case IXGBE_DEV_ID_82598EB_XF_LR:
- case IXGBE_DEV_ID_82598EB_SFP_LOM:
- hw->mac.type = ixgbe_mac_82598EB;
- break;
- case IXGBE_DEV_ID_82599_KX4:
- case IXGBE_DEV_ID_82599_KX4_MEZZ:
- case IXGBE_DEV_ID_82599_XAUI_LOM:
- case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
- case IXGBE_DEV_ID_82599_KR:
- case IXGBE_DEV_ID_82599_SFP:
- case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
- case IXGBE_DEV_ID_82599_SFP_FCOE:
- case IXGBE_DEV_ID_82599_SFP_EM:
- case IXGBE_DEV_ID_82599_SFP_SF2:
- case IXGBE_DEV_ID_82599_QSFP_SF_QP:
- case IXGBE_DEV_ID_82599EN_SFP:
- case IXGBE_DEV_ID_82599_CX4:
- case IXGBE_DEV_ID_82599_LS:
- case IXGBE_DEV_ID_82599_T3_LOM:
- hw->mac.type = ixgbe_mac_82599EB;
- break;
- case IXGBE_DEV_ID_X540T:
- hw->mac.type = ixgbe_mac_X540;
- break;
- default:
- ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
- break;
- }
- } else {
- ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
- }
-
- hw_dbg(hw, "ixgbe_set_mac_type found mac: %d, returns: %d\n",
- hw->mac.type, ret_val);
- return ret_val;
-}
-
-/**
- * ixgbe_init_hw - Initialize the hardware
- * @hw: pointer to hardware structure
- *
- * Initialize the hardware by resetting and then starting the hardware
- **/
-s32 ixgbe_init_hw(struct ixgbe_hw *hw)
-{
- return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_reset_hw - Performs a hardware reset
- * @hw: pointer to hardware structure
- *
- * Resets the hardware by resetting the transmit and receive units, masks and
- * clears all interrupts, performs a PHY reset, and performs a MAC reset
- **/
-s32 ixgbe_reset_hw(struct ixgbe_hw *hw)
-{
- return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_start_hw - Prepares hardware for Rx/Tx
- * @hw: pointer to hardware structure
- *
- * Starts the hardware by filling the bus info structure and media type,
- * clears all on chip counters, initializes receive address registers,
- * multicast table, VLAN filter table, calls routine to setup link and
- * flow control settings, and leaves transmit and receive units disabled
- * and uninitialized.
- **/
-s32 ixgbe_start_hw(struct ixgbe_hw *hw)
-{
- return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_clear_hw_cntrs - Clear hardware counters
- * @hw: pointer to hardware structure
- *
- * Clears all hardware statistics counters by reading them from the hardware
- * Statistics counters are clear on read.
- **/
-s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)
-{
- return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_get_media_type - Get media type
- * @hw: pointer to hardware structure
- *
- * Returns the media type (fiber, copper, backplane)
- **/
-enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw)
-{
- return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw),
- ixgbe_media_type_unknown);
-}
-
-/**
- * ixgbe_get_mac_addr - Get MAC address
- * @hw: pointer to hardware structure
- * @mac_addr: Adapter MAC address
- *
- * Reads the adapter's MAC address from the first Receive Address Register
- * (RAR0) A reset of the adapter must have been performed prior to calling
- * this function in order for the MAC address to have been loaded from the
- * EEPROM into RAR0
- **/
-s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)
-{
- return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr,
- (hw, mac_addr), IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_get_san_mac_addr - Get SAN MAC address
- * @hw: pointer to hardware structure
- * @san_mac_addr: SAN MAC address
- *
- * Reads the SAN MAC address from the EEPROM, if it's available. This is
- * per-port, so set_lan_id() must be called before reading the addresses.
- **/
-s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
-{
- return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr,
- (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_set_san_mac_addr - Write a SAN MAC address
- * @hw: pointer to hardware structure
- * @san_mac_addr: SAN MAC address
- *
- * Writes A SAN MAC address to the EEPROM.
- **/
-s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
-{
- return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr,
- (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_get_device_caps - Get additional device capabilities
- * @hw: pointer to hardware structure
- * @device_caps: the EEPROM word for device capabilities
- *
- * Reads the extra device capabilities from the EEPROM
- **/
-s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps)
-{
- return ixgbe_call_func(hw, hw->mac.ops.get_device_caps,
- (hw, device_caps), IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM
- * @hw: pointer to hardware structure
- * @wwnn_prefix: the alternative WWNN prefix
- * @wwpn_prefix: the alternative WWPN prefix
- *
- * This function will read the EEPROM from the alternative SAN MAC address
- * block to check the support for the alternative WWNN/WWPN prefix support.
- **/
-s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
- u16 *wwpn_prefix)
-{
- return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix,
- (hw, wwnn_prefix, wwpn_prefix),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM
- * @hw: pointer to hardware structure
- * @bs: the fcoe boot status
- *
- * This function will read the FCOE boot status from the iSCSI FCOE block
- **/
-s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs)
-{
- return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status,
- (hw, bs),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_get_bus_info - Set PCI bus info
- * @hw: pointer to hardware structure
- *
- * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
- **/
-s32 ixgbe_get_bus_info(struct ixgbe_hw *hw)
-{
- return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_get_num_of_tx_queues - Get Tx queues
- * @hw: pointer to hardware structure
- *
- * Returns the number of transmit queues for the given adapter.
- **/
-u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw)
-{
- return hw->mac.max_tx_queues;
-}
-
-/**
- * ixgbe_get_num_of_rx_queues - Get Rx queues
- * @hw: pointer to hardware structure
- *
- * Returns the number of receive queues for the given adapter.
- **/
-u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw)
-{
- return hw->mac.max_rx_queues;
-}
-
-/**
- * ixgbe_stop_adapter - Disable Rx/Tx units
- * @hw: pointer to hardware structure
- *
- * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
- * disables transmit and receive units. The adapter_stopped flag is used by
- * the shared code and drivers to determine if the adapter is in a stopped
- * state and should not touch the hardware.
- **/
-s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)
-{
- return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_read_pba_string - Reads part number string from EEPROM
- * @hw: pointer to hardware structure
- * @pba_num: stores the part number string from the EEPROM
- * @pba_num_size: part number string buffer length
- *
- * Reads the part number string from the EEPROM.
- **/
-s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size)
-{
- return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size);
-}
-
-/**
- * ixgbe_identify_phy - Get PHY type
- * @hw: pointer to hardware structure
- *
- * Determines the physical layer module found on the current adapter.
- **/
-s32 ixgbe_identify_phy(struct ixgbe_hw *hw)
-{
- s32 status = 0;
-
- if (hw->phy.type == ixgbe_phy_unknown) {
- status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw),
- IXGBE_NOT_IMPLEMENTED);
- }
-
- return status;
-}
-
-/**
- * ixgbe_reset_phy - Perform a PHY reset
- * @hw: pointer to hardware structure
- **/
-s32 ixgbe_reset_phy(struct ixgbe_hw *hw)
-{
- s32 status = 0;
-
- if (hw->phy.type == ixgbe_phy_unknown) {
- if (ixgbe_identify_phy(hw) != 0)
- status = IXGBE_ERR_PHY;
- }
-
- if (status == 0) {
- status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw),
- IXGBE_NOT_IMPLEMENTED);
- }
- return status;
-}
-
-/**
- * ixgbe_get_phy_firmware_version -
- * @hw: pointer to hardware structure
- * @firmware_version: pointer to firmware version
- **/
-s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version)
-{
- s32 status = 0;
-
- status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version,
- (hw, firmware_version),
- IXGBE_NOT_IMPLEMENTED);
- return status;
-}
-
-/**
- * ixgbe_read_phy_reg - Read PHY register
- * @hw: pointer to hardware structure
- * @reg_addr: 32 bit address of PHY register to read
- * @phy_data: Pointer to read data from PHY register
- *
- * Reads a value from a specified PHY register
- **/
-s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
- u16 *phy_data)
-{
- if (hw->phy.id == 0)
- ixgbe_identify_phy(hw);
-
- return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr,
- device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_write_phy_reg - Write PHY register
- * @hw: pointer to hardware structure
- * @reg_addr: 32 bit PHY register to write
- * @phy_data: Data to write to the PHY register
- *
- * Writes a value to specified PHY register
- **/
-s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
- u16 phy_data)
-{
- if (hw->phy.id == 0)
- ixgbe_identify_phy(hw);
-
- return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,
- device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_setup_phy_link - Restart PHY autoneg
- * @hw: pointer to hardware structure
- *
- * Restart autonegotiation and PHY and waits for completion.
- **/
-s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)
-{
- return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_check_phy_link - Determine link and speed status
- * @hw: pointer to hardware structure
- *
- * Reads a PHY register to determine if link is up and the current speed for
- * the PHY.
- **/
-s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
- bool *link_up)
-{
- return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed,
- link_up), IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_setup_phy_link_speed - Set auto advertise
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg: true if autonegotiation enabled
- *
- * Sets the auto advertised capabilities
- **/
-s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
- bool autoneg,
- bool autoneg_wait_to_complete)
-{
- return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed,
- autoneg, autoneg_wait_to_complete),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_check_link - Get link and speed status
- * @hw: pointer to hardware structure
- *
- * Reads the links register to determine if link is up and the current speed
- **/
-s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
- bool *link_up, bool link_up_wait_to_complete)
-{
- return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed,
- link_up, link_up_wait_to_complete),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_disable_tx_laser - Disable Tx laser
- * @hw: pointer to hardware structure
- *
- * If the driver needs to disable the laser on SFI optics.
- **/
-void ixgbe_disable_tx_laser(struct ixgbe_hw *hw)
-{
- if (hw->mac.ops.disable_tx_laser)
- hw->mac.ops.disable_tx_laser(hw);
-}
-
-/**
- * ixgbe_enable_tx_laser - Enable Tx laser
- * @hw: pointer to hardware structure
- *
- * If the driver needs to enable the laser on SFI optics.
- **/
-void ixgbe_enable_tx_laser(struct ixgbe_hw *hw)
-{
- if (hw->mac.ops.enable_tx_laser)
- hw->mac.ops.enable_tx_laser(hw);
-}
-
-/**
- * ixgbe_flap_tx_laser - flap Tx laser to start autotry process
- * @hw: pointer to hardware structure
- *
- * When the driver changes the link speeds that it can support then
- * flap the tx laser to alert the link partner to start autotry
- * process on its end.
- **/
-void ixgbe_flap_tx_laser(struct ixgbe_hw *hw)
-{
- if (hw->mac.ops.flap_tx_laser)
- hw->mac.ops.flap_tx_laser(hw);
-}
-
-/**
- * ixgbe_setup_link - Set link speed
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg: true if autonegotiation enabled
- *
- * Configures link settings. Restarts the link.
- * Performs autonegotiation if needed.
- **/
-s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
- bool autoneg,
- bool autoneg_wait_to_complete)
-{
- return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed,
- autoneg, autoneg_wait_to_complete),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_get_link_capabilities - Returns link capabilities
- * @hw: pointer to hardware structure
- *
- * Determines the link capabilities of the current configuration.
- **/
-s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
- bool *autoneg)
-{
- return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw,
- speed, autoneg), IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_led_on - Turn on LEDs
- * @hw: pointer to hardware structure
- * @index: led number to turn on
- *
- * Turns on the software controllable LEDs.
- **/
-s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)
-{
- return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_led_off - Turn off LEDs
- * @hw: pointer to hardware structure
- * @index: led number to turn off
- *
- * Turns off the software controllable LEDs.
- **/
-s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index)
-{
- return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_blink_led_start - Blink LEDs
- * @hw: pointer to hardware structure
- * @index: led number to blink
- *
- * Blink LED based on index.
- **/
-s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index)
-{
- return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_blink_led_stop - Stop blinking LEDs
- * @hw: pointer to hardware structure
- *
- * Stop blinking LED based on index.
- **/
-s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index)
-{
- return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_init_eeprom_params - Initialize EEPROM parameters
- * @hw: pointer to hardware structure
- *
- * Initializes the EEPROM parameters ixgbe_eeprom_info within the
- * ixgbe_hw struct in order to set up EEPROM access.
- **/
-s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw)
-{
- return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-
-/**
- * ixgbe_write_eeprom - Write word to EEPROM
- * @hw: pointer to hardware structure
- * @offset: offset within the EEPROM to be written to
- * @data: 16 bit word to be written to the EEPROM
- *
- * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not
- * called after this function, the EEPROM will most likely contain an
- * invalid checksum.
- **/
-s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data)
-{
- return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM
- * @hw: pointer to hardware structure
- * @offset: offset within the EEPROM to be written to
- * @data: 16 bit word(s) to be written to the EEPROM
- * @words: number of words
- *
- * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not
- * called after this function, the EEPROM will most likely contain an
- * invalid checksum.
- **/
-s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words,
- u16 *data)
-{
- return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer,
- (hw, offset, words, data),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_read_eeprom - Read word from EEPROM
- * @hw: pointer to hardware structure
- * @offset: offset within the EEPROM to be read
- * @data: read 16 bit value from EEPROM
- *
- * Reads 16 bit value from EEPROM
- **/
-s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)
-{
- return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM
- * @hw: pointer to hardware structure
- * @offset: offset within the EEPROM to be read
- * @data: read 16 bit word(s) from EEPROM
- * @words: number of words
- *
- * Reads 16 bit word(s) from EEPROM
- **/
-s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
- u16 words, u16 *data)
-{
- return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer,
- (hw, offset, words, data),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum
- * @hw: pointer to hardware structure
- * @checksum_val: calculated checksum
- *
- * Performs checksum calculation and validates the EEPROM checksum
- **/
-s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)
-{
- return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum,
- (hw, checksum_val), IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum
- * @hw: pointer to hardware structure
- **/
-s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw)
-{
- return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_insert_mac_addr - Find a RAR for this mac address
- * @hw: pointer to hardware structure
- * @addr: Address to put into receive address register
- * @vmdq: VMDq pool to assign
- *
- * Puts an ethernet address into a receive address register, or
- * finds the rar that it is already in; adds to the pool list
- **/
-s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
-{
- return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr,
- (hw, addr, vmdq),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_set_rar - Set Rx address register
- * @hw: pointer to hardware structure
- * @index: Receive address register to write
- * @addr: Address to put into receive address register
- * @vmdq: VMDq "set"
- * @enable_addr: set flag that address is active
- *
- * Puts an ethernet address into a receive address register.
- **/
-s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
- u32 enable_addr)
-{
- return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq,
- enable_addr), IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_clear_rar - Clear Rx address register
- * @hw: pointer to hardware structure
- * @index: Receive address register to write
- *
- * Puts an ethernet address into a receive address register.
- **/
-s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index)
-{
- return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_set_vmdq - Associate a VMDq index with a receive address
- * @hw: pointer to hardware structure
- * @rar: receive address register index to associate with VMDq index
- * @vmdq: VMDq set or pool index
- **/
-s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
-{
- return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq),
- IXGBE_NOT_IMPLEMENTED);
-
-}
-
-/**
- * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address
- * @hw: pointer to hardware structure
- * @vmdq: VMDq default pool index
- **/
-s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq)
-{
- return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac,
- (hw, vmdq), IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address
- * @hw: pointer to hardware structure
- * @rar: receive address register index to disassociate with VMDq index
- * @vmdq: VMDq set or pool index
- **/
-s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
-{
- return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_init_rx_addrs - Initializes receive address filters.
- * @hw: pointer to hardware structure
- *
- * Places the MAC address in receive address register 0 and clears the rest
- * of the receive address registers. Clears the multicast table. Assumes
- * the receiver is in reset when the routine is called.
- **/
-s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)
-{
- return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_get_num_rx_addrs - Returns the number of RAR entries.
- * @hw: pointer to hardware structure
- **/
-u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw)
-{
- return hw->mac.num_rar_entries;
-}
-
-/**
- * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses
- * @hw: pointer to hardware structure
- * @addr_list: the list of new multicast addresses
- * @addr_count: number of addresses
- * @func: iterator function to walk the multicast address list
- *
- * The given list replaces any existing list. Clears the secondary addrs from
- * receive address registers. Uses unused receive address registers for the
- * first secondary addresses, and falls back to promiscuous mode as needed.
- **/
-s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
- u32 addr_count, ixgbe_mc_addr_itr func)
-{
- return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw,
- addr_list, addr_count, func),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses
- * @hw: pointer to hardware structure
- * @mc_addr_list: the list of new multicast addresses
- * @mc_addr_count: number of addresses
- * @func: iterator function to walk the multicast address list
- *
- * The given list replaces any existing list. Clears the MC addrs from receive
- * address registers and the multicast table. Uses unused receive address
- * registers for the first multicast addresses, and hashes the rest into the
- * multicast table.
- **/
-s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
- u32 mc_addr_count, ixgbe_mc_addr_itr func,
- bool clear)
-{
- return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw,
- mc_addr_list, mc_addr_count, func, clear),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_enable_mc - Enable multicast address in RAR
- * @hw: pointer to hardware structure
- *
- * Enables multicast address in RAR and the use of the multicast hash table.
- **/
-s32 ixgbe_enable_mc(struct ixgbe_hw *hw)
-{
- return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_disable_mc - Disable multicast address in RAR
- * @hw: pointer to hardware structure
- *
- * Disables multicast address in RAR and the use of the multicast hash table.
- **/
-s32 ixgbe_disable_mc(struct ixgbe_hw *hw)
-{
- return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_clear_vfta - Clear VLAN filter table
- * @hw: pointer to hardware structure
- *
- * Clears the VLAN filer table, and the VMDq index associated with the filter
- **/
-s32 ixgbe_clear_vfta(struct ixgbe_hw *hw)
-{
- return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_set_vfta - Set VLAN filter table
- * @hw: pointer to hardware structure
- * @vlan: VLAN id to write to VLAN filter
- * @vind: VMDq output index that maps queue to VLAN id in VFTA
- * @vlan_on: boolean flag to turn on/off VLAN in VFTA
- *
- * Turn on/off specified VLAN in the VLAN filter table.
- **/
-s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
-{
- return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind,
- vlan_on), IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_set_vlvf - Set VLAN Pool Filter
- * @hw: pointer to hardware structure
- * @vlan: VLAN id to write to VLAN filter
- * @vind: VMDq output index that maps queue to VLAN id in VFVFB
- * @vlan_on: boolean flag to turn on/off VLAN in VFVF
- * @vfta_changed: pointer to boolean flag which indicates whether VFTA
- * should be changed
- *
- * Turn on/off specified bit in VLVF table.
- **/
-s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,
- bool *vfta_changed)
-{
- return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind,
- vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_fc_enable - Enable flow control
- * @hw: pointer to hardware structure
- *
- * Configures the flow control settings based on SW configuration.
- **/
-s32 ixgbe_fc_enable(struct ixgbe_hw *hw)
-{
- return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_set_fw_drv_ver - Try to send the driver version number FW
- * @hw: pointer to hardware structure
- * @maj: driver major number to be sent to firmware
- * @min: driver minor number to be sent to firmware
- * @build: driver build number to be sent to firmware
- * @ver: driver version number to be sent to firmware
- **/
-s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
- u8 ver)
-{
- return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min,
- build, ver), IXGBE_NOT_IMPLEMENTED);
-}
-
-
-/**
- * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
- * @hw: pointer to hardware structure
- *
- * Updates the temperatures in mac.thermal_sensor_data
- **/
-s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw)
-{
- return ixgbe_call_func(hw, hw->mac.ops.get_thermal_sensor_data, (hw),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
- * @hw: pointer to hardware structure
- *
- * Inits the thermal sensor thresholds according to the NVM map
- **/
-s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw)
-{
- return ixgbe_call_func(hw, hw->mac.ops.init_thermal_sensor_thresh, (hw),
- IXGBE_NOT_IMPLEMENTED);
-}
-/**
- * ixgbe_read_analog_reg8 - Reads 8 bit analog register
- * @hw: pointer to hardware structure
- * @reg: analog register to read
- * @val: read value
- *
- * Performs write operation to analog register specified.
- **/
-s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)
-{
- return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg,
- val), IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_write_analog_reg8 - Writes 8 bit analog register
- * @hw: pointer to hardware structure
- * @reg: analog register to write
- * @val: value to write
- *
- * Performs write operation to Atlas analog register specified.
- **/
-s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)
-{
- return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg,
- val), IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_init_uta_tables - Initializes Unicast Table Arrays.
- * @hw: pointer to hardware structure
- *
- * Initializes the Unicast Table Arrays to zero on device load. This
- * is part of the Rx init addr execution path.
- **/
-s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw)
-{
- return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address
- * @hw: pointer to hardware structure
- * @byte_offset: byte offset to read
- * @data: value read
- *
- * Performs byte read operation to SFP module's EEPROM over I2C interface.
- **/
-s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
- u8 *data)
-{
- return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset,
- dev_addr, data), IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_write_i2c_byte - Writes 8 bit word over I2C
- * @hw: pointer to hardware structure
- * @byte_offset: byte offset to write
- * @data: value to write
- *
- * Performs byte write operation to SFP module's EEPROM over I2C interface
- * at a specified device address.
- **/
-s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
- u8 data)
-{
- return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset,
- dev_addr, data), IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
- * @hw: pointer to hardware structure
- * @byte_offset: EEPROM byte offset to write
- * @eeprom_data: value to write
- *
- * Performs byte write operation to SFP module's EEPROM over I2C interface.
- **/
-s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw,
- u8 byte_offset, u8 eeprom_data)
-{
- return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom,
- (hw, byte_offset, eeprom_data),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
- * @hw: pointer to hardware structure
- * @byte_offset: EEPROM byte offset to read
- * @eeprom_data: value read
- *
- * Performs byte read operation to SFP module's EEPROM over I2C interface.
- **/
-s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)
-{
- return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom,
- (hw, byte_offset, eeprom_data),
- IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_get_supported_physical_layer - Returns physical layer type
- * @hw: pointer to hardware structure
- *
- * Determines physical layer capabilities of the current configuration.
- **/
-u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)
-{
- return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer,
- (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);
-}
-
-/**
- * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics
- * @hw: pointer to hardware structure
- * @regval: bitfield to write to the Rx DMA register
- *
- * Enables the Rx DMA unit of the device.
- **/
-s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval)
-{
- return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma,
- (hw, regval), IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_disable_sec_rx_path - Stops the receive data path
- * @hw: pointer to hardware structure
- *
- * Stops the receive data path.
- **/
-s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw)
-{
- return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path,
- (hw), IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_enable_sec_rx_path - Enables the receive data path
- * @hw: pointer to hardware structure
- *
- * Enables the receive data path.
- **/
-s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw)
-{
- return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path,
- (hw), IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore
- * @hw: pointer to hardware structure
- * @mask: Mask to specify which semaphore to acquire
- *
- * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified
- * function (CSR, PHY0, PHY1, EEPROM, Flash)
- **/
-s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
-{
- return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync,
- (hw, mask), IXGBE_NOT_IMPLEMENTED);
-}
-
-/**
- * ixgbe_release_swfw_semaphore - Release SWFW semaphore
- * @hw: pointer to hardware structure
- * @mask: Mask to specify which semaphore to release
- *
- * Releases the SWFW semaphore through SW_FW_SYNC register for the specified
- * function (CSR, PHY0, PHY1, EEPROM, Flash)
- **/
-void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
-{
- if (hw->mac.ops.release_swfw_sync)
- hw->mac.ops.release_swfw_sync(hw, mask);
-}
diff --git a/kernel/linux/kni/ethtool/ixgbe/ixgbe_api.h b/kernel/linux/kni/ethtool/ixgbe/ixgbe_api.h
deleted file mode 100644
index 11247a0..0000000
--- a/kernel/linux/kni/ethtool/ixgbe/ixgbe_api.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*******************************************************************************
-
- Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2012 Intel Corporation.
-
- Contact Information:
- e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
- Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-
-#ifndef _IXGBE_API_H_
-#define _IXGBE_API_H_
-
-#include "ixgbe_type.h"
-
-s32 ixgbe_init_shared_code(struct ixgbe_hw *hw);
-
-extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
-extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);
-extern s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw);
-
-s32 ixgbe_set_mac_type(struct ixgbe_hw *hw);
-s32 ixgbe_init_hw(struct ixgbe_hw *hw);
-s32 ixgbe_reset_hw(struct ixgbe_hw *hw);
-s32 ixgbe_start_hw(struct ixgbe_hw *hw);
-s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw);
-enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw);
-s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr);
-s32 ixgbe_get_bus_info(struct ixgbe_hw *hw);
-u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw);
-u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw);
-s32 ixgbe_stop_adapter(struct ixgbe_hw *hw);
-s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size);
-
-s32 ixgbe_identify_phy(struct ixgbe_hw *hw);
-s32 ixgbe_reset_phy(struct ixgbe_hw *hw);
-s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
- u16 *phy_data);
-s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
- u16 phy_data);
-
-s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw);
-s32 ixgbe_check_phy_link(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed,
- bool *link_up);
-s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw,
- ixgbe_link_speed speed,
- bool autoneg,
- bool autoneg_wait_to_complete);
-void ixgbe_disable_tx_laser(struct ixgbe_hw *hw);
-void ixgbe_enable_tx_laser(struct ixgbe_hw *hw);
-void ixgbe_flap_tx_laser(struct ixgbe_hw *hw);
-s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
- bool autoneg, bool autoneg_wait_to_complete);
-s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
- bool *link_up, bool link_up_wait_to_complete);
-s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
- bool *autoneg);
-s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index);
-s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index);
-s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index);
-s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index);
-
-s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw);
-s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data);
-s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
- u16 words, u16 *data);
-s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data);
-s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
- u16 words, u16 *data);
-
-s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val);
-s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw);
-
-s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
-s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
- u32 enable_addr);
-s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index);
-s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
-s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq);
-s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
-s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw);
-u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw);
-s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
- u32 addr_count, ixgbe_mc_addr_itr func);
-s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
- u32 mc_addr_count, ixgbe_mc_addr_itr func,
- bool clear);
-void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr_list, u32 vmdq);
-s32 ixgbe_enable_mc(struct ixgbe_hw *hw);
-s32 ixgbe_disable_mc(struct ixgbe_hw *hw);
-s32 ixgbe_clear_vfta(struct ixgbe_hw *hw);
-s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan,
- u32 vind, bool vlan_on);
-s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind,
- bool vlan_on, bool *vfta_changed);
-s32 ixgbe_fc_enable(struct ixgbe_hw *hw);
-s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
- u8 ver);
-s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw);
-s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw);
-void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr);
-s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw,
- u16 *firmware_version);
-s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);
-s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);
-s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw);
-s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data);
-u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw);
-s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval);
-s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw);
-s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw);
-s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
-s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
-s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
-s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
- union ixgbe_atr_hash_dword input,
- union ixgbe_atr_hash_dword common,
- u8 queue);
-s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
- union ixgbe_atr_input *input_mask);
-s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
- union ixgbe_atr_input *input,
- u16 soft_id, u8 queue);
-s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
- union ixgbe_atr_input *input,
- u16 soft_id);
-s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
- union ixgbe_atr_input *input,
- union ixgbe_atr_input *mask,
- u16 soft_id,
- u8 queue);
-void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
- union ixgbe_atr_input *mask);
-u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
- union ixgbe_atr_hash_dword common);
-s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
- u8 *data);
-s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
- u8 data);
-s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data);
-s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
-s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
-s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps);
-s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
-void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
-s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
- u16 *wwpn_prefix);
-s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs);
-
-#endif /* _IXGBE_API_H_ */
diff --git a/kernel/linux/kni/ethtool/ixgbe/ixgbe_common.c b/kernel/linux/kni/ethtool/ixgbe/ixgbe_common.c
deleted file mode 100644
index e9b9529..0000000
--- a/kernel/linux/kni/ethtool/ixgbe/ixgbe_common.c
+++ /dev/null
@@ -1,4067 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*******************************************************************************
-
- Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2012 Intel Corporation.
-
- Contact Information:
- e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
- Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-
-#include "ixgbe_common.h"
-#include "ixgbe_phy.h"
-#include "ixgbe_api.h"
-
-static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
-static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
-static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
-static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
-static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
-static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
- u16 count);
-static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
-static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
-static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
-static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
-
-static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
-static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
- u16 *san_mac_offset);
-static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
- u16 words, u16 *data);
-static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
- u16 words, u16 *data);
-static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
- u16 offset);
-
-/**
- * ixgbe_init_ops_generic - Inits function ptrs
- * @hw: pointer to the hardware structure
- *
- * Initialize the function pointers.
- **/
-s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
-{
- struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
- struct ixgbe_mac_info *mac = &hw->mac;
- u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
-
- /* EEPROM */
- eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
- /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
- if (eec & IXGBE_EEC_PRES) {
- eeprom->ops.read = &ixgbe_read_eerd_generic;
- eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_generic;
- } else {
- eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
- eeprom->ops.read_buffer =
- &ixgbe_read_eeprom_buffer_bit_bang_generic;
- }
- eeprom->ops.write = &ixgbe_write_eeprom_generic;
- eeprom->ops.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic;
- eeprom->ops.validate_checksum =
- &ixgbe_validate_eeprom_checksum_generic;
- eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
- eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
-
- /* MAC */
- mac->ops.init_hw = &ixgbe_init_hw_generic;
- mac->ops.reset_hw = NULL;
- mac->ops.start_hw = &ixgbe_start_hw_generic;
- mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
- mac->ops.get_media_type = NULL;
- mac->ops.get_supported_physical_layer = NULL;
- mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
- mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
- mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
- mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
- mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
- mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
- mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
-
- /* LEDs */
- mac->ops.led_on = &ixgbe_led_on_generic;
- mac->ops.led_off = &ixgbe_led_off_generic;
- mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
- mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
-
- /* RAR, Multicast, VLAN */
- mac->ops.set_rar = &ixgbe_set_rar_generic;
- mac->ops.clear_rar = &ixgbe_clear_rar_generic;
- mac->ops.insert_mac_addr = NULL;
- mac->ops.set_vmdq = NULL;
- mac->ops.clear_vmdq = NULL;
- mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
- mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
- mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
- mac->ops.enable_mc = &ixgbe_enable_mc_generic;
- mac->ops.disable_mc = &ixgbe_disable_mc_generic;
- mac->ops.clear_vfta = NULL;
- mac->ops.set_vfta = NULL;
- mac->ops.set_vlvf = NULL;
- mac->ops.init_uta_tables = NULL;
-
- /* Flow Control */
- mac->ops.fc_enable = &ixgbe_fc_enable_generic;
-
- /* Link */
- mac->ops.get_link_capabilities = NULL;
- mac->ops.setup_link = NULL;
- mac->ops.check_link = NULL;
-
- return 0;
-}
-
-/**
- * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
- * control
- * @hw: pointer to hardware structure
- *
- * There are several phys that do not support autoneg flow control. This
- * function check the device id to see if the associated phy supports
- * autoneg flow control.
- **/
-static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
-{
-
- switch (hw->device_id) {
- case IXGBE_DEV_ID_X540T:
- return 0;
- case IXGBE_DEV_ID_82599_T3_LOM:
- return 0;
- default:
- return IXGBE_ERR_FC_NOT_SUPPORTED;
- }
-}
-
-/**
- * ixgbe_setup_fc - Set up flow control
- * @hw: pointer to hardware structure
- *
- * Called at init time to set up flow control.
- **/
-static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
-{
- s32 ret_val = 0;
- u32 reg = 0, reg_bp = 0;
- u16 reg_cu = 0;
-
- /*
- * Validate the requested mode. Strict IEEE mode does not allow
- * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
- */
- if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
- hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
- ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
- goto out;
- }
-
- /*
- * 10gig parts do not have a word in the EEPROM to determine the
- * default flow control setting, so we explicitly set it to full.
- */
- if (hw->fc.requested_mode == ixgbe_fc_default)
- hw->fc.requested_mode = ixgbe_fc_full;
-
- /*
- * Set up the 1G and 10G flow control advertisement registers so the
- * HW will be able to do fc autoneg once the cable is plugged in. If
- * we link at 10G, the 1G advertisement is harmless and vice versa.
- */
- switch (hw->phy.media_type) {
- case ixgbe_media_type_fiber:
- case ixgbe_media_type_backplane:
- reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
- reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
- break;
- case ixgbe_media_type_copper:
- hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg_cu);
- break;
- default:
- break;
- }
-
- /*
- * The possible values of fc.requested_mode are:
- * 0: Flow control is completely disabled
- * 1: Rx flow control is enabled (we can receive pause frames,
- * but not send pause frames).
- * 2: Tx flow control is enabled (we can send pause frames but
- * we do not support receiving pause frames).
- * 3: Both Rx and Tx flow control (symmetric) are enabled.
- * other: Invalid.
- */
- switch (hw->fc.requested_mode) {
- case ixgbe_fc_none:
- /* Flow control completely disabled by software override. */
- reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
- if (hw->phy.media_type == ixgbe_media_type_backplane)
- reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
- IXGBE_AUTOC_ASM_PAUSE);
- else if (hw->phy.media_type == ixgbe_media_type_copper)
- reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
- break;
- case ixgbe_fc_tx_pause:
- /*
- * Tx Flow control is enabled, and Rx Flow control is
- * disabled by software override.
- */
- reg |= IXGBE_PCS1GANA_ASM_PAUSE;
- reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
- if (hw->phy.media_type == ixgbe_media_type_backplane) {
- reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
- reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
- } else if (hw->phy.media_type == ixgbe_media_type_copper) {
- reg_cu |= IXGBE_TAF_ASM_PAUSE;
- reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
- }
- break;
- case ixgbe_fc_rx_pause:
- /*
- * Rx Flow control is enabled and Tx Flow control is
- * disabled by software override. Since there really
- * isn't a way to advertise that we are capable of RX
- * Pause ONLY, we will advertise that we support both
- * symmetric and asymmetric Rx PAUSE, as such we fall
- * through to the fc_full statement. Later, we will
- * disable the adapter's ability to send PAUSE frames.
- */
- case ixgbe_fc_full:
- /* Flow control (both Rx and Tx) is enabled by SW override. */
- reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
- if (hw->phy.media_type == ixgbe_media_type_backplane)
- reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
- IXGBE_AUTOC_ASM_PAUSE;
- else if (hw->phy.media_type == ixgbe_media_type_copper)
- reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
- break;
- default:
- hw_dbg(hw, "Flow control param set incorrectly\n");
- ret_val = IXGBE_ERR_CONFIG;
- goto out;
- break;
- }
-
- if (hw->mac.type != ixgbe_mac_X540) {
- /*
- * Enable auto-negotiation between the MAC & PHY;
- * the MAC will advertise clause 37 flow control.
- */
- IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
- reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
-
- /* Disable AN timeout */
- if (hw->fc.strict_ieee)
- reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
-
- IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
- hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
- }
-
- /*
- * AUTOC restart handles negotiation of 1G and 10G on backplane
- * and copper. There is no need to set the PCS1GCTL register.
- *
- */
- if (hw->phy.media_type == ixgbe_media_type_backplane) {
- reg_bp |= IXGBE_AUTOC_AN_RESTART;
- IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
- } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
- (ixgbe_device_supports_autoneg_fc(hw) == 0)) {
- hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
- }
-
- hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
-out:
- return ret_val;
-}
-
-/**
- * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
- * @hw: pointer to hardware structure
- *
- * Starts the hardware by filling the bus info structure and media type, clears
- * all on chip counters, initializes receive address registers, multicast
- * table, VLAN filter table, calls routine to set up link and flow control
- * settings, and leaves transmit and receive units disabled and uninitialized
- **/
-s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
-{
- s32 ret_val;
- u32 ctrl_ext;
-
- /* Set the media type */
- hw->phy.media_type = hw->mac.ops.get_media_type(hw);
-
- /* PHY ops initialization must be done in reset_hw() */
-
- /* Clear the VLAN filter table */
- hw->mac.ops.clear_vfta(hw);
-
- /* Clear statistics registers */
- hw->mac.ops.clear_hw_cntrs(hw);
-
- /* Set No Snoop Disable */
- ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
- ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
- IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
- IXGBE_WRITE_FLUSH(hw);
-
- /* Setup flow control */
- ret_val = ixgbe_setup_fc(hw);
- if (ret_val != 0)
- goto out;
-
- /* Clear adapter stopped flag */
- hw->adapter_stopped = false;
-
-out:
- return ret_val;
-}
-
-/**
- * ixgbe_start_hw_gen2 - Init sequence for common device family
- * @hw: pointer to hw structure
- *
- * Performs the init sequence common to the second generation
- * of 10 GbE devices.
- * Devices in the second generation:
- * 82599
- * X540
- **/
-s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
-{
- u32 i;
- u32 regval;
-
- /* Clear the rate limiters */
- for (i = 0; i < hw->mac.max_tx_queues; i++) {
- IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
- IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
- }
- IXGBE_WRITE_FLUSH(hw);
-
- /* Disable relaxed ordering */
- for (i = 0; i < hw->mac.max_tx_queues; i++) {
- regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
- regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
- IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
- }
-
- for (i = 0; i < hw->mac.max_rx_queues; i++) {
- regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
- regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
- IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
- IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
- }
-
- return 0;
-}
-
-/**
- * ixgbe_init_hw_generic - Generic hardware initialization
- * @hw: pointer to hardware structure
- *
- * Initialize the hardware by resetting the hardware, filling the bus info
- * structure and media type, clears all on chip counters, initializes receive
- * address registers, multicast table, VLAN filter table, calls routine to set
- * up link and flow control settings, and leaves transmit and receive units
- * disabled and uninitialized
- **/
-s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
-{
- s32 status;
-
- /* Reset the hardware */
- status = hw->mac.ops.reset_hw(hw);
-
- if (status == 0) {
- /* Start the HW */
- status = hw->mac.ops.start_hw(hw);
- }
-
- return status;
-}
-
-/**
- * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
- * @hw: pointer to hardware structure
- *
- * Clears all hardware statistics counters by reading them from the hardware
- * Statistics counters are clear on read.
- **/
-s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
-{
- u16 i = 0;
-
- IXGBE_READ_REG(hw, IXGBE_CRCERRS);
- IXGBE_READ_REG(hw, IXGBE_ILLERRC);
- IXGBE_READ_REG(hw, IXGBE_ERRBC);
- IXGBE_READ_REG(hw, IXGBE_MSPDC);
- for (i = 0; i < 8; i++)
- IXGBE_READ_REG(hw, IXGBE_MPC(i));
-
- IXGBE_READ_REG(hw, IXGBE_MLFC);
- IXGBE_READ_REG(hw, IXGBE_MRFC);
- IXGBE_READ_REG(hw, IXGBE_RLEC);
- IXGBE_READ_REG(hw, IXGBE_LXONTXC);
- IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
- if (hw->mac.type >= ixgbe_mac_82599EB) {
- IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
- IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
- } else {
- IXGBE_READ_REG(hw, IXGBE_LXONRXC);
- IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
- }
-
- for (i = 0; i < 8; i++) {
- IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
- IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
- if (hw->mac.type >= ixgbe_mac_82599EB) {
- IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
- IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
- } else {
- IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
- IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
- }
- }
- if (hw->mac.type >= ixgbe_mac_82599EB)
- for (i = 0; i < 8; i++)
- IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
- IXGBE_READ_REG(hw, IXGBE_PRC64);
- IXGBE_READ_REG(hw, IXGBE_PRC127);
- IXGBE_READ_REG(hw, IXGBE_PRC255);
- IXGBE_READ_REG(hw, IXGBE_PRC511);
- IXGBE_READ_REG(hw, IXGBE_PRC1023);
- IXGBE_READ_REG(hw, IXGBE_PRC1522);
- IXGBE_READ_REG(hw, IXGBE_GPRC);
- IXGBE_READ_REG(hw, IXGBE_BPRC);
- IXGBE_READ_REG(hw, IXGBE_MPRC);
- IXGBE_READ_REG(hw, IXGBE_GPTC);
- IXGBE_READ_REG(hw, IXGBE_GORCL);
- IXGBE_READ_REG(hw, IXGBE_GORCH);
- IXGBE_READ_REG(hw, IXGBE_GOTCL);
- IXGBE_READ_REG(hw, IXGBE_GOTCH);
- if (hw->mac.type == ixgbe_mac_82598EB)
- for (i = 0; i < 8; i++)
- IXGBE_READ_REG(hw, IXGBE_RNBC(i));
- IXGBE_READ_REG(hw, IXGBE_RUC);
- IXGBE_READ_REG(hw, IXGBE_RFC);
- IXGBE_READ_REG(hw, IXGBE_ROC);
- IXGBE_READ_REG(hw, IXGBE_RJC);
- IXGBE_READ_REG(hw, IXGBE_MNGPRC);
- IXGBE_READ_REG(hw, IXGBE_MNGPDC);
- IXGBE_READ_REG(hw, IXGBE_MNGPTC);
- IXGBE_READ_REG(hw, IXGBE_TORL);
- IXGBE_READ_REG(hw, IXGBE_TORH);
- IXGBE_READ_REG(hw, IXGBE_TPR);
- IXGBE_READ_REG(hw, IXGBE_TPT);
- IXGBE_READ_REG(hw, IXGBE_PTC64);
- IXGBE_READ_REG(hw, IXGBE_PTC127);
- IXGBE_READ_REG(hw, IXGBE_PTC255);
- IXGBE_READ_REG(hw, IXGBE_PTC511);
- IXGBE_READ_REG(hw, IXGBE_PTC1023);
- IXGBE_READ_REG(hw, IXGBE_PTC1522);
- IXGBE_READ_REG(hw, IXGBE_MPTC);
- IXGBE_READ_REG(hw, IXGBE_BPTC);
- for (i = 0; i < 16; i++) {
- IXGBE_READ_REG(hw, IXGBE_QPRC(i));
- IXGBE_READ_REG(hw, IXGBE_QPTC(i));
- if (hw->mac.type >= ixgbe_mac_82599EB) {
- IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
- IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
- IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
- IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
- IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
- } else {
- IXGBE_READ_REG(hw, IXGBE_QBRC(i));
- IXGBE_READ_REG(hw, IXGBE_QBTC(i));
- }
- }
-
- if (hw->mac.type == ixgbe_mac_X540) {
- if (hw->phy.id == 0)
- ixgbe_identify_phy(hw);
- hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
- IXGBE_MDIO_PCS_DEV_TYPE, &i);
- hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
- IXGBE_MDIO_PCS_DEV_TYPE, &i);
- hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
- IXGBE_MDIO_PCS_DEV_TYPE, &i);
- hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
- IXGBE_MDIO_PCS_DEV_TYPE, &i);
- }
-
- return 0;
-}
-
-/**
- * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
- * @hw: pointer to hardware structure
- * @pba_num: stores the part number string from the EEPROM
- * @pba_num_size: part number string buffer length
- *
- * Reads the part number string from the EEPROM.
- **/
-s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
- u32 pba_num_size)
-{
- s32 ret_val;
- u16 data;
- u16 pba_ptr;
- u16 offset;
- u16 length;
-
- if (pba_num == NULL) {
- hw_dbg(hw, "PBA string buffer was null\n");
- return IXGBE_ERR_INVALID_ARGUMENT;
- }
-
- ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
- if (ret_val) {
- hw_dbg(hw, "NVM Read Error\n");
- return ret_val;
- }
-
- ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
- if (ret_val) {
- hw_dbg(hw, "NVM Read Error\n");
- return ret_val;
- }
-
- /*
- * if data is not ptr guard the PBA must be in legacy format which
- * means pba_ptr is actually our second data word for the PBA number
- * and we can decode it into an ascii string
- */
- if (data != IXGBE_PBANUM_PTR_GUARD) {
- hw_dbg(hw, "NVM PBA number is not stored as string\n");
-
- /* we will need 11 characters to store the PBA */
- if (pba_num_size < 11) {
- hw_dbg(hw, "PBA string buffer too small\n");
- return IXGBE_ERR_NO_SPACE;
- }
-
- /* extract hex string from data and pba_ptr */
- pba_num[0] = (data >> 12) & 0xF;
- pba_num[1] = (data >> 8) & 0xF;
- pba_num[2] = (data >> 4) & 0xF;
- pba_num[3] = data & 0xF;
- pba_num[4] = (pba_ptr >> 12) & 0xF;
- pba_num[5] = (pba_ptr >> 8) & 0xF;
- pba_num[6] = '-';
- pba_num[7] = 0;
- pba_num[8] = (pba_ptr >> 4) & 0xF;
- pba_num[9] = pba_ptr & 0xF;
-
- /* put a null character on the end of our string */
- pba_num[10] = '\0';
-
- /* switch all the data but the '-' to hex char */
- for (offset = 0; offset < 10; offset++) {
- if (pba_num[offset] < 0xA)
- pba_num[offset] += '0';
- else if (pba_num[offset] < 0x10)
- pba_num[offset] += 'A' - 0xA;
- }
-
- return 0;
- }
-
- ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
- if (ret_val) {
- hw_dbg(hw, "NVM Read Error\n");
- return ret_val;
- }
-
- if (length == 0xFFFF || length == 0) {
- hw_dbg(hw, "NVM PBA number section invalid length\n");
- return IXGBE_ERR_PBA_SECTION;
- }
-
- /* check if pba_num buffer is big enough */
- if (pba_num_size < (((u32)length * 2) - 1)) {
- hw_dbg(hw, "PBA string buffer too small\n");
- return IXGBE_ERR_NO_SPACE;
- }
-
- /* trim pba length from start of string */
- pba_ptr++;
- length--;
-
- for (offset = 0; offset < length; offset++) {
- ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
- if (ret_val) {
- hw_dbg(hw, "NVM Read Error\n");
- return ret_val;
- }
- pba_num[offset * 2] = (u8)(data >> 8);
- pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
- }
- pba_num[offset * 2] = '\0';
-
- return 0;
-}
-
-/**
- * ixgbe_get_mac_addr_generic - Generic get MAC address
- * @hw: pointer to hardware structure
- * @mac_addr: Adapter MAC address
- *
- * Reads the adapter's MAC address from first Receive Address Register (RAR0)
- * A reset of the adapter must be performed prior to calling this function
- * in order for the MAC address to have been loaded from the EEPROM into RAR0
- **/
-s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
-{
- u32 rar_high;
- u32 rar_low;
- u16 i;
-
- rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
- rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
-
- for (i = 0; i < 4; i++)
- mac_addr[i] = (u8)(rar_low >> (i*8));
-
- for (i = 0; i < 2; i++)
- mac_addr[i+4] = (u8)(rar_high >> (i*8));
-
- return 0;
-}
-
-/**
- * ixgbe_get_bus_info_generic - Generic set PCI bus info
- * @hw: pointer to hardware structure
- *
- * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
- **/
-s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
-{
- struct ixgbe_mac_info *mac = &hw->mac;
- u16 link_status;
-
- hw->bus.type = ixgbe_bus_type_pci_express;
-
- /* Get the negotiated link width and speed from PCI config space */
- link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
-
- switch (link_status & IXGBE_PCI_LINK_WIDTH) {
- case IXGBE_PCI_LINK_WIDTH_1:
- hw->bus.width = ixgbe_bus_width_pcie_x1;
- break;
- case IXGBE_PCI_LINK_WIDTH_2:
- hw->bus.width = ixgbe_bus_width_pcie_x2;
- break;
- case IXGBE_PCI_LINK_WIDTH_4:
- hw->bus.width = ixgbe_bus_width_pcie_x4;
- break;
- case IXGBE_PCI_LINK_WIDTH_8:
- hw->bus.width = ixgbe_bus_width_pcie_x8;
- break;
- default:
- hw->bus.width = ixgbe_bus_width_unknown;
- break;
- }
-
- switch (link_status & IXGBE_PCI_LINK_SPEED) {
- case IXGBE_PCI_LINK_SPEED_2500:
- hw->bus.speed = ixgbe_bus_speed_2500;
- break;
- case IXGBE_PCI_LINK_SPEED_5000:
- hw->bus.speed = ixgbe_bus_speed_5000;
- break;
- case IXGBE_PCI_LINK_SPEED_8000:
- hw->bus.speed = ixgbe_bus_speed_8000;
- break;
- default:
- hw->bus.speed = ixgbe_bus_speed_unknown;
- break;
- }
-
- mac->ops.set_lan_id(hw);
-
- return 0;
-}
-
-/**
- * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
- * @hw: pointer to the HW structure
- *
- * Determines the LAN function id by reading memory-mapped registers
- * and swaps the port value if requested.
- **/
-void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
-{
- struct ixgbe_bus_info *bus = &hw->bus;
- u32 reg;
-
- reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
- bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
- bus->lan_id = bus->func;
-
- /* check for a port swap */
- reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
- if (reg & IXGBE_FACTPS_LFS)
- bus->func ^= 0x1;
-}
-
-/**
- * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
- * @hw: pointer to hardware structure
- *
- * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
- * disables transmit and receive units. The adapter_stopped flag is used by
- * the shared code and drivers to determine if the adapter is in a stopped
- * state and should not touch the hardware.
- **/
-s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
-{
- u32 reg_val;
- u16 i;
-
- /*
- * Set the adapter_stopped flag so other driver functions stop touching
- * the hardware
- */
- hw->adapter_stopped = true;
-
- /* Disable the receive unit */
- IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
-
- /* Clear interrupt mask to stop interrupts from being generated */
- IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
-
- /* Clear any pending interrupts, flush previous writes */
- IXGBE_READ_REG(hw, IXGBE_EICR);
-
- /* Disable the transmit unit. Each queue must be disabled. */
- for (i = 0; i < hw->mac.max_tx_queues; i++)
- IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
-
- /* Disable the receive unit by stopping each queue */
- for (i = 0; i < hw->mac.max_rx_queues; i++) {
- reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
- reg_val &= ~IXGBE_RXDCTL_ENABLE;
- reg_val |= IXGBE_RXDCTL_SWFLSH;
- IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
- }
-
- /* flush all queues disables */
- IXGBE_WRITE_FLUSH(hw);
- msleep(2);
-
- /*
- * Prevent the PCI-E bus from from hanging by disabling PCI-E master
- * access and verify no pending requests
- */
- return ixgbe_disable_pcie_master(hw);
-}
-
-/**
- * ixgbe_led_on_generic - Turns on the software controllable LEDs.
- * @hw: pointer to hardware structure
- * @index: led number to turn on
- **/
-s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
-{
- u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
-
- /* To turn on the LED, set mode to ON. */
- led_reg &= ~IXGBE_LED_MODE_MASK(index);
- led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
- IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
- IXGBE_WRITE_FLUSH(hw);
-
- return 0;
-}
-
-/**
- * ixgbe_led_off_generic - Turns off the software controllable LEDs.
- * @hw: pointer to hardware structure
- * @index: led number to turn off
- **/
-s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
-{
- u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
-
- /* To turn off the LED, set mode to OFF. */
- led_reg &= ~IXGBE_LED_MODE_MASK(index);
- led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
- IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
- IXGBE_WRITE_FLUSH(hw);
-
- return 0;
-}
-
-/**
- * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
- * @hw: pointer to hardware structure
- *
- * Initializes the EEPROM parameters ixgbe_eeprom_info within the
- * ixgbe_hw struct in order to set up EEPROM access.
- **/
-s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
-{
- struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
- u32 eec;
- u16 eeprom_size;
-
- if (eeprom->type == ixgbe_eeprom_uninitialized) {
- eeprom->type = ixgbe_eeprom_none;
- /* Set default semaphore delay to 10ms which is a well
- * tested value */
- eeprom->semaphore_delay = 10;
- /* Clear EEPROM page size, it will be initialized as needed */
- eeprom->word_page_size = 0;
-
- /*
- * Check for EEPROM present first.
- * If not present leave as none
- */
- eec = IXGBE_READ_REG(hw, IXGBE_EEC);
- if (eec & IXGBE_EEC_PRES) {
- eeprom->type = ixgbe_eeprom_spi;
-
- /*
- * SPI EEPROM is assumed here. This code would need to
- * change if a future EEPROM is not SPI.
- */
- eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
- IXGBE_EEC_SIZE_SHIFT);
- eeprom->word_size = 1 << (eeprom_size +
- IXGBE_EEPROM_WORD_SIZE_SHIFT);
- }
-
- if (eec & IXGBE_EEC_ADDR_SIZE)
- eeprom->address_bits = 16;
- else
- eeprom->address_bits = 8;
- hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
- "%d\n", eeprom->type, eeprom->word_size,
- eeprom->address_bits);
- }
-
- return 0;
-}
-
-/**
- * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
- * @hw: pointer to hardware structure
- * @offset: offset within the EEPROM to write
- * @words: number of word(s)
- * @data: 16 bit word(s) to write to EEPROM
- *
- * Reads 16 bit word(s) from EEPROM through bit-bang method
- **/
-s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
- u16 words, u16 *data)
-{
- s32 status = 0;
- u16 i, count;
-
- hw->eeprom.ops.init_params(hw);
-
- if (words == 0) {
- status = IXGBE_ERR_INVALID_ARGUMENT;
- goto out;
- }
-
- if (offset + words > hw->eeprom.word_size) {
- status = IXGBE_ERR_EEPROM;
- goto out;
- }
-
- /*
- * The EEPROM page size cannot be queried from the chip. We do lazy
- * initialization. It is worth to do that when we write large buffer.
- */
- if ((hw->eeprom.word_page_size == 0) &&
- (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
- ixgbe_detect_eeprom_page_size_generic(hw, offset);
-
- /*
- * We cannot hold synchronization semaphores for too long
- * to avoid other entity starvation. However it is more efficient
- * to read in bursts than synchronizing access for each word.
- */
- for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
- count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
- IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
- status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
- count, &data[i]);
-
- if (status != 0)
- break;
- }
-
-out:
- return status;
-}
-
-/**
- * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
- * @hw: pointer to hardware structure
- * @offset: offset within the EEPROM to be written to
- * @words: number of word(s)
- * @data: 16 bit word(s) to be written to the EEPROM
- *
- * If ixgbe_eeprom_update_checksum is not called after this function, the
- * EEPROM will most likely contain an invalid checksum.
- **/
-static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
- u16 words, u16 *data)
-{
- s32 status;
- u16 word;
- u16 page_size;
- u16 i;
- u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
-
- /* Prepare the EEPROM for writing */
- status = ixgbe_acquire_eeprom(hw);
-
- if (status == 0) {
- if (ixgbe_ready_eeprom(hw) != 0) {
- ixgbe_release_eeprom(hw);
- status = IXGBE_ERR_EEPROM;
- }
- }
-
- if (status == 0) {
- for (i = 0; i < words; i++) {
- ixgbe_standby_eeprom(hw);
-
- /* Send the WRITE ENABLE command (8 bit opcode ) */
- ixgbe_shift_out_eeprom_bits(hw,
- IXGBE_EEPROM_WREN_OPCODE_SPI,
- IXGBE_EEPROM_OPCODE_BITS);
-
- ixgbe_standby_eeprom(hw);
-
- /*
- * Some SPI eeproms use the 8th address bit embedded
- * in the opcode
- */
- if ((hw->eeprom.address_bits == 8) &&
- ((offset + i) >= 128))
- write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
-
- /* Send the Write command (8-bit opcode + addr) */
- ixgbe_shift_out_eeprom_bits(hw, write_opcode,
- IXGBE_EEPROM_OPCODE_BITS);
- ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
- hw->eeprom.address_bits);
-
- page_size = hw->eeprom.word_page_size;
-
- /* Send the data in burst via SPI*/
- do {
- word = data[i];
- word = (word >> 8) | (word << 8);
- ixgbe_shift_out_eeprom_bits(hw, word, 16);
-
- if (page_size == 0)
- break;
-
- /* do not wrap around page */
- if (((offset + i) & (page_size - 1)) ==
- (page_size - 1))
- break;
- } while (++i < words);
-
- ixgbe_standby_eeprom(hw);
- msleep(10);
- }
- /* Done with writing - release the EEPROM */
- ixgbe_release_eeprom(hw);
- }
-
- return status;
-}
-
-/**
- * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
- * @hw: pointer to hardware structure
- * @offset: offset within the EEPROM to be written to
- * @data: 16 bit word to be written to the EEPROM
- *
- * If ixgbe_eeprom_update_checksum is not called after this function, the
- * EEPROM will most likely contain an invalid checksum.
- **/
-s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
-{
- s32 status;
-
- hw->eeprom.ops.init_params(hw);
-
- if (offset >= hw->eeprom.word_size) {
- status = IXGBE_ERR_EEPROM;
- goto out;
- }
-
- status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
-
-out:
- return status;
-}
-
-/**
- * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
- * @hw: pointer to hardware structure
- * @offset: offset within the EEPROM to be read
- * @data: read 16 bit words(s) from EEPROM
- * @words: number of word(s)
- *
- * Reads 16 bit word(s) from EEPROM through bit-bang method
- **/
-s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
- u16 words, u16 *data)
-{
- s32 status = 0;
- u16 i, count;
-
- hw->eeprom.ops.init_params(hw);
-
- if (words == 0) {
- status = IXGBE_ERR_INVALID_ARGUMENT;
- goto out;
- }
-
- if (offset + words > hw->eeprom.word_size) {
- status = IXGBE_ERR_EEPROM;
- goto out;
- }
-
- /*
- * We cannot hold synchronization semaphores for too long
- * to avoid other entity starvation. However it is more efficient
- * to read in bursts than synchronizing access for each word.
- */
- for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
- count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
- IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
-
- status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
- count, &data[i]);
-
- if (status != 0)
- break;
- }
-
-out:
- return status;
-}
-
-/**
- * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
- * @hw: pointer to hardware structure
- * @offset: offset within the EEPROM to be read
- * @words: number of word(s)
- * @data: read 16 bit word(s) from EEPROM
- *
- * Reads 16 bit word(s) from EEPROM through bit-bang method
- **/
-static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
- u16 words, u16 *data)
-{
- s32 status;
- u16 word_in;
- u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
- u16 i;
-
- /* Prepare the EEPROM for reading */
- status = ixgbe_acquire_eeprom(hw);
-
- if (status == 0) {
- if (ixgbe_ready_eeprom(hw) != 0) {
- ixgbe_release_eeprom(hw);
- status = IXGBE_ERR_EEPROM;
- }
- }
-
- if (status == 0) {
- for (i = 0; i < words; i++) {
- ixgbe_standby_eeprom(hw);
- /*
- * Some SPI eeproms use the 8th address bit embedded
- * in the opcode
- */
- if ((hw->eeprom.address_bits == 8) &&
- ((offset + i) >= 128))
- read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
-
- /* Send the READ command (opcode + addr) */
- ixgbe_shift_out_eeprom_bits(hw, read_opcode,
- IXGBE_EEPROM_OPCODE_BITS);
- ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
- hw->eeprom.address_bits);
-
- /* Read the data. */
- word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
- data[i] = (word_in >> 8) | (word_in << 8);
- }
-
- /* End this read operation */
- ixgbe_release_eeprom(hw);
- }
-
- return status;
-}
-
-/**
- * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
- * @hw: pointer to hardware structure
- * @offset: offset within the EEPROM to be read
- * @data: read 16 bit value from EEPROM
- *
- * Reads 16 bit value from EEPROM through bit-bang method
- **/
-s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
- u16 *data)
-{
- s32 status;
-
- hw->eeprom.ops.init_params(hw);
-
- if (offset >= hw->eeprom.word_size) {
- status = IXGBE_ERR_EEPROM;
- goto out;
- }
-
- status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
-
-out:
- return status;
-}
-
-/**
- * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
- * @hw: pointer to hardware structure
- * @offset: offset of word in the EEPROM to read
- * @words: number of word(s)
- * @data: 16 bit word(s) from the EEPROM
- *
- * Reads a 16 bit word(s) from the EEPROM using the EERD register.
- **/
-s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
- u16 words, u16 *data)
-{
- u32 eerd;
- s32 status = 0;
- u32 i;
-
- hw->eeprom.ops.init_params(hw);
-
- if (words == 0) {
- status = IXGBE_ERR_INVALID_ARGUMENT;
- goto out;
- }
-
- if (offset >= hw->eeprom.word_size) {
- status = IXGBE_ERR_EEPROM;
- goto out;
- }
-
- for (i = 0; i < words; i++) {
- eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) +
- IXGBE_EEPROM_RW_REG_START;
-
- IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
- status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
-
- if (status == 0) {
- data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
- IXGBE_EEPROM_RW_REG_DATA);
- } else {
- hw_dbg(hw, "Eeprom read timed out\n");
- goto out;
- }
- }
-out:
- return status;
-}
-
-/**
- * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
- * @hw: pointer to hardware structure
- * @offset: offset within the EEPROM to be used as a scratch pad
- *
- * Discover EEPROM page size by writing marching data at given offset.
- * This function is called only when we are writing a new large buffer
- * at given offset so the data would be overwritten anyway.
- **/
-static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
- u16 offset)
-{
- u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
- s32 status = 0;
- u16 i;
-
- for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
- data[i] = i;
-
- hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
- status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
- IXGBE_EEPROM_PAGE_SIZE_MAX, data);
- hw->eeprom.word_page_size = 0;
- if (status != 0)
- goto out;
-
- status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
- if (status != 0)
- goto out;
-
- /*
- * When writing in burst more than the actual page size
- * EEPROM address wraps around current page.
- */
- hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
-
- hw_dbg(hw, "Detected EEPROM page size = %d words.",
- hw->eeprom.word_page_size);
-out:
- return status;
-}
-
-/**
- * ixgbe_read_eerd_generic - Read EEPROM word using EERD
- * @hw: pointer to hardware structure
- * @offset: offset of word in the EEPROM to read
- * @data: word read from the EEPROM
- *
- * Reads a 16 bit word from the EEPROM using the EERD register.
- **/
-s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
-{
- return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
-}
-
-/**
- * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
- * @hw: pointer to hardware structure
- * @offset: offset of word in the EEPROM to write
- * @words: number of word(s)
- * @data: word(s) write to the EEPROM
- *
- * Write a 16 bit word(s) to the EEPROM using the EEWR register.
- **/
-s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
- u16 words, u16 *data)
-{
- u32 eewr;
- s32 status = 0;
- u16 i;
-
- hw->eeprom.ops.init_params(hw);
-
- if (words == 0) {
- status = IXGBE_ERR_INVALID_ARGUMENT;
- goto out;
- }
-
- if (offset >= hw->eeprom.word_size) {
- status = IXGBE_ERR_EEPROM;
- goto out;
- }
-
- for (i = 0; i < words; i++) {
- eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
- (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
- IXGBE_EEPROM_RW_REG_START;
-
- status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
- if (status != 0) {
- hw_dbg(hw, "Eeprom write EEWR timed out\n");
- goto out;
- }
-
- IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
-
- status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
- if (status != 0) {
- hw_dbg(hw, "Eeprom write EEWR timed out\n");
- goto out;
- }
- }
-
-out:
- return status;
-}
-
-/**
- * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
- * @hw: pointer to hardware structure
- * @offset: offset of word in the EEPROM to write
- * @data: word write to the EEPROM
- *
- * Write a 16 bit word to the EEPROM using the EEWR register.
- **/
-s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
-{
- return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
-}
-
-/**
- * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
- * @hw: pointer to hardware structure
- * @ee_reg: EEPROM flag for polling
- *
- * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
- * read or write is done respectively.
- **/
-s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
-{
- u32 i;
- u32 reg;
- s32 status = IXGBE_ERR_EEPROM;
-
- for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
- if (ee_reg == IXGBE_NVM_POLL_READ)
- reg = IXGBE_READ_REG(hw, IXGBE_EERD);
- else
- reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
-
- if (reg & IXGBE_EEPROM_RW_REG_DONE) {
- status = 0;
- break;
- }
- udelay(5);
- }
- return status;
-}
-
-/**
- * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
- * @hw: pointer to hardware structure
- *
- * Prepares EEPROM for access using bit-bang method. This function should
- * be called before issuing a command to the EEPROM.
- **/
-static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
-{
- s32 status = 0;
- u32 eec;
- u32 i;
-
- if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
- != 0)
- status = IXGBE_ERR_SWFW_SYNC;
-
- if (status == 0) {
- eec = IXGBE_READ_REG(hw, IXGBE_EEC);
-
- /* Request EEPROM Access */
- eec |= IXGBE_EEC_REQ;
- IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
-
- for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
- eec = IXGBE_READ_REG(hw, IXGBE_EEC);
- if (eec & IXGBE_EEC_GNT)
- break;
- udelay(5);
- }
-
- /* Release if grant not acquired */
- if (!(eec & IXGBE_EEC_GNT)) {
- eec &= ~IXGBE_EEC_REQ;
- IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
- hw_dbg(hw, "Could not acquire EEPROM grant\n");
-
- hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
- status = IXGBE_ERR_EEPROM;
- }
-
- /* Setup EEPROM for Read/Write */
- if (status == 0) {
- /* Clear CS and SK */
- eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
- IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
- IXGBE_WRITE_FLUSH(hw);
- udelay(1);
- }
- }
- return status;
-}
-
-/**
- * ixgbe_get_eeprom_semaphore - Get hardware semaphore
- * @hw: pointer to hardware structure
- *
- * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
- **/
-static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
-{
- s32 status = IXGBE_ERR_EEPROM;
- u32 timeout = 2000;
- u32 i;
- u32 swsm;
-
- /* Get SMBI software semaphore between device drivers first */
- for (i = 0; i < timeout; i++) {
- /*
- * If the SMBI bit is 0 when we read it, then the bit will be
- * set and we have the semaphore
- */
- swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
- if (!(swsm & IXGBE_SWSM_SMBI)) {
- status = 0;
- break;
- }
- udelay(50);
- }
-
- if (i == timeout) {
- hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore "
- "not granted.\n");
- /*
- * this release is particularly important because our attempts
- * above to get the semaphore may have succeeded, and if there
- * was a timeout, we should unconditionally clear the semaphore
- * bits to free the driver to make progress
- */
- ixgbe_release_eeprom_semaphore(hw);
-
- udelay(50);
- /*
- * one last try
- * If the SMBI bit is 0 when we read it, then the bit will be
- * set and we have the semaphore
- */
- swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
- if (!(swsm & IXGBE_SWSM_SMBI))
- status = 0;
- }
-
- /* Now get the semaphore between SW/FW through the SWESMBI bit */
- if (status == 0) {
- for (i = 0; i < timeout; i++) {
- swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
-
- /* Set the SW EEPROM semaphore bit to request access */
- swsm |= IXGBE_SWSM_SWESMBI;
- IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
-
- /*
- * If we set the bit successfully then we got the
- * semaphore.
- */
- swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
- if (swsm & IXGBE_SWSM_SWESMBI)
- break;
-
- udelay(50);
- }
-
- /*
- * Release semaphores and return error if SW EEPROM semaphore
- * was not granted because we don't have access to the EEPROM
- */
- if (i >= timeout) {
- hw_dbg(hw, "SWESMBI Software EEPROM semaphore "
- "not granted.\n");
- ixgbe_release_eeprom_semaphore(hw);
- status = IXGBE_ERR_EEPROM;
- }
- } else {
- hw_dbg(hw, "Software semaphore SMBI between device drivers "
- "not granted.\n");
- }
-
- return status;
-}
-
-/**
- * ixgbe_release_eeprom_semaphore - Release hardware semaphore
- * @hw: pointer to hardware structure
- *
- * This function clears hardware semaphore bits.
- **/
-static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
-{
- u32 swsm;
-
- swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
-
- /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
- swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
- IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
- IXGBE_WRITE_FLUSH(hw);
-}
-
-/**
- * ixgbe_ready_eeprom - Polls for EEPROM ready
- * @hw: pointer to hardware structure
- **/
-static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
-{
- s32 status = 0;
- u16 i;
- u8 spi_stat_reg;
-
- /*
- * Read "Status Register" repeatedly until the LSB is cleared. The
- * EEPROM will signal that the command has been completed by clearing
- * bit 0 of the internal status register. If it's not cleared within
- * 5 milliseconds, then error out.
- */
- for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
- ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
- IXGBE_EEPROM_OPCODE_BITS);
- spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
- if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
- break;
-
- udelay(5);
- ixgbe_standby_eeprom(hw);
- };
-
- /*
- * On some parts, SPI write time could vary from 0-20mSec on 3.3V
- * devices (and only 0-5mSec on 5V devices)
- */
- if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
- hw_dbg(hw, "SPI EEPROM Status error\n");
- status = IXGBE_ERR_EEPROM;
- }
-
- return status;
-}
-
-/**
- * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
- * @hw: pointer to hardware structure
- **/
-static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
-{
- u32 eec;
-
- eec = IXGBE_READ_REG(hw, IXGBE_EEC);
-
- /* Toggle CS to flush commands */
- eec |= IXGBE_EEC_CS;
- IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
- IXGBE_WRITE_FLUSH(hw);
- udelay(1);
- eec &= ~IXGBE_EEC_CS;
- IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
- IXGBE_WRITE_FLUSH(hw);
- udelay(1);
-}
-
-/**
- * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
- * @hw: pointer to hardware structure
- * @data: data to send to the EEPROM
- * @count: number of bits to shift out
- **/
-static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
- u16 count)
-{
- u32 eec;
- u32 mask;
- u32 i;
-
- eec = IXGBE_READ_REG(hw, IXGBE_EEC);
-
- /*
- * Mask is used to shift "count" bits of "data" out to the EEPROM
- * one bit at a time. Determine the starting bit based on count
- */
- mask = 0x01 << (count - 1);
-
- for (i = 0; i < count; i++) {
- /*
- * A "1" is shifted out to the EEPROM by setting bit "DI" to a
- * "1", and then raising and then lowering the clock (the SK
- * bit controls the clock input to the EEPROM). A "0" is
- * shifted out to the EEPROM by setting "DI" to "0" and then
- * raising and then lowering the clock.
- */
- if (data & mask)
- eec |= IXGBE_EEC_DI;
- else
- eec &= ~IXGBE_EEC_DI;
-
- IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
- IXGBE_WRITE_FLUSH(hw);
-
- udelay(1);
-
- ixgbe_raise_eeprom_clk(hw, &eec);
- ixgbe_lower_eeprom_clk(hw, &eec);
-
- /*
- * Shift mask to signify next bit of data to shift in to the
- * EEPROM
- */
- mask = mask >> 1;
- };
-
- /* We leave the "DI" bit set to "0" when we leave this routine. */
- eec &= ~IXGBE_EEC_DI;
- IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
- IXGBE_WRITE_FLUSH(hw);
-}
-
-/**
- * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
- * @hw: pointer to hardware structure
- **/
-static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
-{
- u32 eec;
- u32 i;
- u16 data = 0;
-
- /*
- * In order to read a register from the EEPROM, we need to shift
- * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
- * the clock input to the EEPROM (setting the SK bit), and then reading
- * the value of the "DO" bit. During this "shifting in" process the
- * "DI" bit should always be clear.
- */
- eec = IXGBE_READ_REG(hw, IXGBE_EEC);
-
- eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
-
- for (i = 0; i < count; i++) {
- data = data << 1;
- ixgbe_raise_eeprom_clk(hw, &eec);
-
- eec = IXGBE_READ_REG(hw, IXGBE_EEC);
-
- eec &= ~(IXGBE_EEC_DI);
- if (eec & IXGBE_EEC_DO)
- data |= 1;
-
- ixgbe_lower_eeprom_clk(hw, &eec);
- }
-
- return data;
-}
-
-/**
- * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
- * @hw: pointer to hardware structure
- * @eec: EEC register's current value
- **/
-static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
-{
- /*
- * Raise the clock input to the EEPROM
- * (setting the SK bit), then delay
- */
- *eec = *eec | IXGBE_EEC_SK;
- IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
- IXGBE_WRITE_FLUSH(hw);
- udelay(1);
-}
-
-/**
- * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
- * @hw: pointer to hardware structure
- * @eecd: EECD's current value
- **/
-static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
-{
- /*
- * Lower the clock input to the EEPROM (clearing the SK bit), then
- * delay
- */
- *eec = *eec & ~IXGBE_EEC_SK;
- IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
- IXGBE_WRITE_FLUSH(hw);
- udelay(1);
-}
-
-/**
- * ixgbe_release_eeprom - Release EEPROM, release semaphores
- * @hw: pointer to hardware structure
- **/
-static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
-{
- u32 eec;
-
- eec = IXGBE_READ_REG(hw, IXGBE_EEC);
-
- eec |= IXGBE_EEC_CS; /* Pull CS high */
- eec &= ~IXGBE_EEC_SK; /* Lower SCK */
-
- IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
- IXGBE_WRITE_FLUSH(hw);
-
- udelay(1);
-
- /* Stop requesting EEPROM access */
- eec &= ~IXGBE_EEC_REQ;
- IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
-
- hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
-
- /* Delay before attempt to obtain semaphore again to allow FW access */
- msleep(hw->eeprom.semaphore_delay);
-}
-
-/**
- * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
- * @hw: pointer to hardware structure
- **/
-u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
-{
- u16 i;
- u16 j;
- u16 checksum = 0;
- u16 length = 0;
- u16 pointer = 0;
- u16 word = 0;
-
- /* Include 0x0-0x3F in the checksum */
- for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
- if (hw->eeprom.ops.read(hw, i, &word) != 0) {
- hw_dbg(hw, "EEPROM read failed\n");
- break;
- }
- checksum += word;
- }
-
- /* Include all data from pointers except for the fw pointer */
- for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
- hw->eeprom.ops.read(hw, i, &pointer);
-
- /* Make sure the pointer seems valid */
- if (pointer != 0xFFFF && pointer != 0) {
- hw->eeprom.ops.read(hw, pointer, &length);
-
- if (length != 0xFFFF && length != 0) {
- for (j = pointer+1; j <= pointer+length; j++) {
- hw->eeprom.ops.read(hw, j, &word);
- checksum += word;
- }
- }
- }
- }
-
- checksum = (u16)IXGBE_EEPROM_SUM - checksum;
-
- return checksum;
-}
-
-/**
- * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
- * @hw: pointer to hardware structure
- * @checksum_val: calculated checksum
- *
- * Performs checksum calculation and validates the EEPROM checksum. If the
- * caller does not need checksum_val, the value can be NULL.
- **/
-s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
- u16 *checksum_val)
-{
- s32 status;
- u16 checksum;
- u16 read_checksum = 0;
-
- /*
- * Read the first word from the EEPROM. If this times out or fails, do
- * not continue or we could be in for a very long wait while every
- * EEPROM read fails
- */
- status = hw->eeprom.ops.read(hw, 0, &checksum);
-
- if (status == 0) {
- checksum = hw->eeprom.ops.calc_checksum(hw);
-
- hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
-
- /*
- * Verify read checksum from EEPROM is the same as
- * calculated checksum
- */
- if (read_checksum != checksum)
- status = IXGBE_ERR_EEPROM_CHECKSUM;
-
- /* If the user cares, return the calculated checksum */
- if (checksum_val)
- *checksum_val = checksum;
- } else {
- hw_dbg(hw, "EEPROM read failed\n");
- }
-
- return status;
-}
-
-/**
- * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
- * @hw: pointer to hardware structure
- **/
-s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
-{
- s32 status;
- u16 checksum;
-
- /*
- * Read the first word from the EEPROM. If this times out or fails, do
- * not continue or we could be in for a very long wait while every
- * EEPROM read fails
- */
- status = hw->eeprom.ops.read(hw, 0, &checksum);
-
- if (status == 0) {
- checksum = hw->eeprom.ops.calc_checksum(hw);
- status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
- checksum);
- } else {
- hw_dbg(hw, "EEPROM read failed\n");
- }
-
- return status;
-}
-
-/**
- * ixgbe_validate_mac_addr - Validate MAC address
- * @mac_addr: pointer to MAC address.
- *
- * Tests a MAC address to ensure it is a valid Individual Address
- **/
-s32 ixgbe_validate_mac_addr(u8 *mac_addr)
-{
- s32 status = 0;
-
- /* Make sure it is not a multicast address */
- if (IXGBE_IS_MULTICAST(mac_addr)) {
- hw_dbg(hw, "MAC address is multicast\n");
- status = IXGBE_ERR_INVALID_MAC_ADDR;
- /* Not a broadcast address */
- } else if (IXGBE_IS_BROADCAST(mac_addr)) {
- hw_dbg(hw, "MAC address is broadcast\n");
- status = IXGBE_ERR_INVALID_MAC_ADDR;
- /* Reject the zero address */
- } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
- mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
- hw_dbg(hw, "MAC address is all zeros\n");
- status = IXGBE_ERR_INVALID_MAC_ADDR;
- }
- return status;
-}
-
-/**
- * ixgbe_set_rar_generic - Set Rx address register
- * @hw: pointer to hardware structure
- * @index: Receive address register to write
- * @addr: Address to put into receive address register
- * @vmdq: VMDq "set" or "pool" index
- * @enable_addr: set flag that address is active
- *
- * Puts an ethernet address into a receive address register.
- **/
-s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
- u32 enable_addr)
-{
- u32 rar_low, rar_high;
- u32 rar_entries = hw->mac.num_rar_entries;
-
- /* Make sure we are using a valid rar index range */
- if (index >= rar_entries) {
- hw_dbg(hw, "RAR index %d is out of range.\n", index);
- return IXGBE_ERR_INVALID_ARGUMENT;
- }
-
- /* setup VMDq pool selection before this RAR gets enabled */
- hw->mac.ops.set_vmdq(hw, index, vmdq);
-
- /*
- * HW expects these in little endian so we reverse the byte
- * order from network order (big endian) to little endian
- */
- rar_low = ((u32)addr[0] |
- ((u32)addr[1] << 8) |
- ((u32)addr[2] << 16) |
- ((u32)addr[3] << 24));
- /*
- * Some parts put the VMDq setting in the extra RAH bits,
- * so save everything except the lower 16 bits that hold part
- * of the address and the address valid bit.
- */
- rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
- rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
- rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
-
- if (enable_addr != 0)
- rar_high |= IXGBE_RAH_AV;
-
- IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
- IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
-
- return 0;
-}
-
-/**
- * ixgbe_clear_rar_generic - Remove Rx address register
- * @hw: pointer to hardware structure
- * @index: Receive address register to write
- *
- * Clears an ethernet address from a receive address register.
- **/
-s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
-{
- u32 rar_high;
- u32 rar_entries = hw->mac.num_rar_entries;
-
- /* Make sure we are using a valid rar index range */
- if (index >= rar_entries) {
- hw_dbg(hw, "RAR index %d is out of range.\n", index);
- return IXGBE_ERR_INVALID_ARGUMENT;
- }
-
- /*
- * Some parts put the VMDq setting in the extra RAH bits,
- * so save everything except the lower 16 bits that hold part
- * of the address and the address valid bit.
- */
- rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
- rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
-
- IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
- IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
-
- /* clear VMDq pool/queue selection for this RAR */
- hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
-
- return 0;
-}
-
-/**
- * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
- * @hw: pointer to hardware structure
- *
- * Places the MAC address in receive address register 0 and clears the rest
- * of the receive address registers. Clears the multicast table. Assumes
- * the receiver is in reset when the routine is called.
- **/
-s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
-{
- u32 i;
- u32 rar_entries = hw->mac.num_rar_entries;
-
- /*
- * If the current mac address is valid, assume it is a software override
- * to the permanent address.
- * Otherwise, use the permanent address from the eeprom.
- */
- if (ixgbe_validate_mac_addr(hw->mac.addr) ==
- IXGBE_ERR_INVALID_MAC_ADDR) {
- /* Get the MAC address from the RAR0 for later reference */
- hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
-
- hw_dbg(hw, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
- hw->mac.addr[0], hw->mac.addr[1],
- hw->mac.addr[2]);
- hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
- hw->mac.addr[4], hw->mac.addr[5]);
- } else {
- /* Setup the receive address. */
- hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
- hw_dbg(hw, " New MAC Addr =%.2X %.2X %.2X ",
- hw->mac.addr[0], hw->mac.addr[1],
- hw->mac.addr[2]);
- hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
- hw->mac.addr[4], hw->mac.addr[5]);
-
- hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
-
- /* clear VMDq pool/queue selection for RAR 0 */
- hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
- }
- hw->addr_ctrl.overflow_promisc = 0;
-
- hw->addr_ctrl.rar_used_count = 1;
-
- /* Zero out the other receive addresses. */
- hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
- for (i = 1; i < rar_entries; i++) {
- IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
- IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
- }
-
- /* Clear the MTA */
- hw->addr_ctrl.mta_in_use = 0;
- IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
-
- hw_dbg(hw, " Clearing MTA\n");
- for (i = 0; i < hw->mac.mcft_size; i++)
- IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
-
- ixgbe_init_uta_tables(hw);
-
- return 0;
-}
-
-/**
- * ixgbe_add_uc_addr - Adds a secondary unicast address.
- * @hw: pointer to hardware structure
- * @addr: new address
- *
- * Adds it to unused receive address register or goes into promiscuous mode.
- **/
-void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
-{
- u32 rar_entries = hw->mac.num_rar_entries;
- u32 rar;
-
- hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
- addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
-
- /*
- * Place this address in the RAR if there is room,
- * else put the controller into promiscuous mode
- */
- if (hw->addr_ctrl.rar_used_count < rar_entries) {
- rar = hw->addr_ctrl.rar_used_count;
- hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
- hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar);
- hw->addr_ctrl.rar_used_count++;
- } else {
- hw->addr_ctrl.overflow_promisc++;
- }
-
- hw_dbg(hw, "ixgbe_add_uc_addr Complete\n");
-}
-
-/**
- * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
- * @hw: pointer to hardware structure
- * @addr_list: the list of new addresses
- * @addr_count: number of addresses
- * @next: iterator function to walk the address list
- *
- * The given list replaces any existing list. Clears the secondary addrs from
- * receive address registers. Uses unused receive address registers for the
- * first secondary addresses, and falls back to promiscuous mode as needed.
- *
- * Drivers using secondary unicast addresses must set user_set_promisc when
- * manually putting the device into promiscuous mode.
- **/
-s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
- u32 addr_count, ixgbe_mc_addr_itr next)
-{
- u8 *addr;
- u32 i;
- u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
- u32 uc_addr_in_use;
- u32 fctrl;
- u32 vmdq;
-
- /*
- * Clear accounting of old secondary address list,
- * don't count RAR[0]
- */
- uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
- hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
- hw->addr_ctrl.overflow_promisc = 0;
-
- /* Zero out the other receive addresses */
- hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use+1);
- for (i = 0; i < uc_addr_in_use; i++) {
- IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
- IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
- }
-
- /* Add the new addresses */
- for (i = 0; i < addr_count; i++) {
- hw_dbg(hw, " Adding the secondary addresses:\n");
- addr = next(hw, &addr_list, &vmdq);
- ixgbe_add_uc_addr(hw, addr, vmdq);
- }
-
- if (hw->addr_ctrl.overflow_promisc) {
- /* enable promisc if not already in overflow or set by user */
- if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
- hw_dbg(hw, " Entering address overflow promisc mode\n");
- fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
- fctrl |= IXGBE_FCTRL_UPE;
- IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
- }
- } else {
- /* only disable if set by overflow, not by user */
- if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
- hw_dbg(hw, " Leaving address overflow promisc mode\n");
- fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
- fctrl &= ~IXGBE_FCTRL_UPE;
- IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
- }
- }
-
- hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n");
- return 0;
-}
-
-/**
- * ixgbe_mta_vector - Determines bit-vector in multicast table to set
- * @hw: pointer to hardware structure
- * @mc_addr: the multicast address
- *
- * Extracts the 12 bits, from a multicast address, to determine which
- * bit-vector to set in the multicast table. The hardware uses 12 bits, from
- * incoming rx multicast addresses, to determine the bit-vector to check in
- * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
- * by the MO field of the MCSTCTRL. The MO field is set during initialization
- * to mc_filter_type.
- **/
-static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
-{
- u32 vector = 0;
-
- switch (hw->mac.mc_filter_type) {
- case 0: /* use bits [47:36] of the address */
- vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
- break;
- case 1: /* use bits [46:35] of the address */
- vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
- break;
- case 2: /* use bits [45:34] of the address */
- vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
- break;
- case 3: /* use bits [43:32] of the address */
- vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
- break;
- default: /* Invalid mc_filter_type */
- hw_dbg(hw, "MC filter type param set incorrectly\n");
- break;
- }
-
- /* vector can only be 12-bits or boundary will be exceeded */
- vector &= 0xFFF;
- return vector;
-}
-
-/**
- * ixgbe_set_mta - Set bit-vector in multicast table
- * @hw: pointer to hardware structure
- * @hash_value: Multicast address hash value
- *
- * Sets the bit-vector in the multicast table.
- **/
-void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
-{
- u32 vector;
- u32 vector_bit;
- u32 vector_reg;
-
- hw->addr_ctrl.mta_in_use++;
-
- vector = ixgbe_mta_vector(hw, mc_addr);
- hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
-
- /*
- * The MTA is a register array of 128 32-bit registers. It is treated
- * like an array of 4096 bits. We want to set bit
- * BitArray[vector_value]. So we figure out what register the bit is
- * in, read it, OR in the new bit, then write back the new value. The
- * register is determined by the upper 7 bits of the vector value and
- * the bit within that register are determined by the lower 5 bits of
- * the value.
- */
- vector_reg = (vector >> 5) & 0x7F;
- vector_bit = vector & 0x1F;
- hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
-}
-
-/**
- * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
- * @hw: pointer to hardware structure
- * @mc_addr_list: the list of new multicast addresses
- * @mc_addr_count: number of addresses
- * @next: iterator function to walk the multicast address list
- * @clear: flag, when set clears the table beforehand
- *
- * When the clear flag is set, the given list replaces any existing list.
- * Hashes the given addresses into the multicast table.
- **/
-s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
- u32 mc_addr_count, ixgbe_mc_addr_itr next,
- bool clear)
-{
- u32 i;
- u32 vmdq;
-
- /*
- * Set the new number of MC addresses that we are being requested to
- * use.
- */
- hw->addr_ctrl.num_mc_addrs = mc_addr_count;
- hw->addr_ctrl.mta_in_use = 0;
-
- /* Clear mta_shadow */
- if (clear) {
- hw_dbg(hw, " Clearing MTA\n");
- memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
- }
-
- /* Update mta_shadow */
- for (i = 0; i < mc_addr_count; i++) {
- hw_dbg(hw, " Adding the multicast addresses:\n");
- ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
- }
-
- /* Enable mta */
- for (i = 0; i < hw->mac.mcft_size; i++)
- IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
- hw->mac.mta_shadow[i]);
-
- if (hw->addr_ctrl.mta_in_use > 0)
- IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
- IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
-
- hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
- return 0;
-}
-
-/**
- * ixgbe_enable_mc_generic - Enable multicast address in RAR
- * @hw: pointer to hardware structure
- *
- * Enables multicast address in RAR and the use of the multicast hash table.
- **/
-s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
-{
- struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
-
- if (a->mta_in_use > 0)
- IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
- hw->mac.mc_filter_type);
-
- return 0;
-}
-
-/**
- * ixgbe_disable_mc_generic - Disable multicast address in RAR
- * @hw: pointer to hardware structure
- *
- * Disables multicast address in RAR and the use of the multicast hash table.
- **/
-s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
-{
- struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
-
- if (a->mta_in_use > 0)
- IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
-
- return 0;
-}
-
-/**
- * ixgbe_fc_enable_generic - Enable flow control
- * @hw: pointer to hardware structure
- *
- * Enable flow control according to the current settings.
- **/
-s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
-{
- s32 ret_val = 0;
- u32 mflcn_reg, fccfg_reg;
- u32 reg;
- u32 fcrtl, fcrth;
- int i;
-
- /* Validate the water mark configuration */
- if (!hw->fc.pause_time) {
- ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
- goto out;
- }
-
- /* Low water mark of zero causes XOFF floods */
- for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
- if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
- hw->fc.high_water[i]) {
- if (!hw->fc.low_water[i] ||
- hw->fc.low_water[i] >= hw->fc.high_water[i]) {
- hw_dbg(hw, "Invalid water mark configuration\n");
- ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
- goto out;
- }
- }
- }
-
- /* Negotiate the fc mode to use */
- ixgbe_fc_autoneg(hw);
-
- /* Disable any previous flow control settings */
- mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
- mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
-
- fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
- fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
-
- /*
- * The possible values of fc.current_mode are:
- * 0: Flow control is completely disabled
- * 1: Rx flow control is enabled (we can receive pause frames,
- * but not send pause frames).
- * 2: Tx flow control is enabled (we can send pause frames but
- * we do not support receiving pause frames).
- * 3: Both Rx and Tx flow control (symmetric) are enabled.
- * other: Invalid.
- */
- switch (hw->fc.current_mode) {
- case ixgbe_fc_none:
- /*
- * Flow control is disabled by software override or autoneg.
- * The code below will actually disable it in the HW.
- */
- break;
- case ixgbe_fc_rx_pause:
- /*
- * Rx Flow control is enabled and Tx Flow control is
- * disabled by software override. Since there really
- * isn't a way to advertise that we are capable of RX
- * Pause ONLY, we will advertise that we support both
- * symmetric and asymmetric Rx PAUSE. Later, we will
- * disable the adapter's ability to send PAUSE frames.
- */
- mflcn_reg |= IXGBE_MFLCN_RFCE;
- break;
- case ixgbe_fc_tx_pause:
- /*
- * Tx Flow control is enabled, and Rx Flow control is
- * disabled by software override.
- */
- fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
- break;
- case ixgbe_fc_full:
- /* Flow control (both Rx and Tx) is enabled by SW override. */
- mflcn_reg |= IXGBE_MFLCN_RFCE;
- fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
- break;
- default:
- hw_dbg(hw, "Flow control param set incorrectly\n");
- ret_val = IXGBE_ERR_CONFIG;
- goto out;
- break;
- }
-
- /* Set 802.3x based flow control settings. */
- mflcn_reg |= IXGBE_MFLCN_DPF;
- IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
- IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
-
-
- /* Set up and enable Rx high/low water mark thresholds, enable XON. */
- for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
- if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
- hw->fc.high_water[i]) {
- fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
- IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
- fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
- } else {
- IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
- /*
- * In order to prevent Tx hangs when the internal Tx
- * switch is enabled we must set the high water mark
- * to the maximum FCRTH value. This allows the Tx
- * switch to function even under heavy Rx workloads.
- */
- fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
- }
-
- IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
- }
-
- /* Configure pause time (2 TCs per register) */
- reg = hw->fc.pause_time * 0x00010001;
- for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
- IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
-
- /* Configure flow control refresh threshold value */
- IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
-
-out:
- return ret_val;
-}
-
-/**
- * ixgbe_negotiate_fc - Negotiate flow control
- * @hw: pointer to hardware structure
- * @adv_reg: flow control advertised settings
- * @lp_reg: link partner's flow control settings
- * @adv_sym: symmetric pause bit in advertisement
- * @adv_asm: asymmetric pause bit in advertisement
- * @lp_sym: symmetric pause bit in link partner advertisement
- * @lp_asm: asymmetric pause bit in link partner advertisement
- *
- * Find the intersection between advertised settings and link partner's
- * advertised settings
- **/
-static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
- u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
-{
- if (!adv_reg || !lp_reg)
- return IXGBE_ERR_FC_NOT_NEGOTIATED;
-
- if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
- /*
- * Now we need to check if the user selected Rx ONLY
- * of pause frames. In this case, we had to advertise
- * FULL flow control because we could not advertise RX
- * ONLY. Hence, we must now check to see if we need to
- * turn OFF the TRANSMISSION of PAUSE frames.
- */
- if (hw->fc.requested_mode == ixgbe_fc_full) {
- hw->fc.current_mode = ixgbe_fc_full;
- hw_dbg(hw, "Flow Control = FULL.\n");
- } else {
- hw->fc.current_mode = ixgbe_fc_rx_pause;
- hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
- }
- } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
- (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
- hw->fc.current_mode = ixgbe_fc_tx_pause;
- hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
- } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
- !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
- hw->fc.current_mode = ixgbe_fc_rx_pause;
- hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
- } else {
- hw->fc.current_mode = ixgbe_fc_none;
- hw_dbg(hw, "Flow Control = NONE.\n");
- }
- return 0;
-}
-
-/**
- * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
- * @hw: pointer to hardware structure
- *
- * Enable flow control according on 1 gig fiber.
- **/
-static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
-{
- u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
- s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
-
- /*
- * On multispeed fiber at 1g, bail out if
- * - link is up but AN did not complete, or if
- * - link is up and AN completed but timed out
- */
-
- linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
- if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
- (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
- goto out;
-
- pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
- pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
-
- ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
- pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
- IXGBE_PCS1GANA_ASM_PAUSE,
- IXGBE_PCS1GANA_SYM_PAUSE,
- IXGBE_PCS1GANA_ASM_PAUSE);
-
-out:
- return ret_val;
-}
-
-/**
- * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
- * @hw: pointer to hardware structure
- *
- * Enable flow control according to IEEE clause 37.
- **/
-static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
-{
- u32 links2, anlp1_reg, autoc_reg, links;
- s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
-
- /*
- * On backplane, bail out if
- * - backplane autoneg was not completed, or if
- * - we are 82599 and link partner is not AN enabled
- */
- links = IXGBE_READ_REG(hw, IXGBE_LINKS);
- if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
- goto out;
-
- if (hw->mac.type == ixgbe_mac_82599EB) {
- links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
- if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
- goto out;
- }
- /*
- * Read the 10g AN autoc and LP ability registers and resolve
- * local flow control settings accordingly
- */
- autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
- anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
-
- ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
- anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
- IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
-
-out:
- return ret_val;
-}
-
-/**
- * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
- * @hw: pointer to hardware structure
- *
- * Enable flow control according to IEEE clause 37.
- **/
-static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
-{
- u16 technology_ability_reg = 0;
- u16 lp_technology_ability_reg = 0;
-
- hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- &technology_ability_reg);
- hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- &lp_technology_ability_reg);
-
- return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
- (u32)lp_technology_ability_reg,
- IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
- IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
-}
-
-/**
- * ixgbe_fc_autoneg - Configure flow control
- * @hw: pointer to hardware structure
- *
- * Compares our advertised flow control capabilities to those advertised by
- * our link partner, and determines the proper flow control mode to use.
- **/
-void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
-{
- s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
- ixgbe_link_speed speed;
- bool link_up;
-
- /*
- * AN should have completed when the cable was plugged in.
- * Look for reasons to bail out. Bail out if:
- * - FC autoneg is disabled, or if
- * - link is not up.
- */
- if (hw->fc.disable_fc_autoneg)
- goto out;
-
- hw->mac.ops.check_link(hw, &speed, &link_up, false);
- if (!link_up)
- goto out;
-
- switch (hw->phy.media_type) {
- /* Autoneg flow control on fiber adapters */
- case ixgbe_media_type_fiber:
- if (speed == IXGBE_LINK_SPEED_1GB_FULL)
- ret_val = ixgbe_fc_autoneg_fiber(hw);
- break;
-
- /* Autoneg flow control on backplane adapters */
- case ixgbe_media_type_backplane:
- ret_val = ixgbe_fc_autoneg_backplane(hw);
- break;
-
- /* Autoneg flow control on copper adapters */
- case ixgbe_media_type_copper:
- if (ixgbe_device_supports_autoneg_fc(hw) == 0)
- ret_val = ixgbe_fc_autoneg_copper(hw);
- break;
-
- default:
- break;
- }
-
-out:
- if (ret_val == 0) {
- hw->fc.fc_was_autonegged = true;
- } else {
- hw->fc.fc_was_autonegged = false;
- hw->fc.current_mode = hw->fc.requested_mode;
- }
-}
-
-/**
- * ixgbe_disable_pcie_master - Disable PCI-express master access
- * @hw: pointer to hardware structure
- *
- * Disables PCI-Express master access and verifies there are no pending
- * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
- * bit hasn't caused the master requests to be disabled, else 0
- * is returned signifying master requests disabled.
- **/
-s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
-{
- s32 status = 0;
- u32 i;
-
- /* Always set this bit to ensure any future transactions are blocked */
- IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
-
- /* Exit if master requets are blocked */
- if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
- goto out;
-
- /* Poll for master request bit to clear */
- for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
- udelay(100);
- if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
- goto out;
- }
-
- /*
- * Two consecutive resets are required via CTRL.RST per datasheet
- * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
- * of this need. The first reset prevents new master requests from
- * being issued by our device. We then must wait 1usec or more for any
- * remaining completions from the PCIe bus to trickle in, and then reset
- * again to clear out any effects they may have had on our device.
- */
- hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
- hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
-
- /*
- * Before proceeding, make sure that the PCIe block does not have
- * transactions pending.
- */
- for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
- udelay(100);
- if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) &
- IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
- goto out;
- }
-
- hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
- status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
-
-out:
- return status;
-}
-
-/**
- * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
- * @hw: pointer to hardware structure
- * @mask: Mask to specify which semaphore to acquire
- *
- * Acquires the SWFW semaphore through the GSSR register for the specified
- * function (CSR, PHY0, PHY1, EEPROM, Flash)
- **/
-s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
-{
- u32 gssr;
- u32 swmask = mask;
- u32 fwmask = mask << 5;
- s32 timeout = 200;
-
- while (timeout) {
- /*
- * SW EEPROM semaphore bit is used for access to all
- * SW_FW_SYNC/GSSR bits (not just EEPROM)
- */
- if (ixgbe_get_eeprom_semaphore(hw))
- return IXGBE_ERR_SWFW_SYNC;
-
- gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
- if (!(gssr & (fwmask | swmask)))
- break;
-
- /*
- * Firmware currently using resource (fwmask) or other software
- * thread currently using resource (swmask)
- */
- ixgbe_release_eeprom_semaphore(hw);
- msleep(5);
- timeout--;
- }
-
- if (!timeout) {
- hw_dbg(hw, "Driver can't access resource, SW_FW_SYNC timeout.\n");
- return IXGBE_ERR_SWFW_SYNC;
- }
-
- gssr |= swmask;
- IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
-
- ixgbe_release_eeprom_semaphore(hw);
- return 0;
-}
-
-/**
- * ixgbe_release_swfw_sync - Release SWFW semaphore
- * @hw: pointer to hardware structure
- * @mask: Mask to specify which semaphore to release
- *
- * Releases the SWFW semaphore through the GSSR register for the specified
- * function (CSR, PHY0, PHY1, EEPROM, Flash)
- **/
-void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
-{
- u32 gssr;
- u32 swmask = mask;
-
- ixgbe_get_eeprom_semaphore(hw);
-
- gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
- gssr &= ~swmask;
- IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
-
- ixgbe_release_eeprom_semaphore(hw);
-}
-
-/**
- * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
- * @hw: pointer to hardware structure
- *
- * Stops the receive data path and waits for the HW to internally empty
- * the Rx security block
- **/
-s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
-{
-#define IXGBE_MAX_SECRX_POLL 40
-
- int i;
- int secrxreg;
-
- secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
- secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
- IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
- for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
- secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
- if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
- break;
- else
- /* Use interrupt-safe sleep just in case */
- udelay(1000);
- }
-
- /* For informational purposes only */
- if (i >= IXGBE_MAX_SECRX_POLL)
- hw_dbg(hw, "Rx unit being enabled before security "
- "path fully disabled. Continuing with init.\n");
-
- return 0;
-}
-
-/**
- * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
- * @hw: pointer to hardware structure
- *
- * Enables the receive data path.
- **/
-s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
-{
- int secrxreg;
-
- secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
- secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
- IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
- IXGBE_WRITE_FLUSH(hw);
-
- return 0;
-}
-
-/**
- * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
- * @hw: pointer to hardware structure
- * @regval: register value to write to RXCTRL
- *
- * Enables the Rx DMA unit
- **/
-s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
-{
- IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
-
- return 0;
-}
-
-/**
- * ixgbe_blink_led_start_generic - Blink LED based on index.
- * @hw: pointer to hardware structure
- * @index: led number to blink
- **/
-s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
-{
- ixgbe_link_speed speed = 0;
- bool link_up = 0;
- u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
- u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
-
- /*
- * Link must be up to auto-blink the LEDs;
- * Force it if link is down.
- */
- hw->mac.ops.check_link(hw, &speed, &link_up, false);
-
- if (!link_up) {
- autoc_reg |= IXGBE_AUTOC_AN_RESTART;
- autoc_reg |= IXGBE_AUTOC_FLU;
- IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
- IXGBE_WRITE_FLUSH(hw);
- msleep(10);
- }
-
- led_reg &= ~IXGBE_LED_MODE_MASK(index);
- led_reg |= IXGBE_LED_BLINK(index);
- IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
- IXGBE_WRITE_FLUSH(hw);
-
- return 0;
-}
-
-/**
- * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
- * @hw: pointer to hardware structure
- * @index: led number to stop blinking
- **/
-s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
-{
- u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
- u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
-
- autoc_reg &= ~IXGBE_AUTOC_FLU;
- autoc_reg |= IXGBE_AUTOC_AN_RESTART;
- IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
-
- led_reg &= ~IXGBE_LED_MODE_MASK(index);
- led_reg &= ~IXGBE_LED_BLINK(index);
- led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
- IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
- IXGBE_WRITE_FLUSH(hw);
-
- return 0;
-}
-
-/**
- * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
- * @hw: pointer to hardware structure
- * @san_mac_offset: SAN MAC address offset
- *
- * This function will read the EEPROM location for the SAN MAC address
- * pointer, and returns the value at that location. This is used in both
- * get and set mac_addr routines.
- **/
-static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
- u16 *san_mac_offset)
-{
- /*
- * First read the EEPROM pointer to see if the MAC addresses are
- * available.
- */
- hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
-
- return 0;
-}
-
-/**
- * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
- * @hw: pointer to hardware structure
- * @san_mac_addr: SAN MAC address
- *
- * Reads the SAN MAC address from the EEPROM, if it's available. This is
- * per-port, so set_lan_id() must be called before reading the addresses.
- * set_lan_id() is called by identify_sfp(), but this cannot be relied
- * upon for non-SFP connections, so we must call it here.
- **/
-s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
-{
- u16 san_mac_data, san_mac_offset;
- u8 i;
-
- /*
- * First read the EEPROM pointer to see if the MAC addresses are
- * available. If they're not, no point in calling set_lan_id() here.
- */
- ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
-
- if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
- /*
- * No addresses available in this EEPROM. It's not an
- * error though, so just wipe the local address and return.
- */
- for (i = 0; i < 6; i++)
- san_mac_addr[i] = 0xFF;
-
- goto san_mac_addr_out;
- }
-
- /* make sure we know which port we need to program */
- hw->mac.ops.set_lan_id(hw);
- /* apply the port offset to the address offset */
- (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
- (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
- for (i = 0; i < 3; i++) {
- hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
- san_mac_addr[i * 2] = (u8)(san_mac_data);
- san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
- san_mac_offset++;
- }
-
-san_mac_addr_out:
- return 0;
-}
-
-/**
- * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
- * @hw: pointer to hardware structure
- * @san_mac_addr: SAN MAC address
- *
- * Write a SAN MAC address to the EEPROM.
- **/
-s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
-{
- s32 status = 0;
- u16 san_mac_data, san_mac_offset;
- u8 i;
-
- /* Look for SAN mac address pointer. If not defined, return */
- ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
-
- if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
- status = IXGBE_ERR_NO_SAN_ADDR_PTR;
- goto san_mac_addr_out;
- }
-
- /* Make sure we know which port we need to write */
- hw->mac.ops.set_lan_id(hw);
- /* Apply the port offset to the address offset */
- (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
- (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
-
- for (i = 0; i < 3; i++) {
- san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
- san_mac_data |= (u16)(san_mac_addr[i * 2]);
- hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
- san_mac_offset++;
- }
-
-san_mac_addr_out:
- return status;
-}
-
-/**
- * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
- * @hw: pointer to hardware structure
- *
- * Read PCIe configuration space, and get the MSI-X vector count from
- * the capabilities table.
- **/
-u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
-{
- u16 msix_count = 1;
- u16 max_msix_count;
- u16 pcie_offset;
-
- switch (hw->mac.type) {
- case ixgbe_mac_82598EB:
- pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
- max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
- break;
- case ixgbe_mac_82599EB:
- case ixgbe_mac_X540:
- pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
- max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
- break;
- default:
- return msix_count;
- }
-
- msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
- msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
-
- /* MSI-X count is zero-based in HW */
- msix_count++;
-
- if (msix_count > max_msix_count)
- msix_count = max_msix_count;
-
- return msix_count;
-}
-
-/**
- * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
- * @hw: pointer to hardware structure
- * @addr: Address to put into receive address register
- * @vmdq: VMDq pool to assign
- *
- * Puts an ethernet address into a receive address register, or
- * finds the rar that it is already in; adds to the pool list
- **/
-s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
-{
- static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
- u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
- u32 rar;
- u32 rar_low, rar_high;
- u32 addr_low, addr_high;
-
- /* swap bytes for HW little endian */
- addr_low = addr[0] | (addr[1] << 8)
- | (addr[2] << 16)
- | (addr[3] << 24);
- addr_high = addr[4] | (addr[5] << 8);
-
- /*
- * Either find the mac_id in rar or find the first empty space.
- * rar_highwater points to just after the highest currently used
- * rar in order to shorten the search. It grows when we add a new
- * rar to the top.
- */
- for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
- rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
-
- if (((IXGBE_RAH_AV & rar_high) == 0)
- && first_empty_rar == NO_EMPTY_RAR_FOUND) {
- first_empty_rar = rar;
- } else if ((rar_high & 0xFFFF) == addr_high) {
- rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
- if (rar_low == addr_low)
- break; /* found it already in the rars */
- }
- }
-
- if (rar < hw->mac.rar_highwater) {
- /* already there so just add to the pool bits */
- ixgbe_set_vmdq(hw, rar, vmdq);
- } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
- /* stick it into first empty RAR slot we found */
- rar = first_empty_rar;
- ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
- } else if (rar == hw->mac.rar_highwater) {
- /* add it to the top of the list and inc the highwater mark */
- ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
- hw->mac.rar_highwater++;
- } else if (rar >= hw->mac.num_rar_entries) {
- return IXGBE_ERR_INVALID_MAC_ADDR;
- }
-
- /*
- * If we found rar[0], make sure the default pool bit (we use pool 0)
- * remains cleared to be sure default pool packets will get delivered
- */
- if (rar == 0)
- ixgbe_clear_vmdq(hw, rar, 0);
-
- return rar;
-}
-
-/**
- * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
- * @hw: pointer to hardware struct
- * @rar: receive address register index to disassociate
- * @vmdq: VMDq pool index to remove from the rar
- **/
-s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
-{
- u32 mpsar_lo, mpsar_hi;
- u32 rar_entries = hw->mac.num_rar_entries;
-
- /* Make sure we are using a valid rar index range */
- if (rar >= rar_entries) {
- hw_dbg(hw, "RAR index %d is out of range.\n", rar);
- return IXGBE_ERR_INVALID_ARGUMENT;
- }
-
- mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
- mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
-
- if (!mpsar_lo && !mpsar_hi)
- goto done;
-
- if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
- if (mpsar_lo) {
- IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
- mpsar_lo = 0;
- }
- if (mpsar_hi) {
- IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
- mpsar_hi = 0;
- }
- } else if (vmdq < 32) {
- mpsar_lo &= ~(1 << vmdq);
- IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
- } else {
- mpsar_hi &= ~(1 << (vmdq - 32));
- IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
- }
-
- /* was that the last pool using this rar? */
- if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
- hw->mac.ops.clear_rar(hw, rar);
-done:
- return 0;
-}
-
-/**
- * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
- * @hw: pointer to hardware struct
- * @rar: receive address register index to associate with a VMDq index
- * @vmdq: VMDq pool index
- **/
-s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
-{
- u32 mpsar;
- u32 rar_entries = hw->mac.num_rar_entries;
-
- /* Make sure we are using a valid rar index range */
- if (rar >= rar_entries) {
- hw_dbg(hw, "RAR index %d is out of range.\n", rar);
- return IXGBE_ERR_INVALID_ARGUMENT;
- }
-
- if (vmdq < 32) {
- mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
- mpsar |= 1 << vmdq;
- IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
- } else {
- mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
- mpsar |= 1 << (vmdq - 32);
- IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
- }
- return 0;
-}
-
-/**
- * This function should only be involved in the IOV mode.
- * In IOV mode, Default pool is next pool after the number of
- * VFs advertized and not 0.
- * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
- *
- * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
- * @hw: pointer to hardware struct
- * @vmdq: VMDq pool index
- **/
-s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
-{
- u32 mpsar;
- u32 rar = hw->mac.san_mac_rar_index;
-
- if (vmdq < 32) {
- mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
- mpsar |= 1 << vmdq;
- IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
- } else {
- mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
- mpsar |= 1 << (vmdq - 32);
- IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
- }
-
- return 0;
-}
-
-/**
- * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
- * @hw: pointer to hardware structure
- **/
-s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
-{
- int i;
-
- hw_dbg(hw, " Clearing UTA\n");
-
- for (i = 0; i < 128; i++)
- IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
-
- return 0;
-}
-
-/**
- * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
- * @hw: pointer to hardware structure
- * @vlan: VLAN id to write to VLAN filter
- *
- * return the VLVF index where this VLAN id should be placed
- *
- **/
-s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
-{
- u32 bits = 0;
- u32 first_empty_slot = 0;
- s32 regindex;
-
- /* short cut the special case */
- if (vlan == 0)
- return 0;
-
- /*
- * Search for the vlan id in the VLVF entries. Save off the first empty
- * slot found along the way
- */
- for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
- bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
- if (!bits && !(first_empty_slot))
- first_empty_slot = regindex;
- else if ((bits & 0x0FFF) == vlan)
- break;
- }
-
- /*
- * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
- * in the VLVF. Else use the first empty VLVF register for this
- * vlan id.
- */
- if (regindex >= IXGBE_VLVF_ENTRIES) {
- if (first_empty_slot)
- regindex = first_empty_slot;
- else {
- hw_dbg(hw, "No space in VLVF.\n");
- regindex = IXGBE_ERR_NO_SPACE;
- }
- }
-
- return regindex;
-}
-
-/**
- * ixgbe_set_vfta_generic - Set VLAN filter table
- * @hw: pointer to hardware structure
- * @vlan: VLAN id to write to VLAN filter
- * @vind: VMDq output index that maps queue to VLAN id in VFVFB
- * @vlan_on: boolean flag to turn on/off VLAN in VFVF
- *
- * Turn on/off specified VLAN in the VLAN filter table.
- **/
-s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
- bool vlan_on)
-{
- s32 regindex;
- u32 bitindex;
- u32 vfta;
- u32 targetbit;
- s32 ret_val = 0;
- bool vfta_changed = false;
-
- if (vlan > 4095)
- return IXGBE_ERR_PARAM;
-
- /*
- * this is a 2 part operation - first the VFTA, then the
- * VLVF and VLVFB if VT Mode is set
- * We don't write the VFTA until we know the VLVF part succeeded.
- */
-
- /* Part 1
- * The VFTA is a bitstring made up of 128 32-bit registers
- * that enable the particular VLAN id, much like the MTA:
- * bits[11-5]: which register
- * bits[4-0]: which bit in the register
- */
- regindex = (vlan >> 5) & 0x7F;
- bitindex = vlan & 0x1F;
- targetbit = (1 << bitindex);
- vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
-
- if (vlan_on) {
- if (!(vfta & targetbit)) {
- vfta |= targetbit;
- vfta_changed = true;
- }
- } else {
- if (vfta & targetbit) {
- vfta &= ~targetbit;
- vfta_changed = true;
- }
- }
-
- /* Part 2
- * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
- */
- ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
- &vfta_changed);
- if (ret_val != 0)
- return ret_val;
-
- if (vfta_changed)
- IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
-
- return 0;
-}
-
-/**
- * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
- * @hw: pointer to hardware structure
- * @vlan: VLAN id to write to VLAN filter
- * @vind: VMDq output index that maps queue to VLAN id in VFVFB
- * @vlan_on: boolean flag to turn on/off VLAN in VFVF
- * @vfta_changed: pointer to boolean flag which indicates whether VFTA
- * should be changed
- *
- * Turn on/off specified bit in VLVF table.
- **/
-s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
- bool vlan_on, bool *vfta_changed)
-{
- u32 vt;
-
- if (vlan > 4095)
- return IXGBE_ERR_PARAM;
-
- /* If VT Mode is set
- * Either vlan_on
- * make sure the vlan is in VLVF
- * set the vind bit in the matching VLVFB
- * Or !vlan_on
- * clear the pool bit and possibly the vind
- */
- vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
- if (vt & IXGBE_VT_CTL_VT_ENABLE) {
- s32 vlvf_index;
- u32 bits;
-
- vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
- if (vlvf_index < 0)
- return vlvf_index;
-
- if (vlan_on) {
- /* set the pool bit */
- if (vind < 32) {
- bits = IXGBE_READ_REG(hw,
- IXGBE_VLVFB(vlvf_index * 2));
- bits |= (1 << vind);
- IXGBE_WRITE_REG(hw,
- IXGBE_VLVFB(vlvf_index * 2),
- bits);
- } else {
- bits = IXGBE_READ_REG(hw,
- IXGBE_VLVFB((vlvf_index * 2) + 1));
- bits |= (1 << (vind - 32));
- IXGBE_WRITE_REG(hw,
- IXGBE_VLVFB((vlvf_index * 2) + 1),
- bits);
- }
- } else {
- /* clear the pool bit */
- if (vind < 32) {
- bits = IXGBE_READ_REG(hw,
- IXGBE_VLVFB(vlvf_index * 2));
- bits &= ~(1 << vind);
- IXGBE_WRITE_REG(hw,
- IXGBE_VLVFB(vlvf_index * 2),
- bits);
- bits |= IXGBE_READ_REG(hw,
- IXGBE_VLVFB((vlvf_index * 2) + 1));
- } else {
- bits = IXGBE_READ_REG(hw,
- IXGBE_VLVFB((vlvf_index * 2) + 1));
- bits &= ~(1 << (vind - 32));
- IXGBE_WRITE_REG(hw,
- IXGBE_VLVFB((vlvf_index * 2) + 1),
- bits);
- bits |= IXGBE_READ_REG(hw,
- IXGBE_VLVFB(vlvf_index * 2));
- }
- }
-
- /*
- * If there are still bits set in the VLVFB registers
- * for the VLAN ID indicated we need to see if the
- * caller is requesting that we clear the VFTA entry bit.
- * If the caller has requested that we clear the VFTA
- * entry bit but there are still pools/VFs using this VLAN
- * ID entry then ignore the request. We're not worried
- * about the case where we're turning the VFTA VLAN ID
- * entry bit on, only when requested to turn it off as
- * there may be multiple pools and/or VFs using the
- * VLAN ID entry. In that case we cannot clear the
- * VFTA bit until all pools/VFs using that VLAN ID have also
- * been cleared. This will be indicated by "bits" being
- * zero.
- */
- if (bits) {
- IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
- (IXGBE_VLVF_VIEN | vlan));
- if (!vlan_on && (vfta_changed != NULL)) {
- /* someone wants to clear the vfta entry
- * but some pools/VFs are still using it.
- * Ignore it. */
- *vfta_changed = false;
- }
- } else
- IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
- }
-
- return 0;
-}
-
-/**
- * ixgbe_clear_vfta_generic - Clear VLAN filter table
- * @hw: pointer to hardware structure
- *
- * Clears the VLAN filer table, and the VMDq index associated with the filter
- **/
-s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
-{
- u32 offset;
-
- for (offset = 0; offset < hw->mac.vft_size; offset++)
- IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
-
- for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
- IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
- IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
- IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
- }
-
- return 0;
-}
-
-/**
- * ixgbe_check_mac_link_generic - Determine link and speed status
- * @hw: pointer to hardware structure
- * @speed: pointer to link speed
- * @link_up: true when link is up
- * @link_up_wait_to_complete: bool used to wait for link up or not
- *
- * Reads the links register to determine if link is up and the current speed
- **/
-s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
- bool *link_up, bool link_up_wait_to_complete)
-{
- u32 links_reg, links_orig;
- u32 i;
-
- /* clear the old state */
- links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
-
- links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
-
- if (links_orig != links_reg) {
- hw_dbg(hw, "LINKS changed from %08X to %08X\n",
- links_orig, links_reg);
- }
-
- if (link_up_wait_to_complete) {
- for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
- if (links_reg & IXGBE_LINKS_UP) {
- *link_up = true;
- break;
- } else {
- *link_up = false;
- }
- msleep(100);
- links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
- }
- } else {
- if (links_reg & IXGBE_LINKS_UP)
- *link_up = true;
- else
- *link_up = false;
- }
-
- if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
- IXGBE_LINKS_SPEED_10G_82599)
- *speed = IXGBE_LINK_SPEED_10GB_FULL;
- else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
- IXGBE_LINKS_SPEED_1G_82599)
- *speed = IXGBE_LINK_SPEED_1GB_FULL;
- else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
- IXGBE_LINKS_SPEED_100_82599)
- *speed = IXGBE_LINK_SPEED_100_FULL;
- else
- *speed = IXGBE_LINK_SPEED_UNKNOWN;
-
- return 0;
-}
-
-/**
- * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
- * the EEPROM
- * @hw: pointer to hardware structure
- * @wwnn_prefix: the alternative WWNN prefix
- * @wwpn_prefix: the alternative WWPN prefix
- *
- * This function will read the EEPROM from the alternative SAN MAC address
- * block to check the support for the alternative WWNN/WWPN prefix support.
- **/
-s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
- u16 *wwpn_prefix)
-{
- u16 offset, caps;
- u16 alt_san_mac_blk_offset;
-
- /* clear output first */
- *wwnn_prefix = 0xFFFF;
- *wwpn_prefix = 0xFFFF;
-
- /* check if alternative SAN MAC is supported */
- hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
- &alt_san_mac_blk_offset);
-
- if ((alt_san_mac_blk_offset == 0) ||
- (alt_san_mac_blk_offset == 0xFFFF))
- goto wwn_prefix_out;
-
- /* check capability in alternative san mac address block */
- offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
- hw->eeprom.ops.read(hw, offset, &caps);
- if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
- goto wwn_prefix_out;
-
- /* get the corresponding prefix for WWNN/WWPN */
- offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
- hw->eeprom.ops.read(hw, offset, wwnn_prefix);
-
- offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
- hw->eeprom.ops.read(hw, offset, wwpn_prefix);
-
-wwn_prefix_out:
- return 0;
-}
-
-/**
- * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
- * @hw: pointer to hardware structure
- * @bs: the fcoe boot status
- *
- * This function will read the FCOE boot status from the iSCSI FCOE block
- **/
-s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
-{
- u16 offset, caps, flags;
- s32 status;
-
- /* clear output first */
- *bs = ixgbe_fcoe_bootstatus_unavailable;
-
- /* check if FCOE IBA block is present */
- offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
- status = hw->eeprom.ops.read(hw, offset, &caps);
- if (status != 0)
- goto out;
-
- if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
- goto out;
-
- /* check if iSCSI FCOE block is populated */
- status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
- if (status != 0)
- goto out;
-
- if ((offset == 0) || (offset == 0xFFFF))
- goto out;
-
- /* read fcoe flags in iSCSI FCOE block */
- offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
- status = hw->eeprom.ops.read(hw, offset, &flags);
- if (status != 0)
- goto out;
-
- if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
- *bs = ixgbe_fcoe_bootstatus_enabled;
- else
- *bs = ixgbe_fcoe_bootstatus_disabled;
-
-out:
- return status;
-}
-
-/**
- * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
- * @hw: pointer to hardware structure
- * @enable: enable or disable switch for anti-spoofing
- * @pf: Physical Function pool - do not enable anti-spoofing for the PF
- *
- **/
-void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
-{
- int j;
- int pf_target_reg = pf >> 3;
- int pf_target_shift = pf % 8;
- u32 pfvfspoof = 0;
-
- if (hw->mac.type == ixgbe_mac_82598EB)
- return;
-
- if (enable)
- pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
-
- /*
- * PFVFSPOOF register array is size 8 with 8 bits assigned to
- * MAC anti-spoof enables in each register array element.
- */
- for (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
- IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
-
- /* If not enabling anti-spoofing then done */
- if (!enable)
- return;
-
- /*
- * The PF should be allowed to spoof so that it can support
- * emulation mode NICs. Reset the bit assigned to the PF
- */
- pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg));
- pfvfspoof ^= (1 << pf_target_shift);
- IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof);
-}
-
-/**
- * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
- * @hw: pointer to hardware structure
- * @enable: enable or disable switch for VLAN anti-spoofing
- * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
- *
- **/
-void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
-{
- int vf_target_reg = vf >> 3;
- int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
- u32 pfvfspoof;
-
- if (hw->mac.type == ixgbe_mac_82598EB)
- return;
-
- pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
- if (enable)
- pfvfspoof |= (1 << vf_target_shift);
- else
- pfvfspoof &= ~(1 << vf_target_shift);
- IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
-}
-
-/**
- * ixgbe_get_device_caps_generic - Get additional device capabilities
- * @hw: pointer to hardware structure
- * @device_caps: the EEPROM word with the extra device capabilities
- *
- * This function will read the EEPROM location for the device capabilities,
- * and return the word through device_caps.
- **/
-s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
-{
- hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
-
- return 0;
-}
-
-/**
- * ixgbe_calculate_checksum - Calculate checksum for buffer
- * @buffer: pointer to EEPROM
- * @length: size of EEPROM to calculate a checksum for
- * Calculates the checksum for some buffer on a specified length. The
- * checksum calculated is returned.
- **/
-static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
-{
- u32 i;
- u8 sum = 0;
-
- if (!buffer)
- return 0;
- for (i = 0; i < length; i++)
- sum += buffer[i];
-
- return (u8) (0 - sum);
-}
-
-/**
- * ixgbe_host_interface_command - Issue command to manageability block
- * @hw: pointer to the HW structure
- * @buffer: contains the command to write and where the return status will
- * be placed
- * @length: length of buffer, must be multiple of 4 bytes
- *
- * Communicates with the manageability block. On success return 0
- * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
- **/
-static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
- u32 length)
-{
- u32 hicr, i, bi;
- u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
- u8 buf_len, dword_len;
-
- s32 ret_val = 0;
-
- if (length == 0 || length & 0x3 ||
- length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
- hw_dbg(hw, "Buffer length failure.\n");
- ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
- goto out;
- }
-
- /* Check that the host interface is enabled. */
- hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
- if ((hicr & IXGBE_HICR_EN) == 0) {
- hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
- ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
- goto out;
- }
-
- /* Calculate length in DWORDs */
- dword_len = length >> 2;
-
- /*
- * The device driver writes the relevant command block
- * into the ram area.
- */
- for (i = 0; i < dword_len; i++)
- IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
- i, IXGBE_CPU_TO_LE32(buffer[i]));
-
- /* Setting this bit tells the ARC that a new command is pending. */
- IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
-
- for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
- hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
- if (!(hicr & IXGBE_HICR_C))
- break;
- msleep(1);
- }
-
- /* Check command successful completion. */
- if (i == IXGBE_HI_COMMAND_TIMEOUT ||
- (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
- hw_dbg(hw, "Command has failed with no status valid.\n");
- ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
- goto out;
- }
-
- /* Calculate length in DWORDs */
- dword_len = hdr_size >> 2;
-
- /* first pull in the header so we know the buffer length */
- for (bi = 0; bi < dword_len; bi++) {
- buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
- IXGBE_LE32_TO_CPUS(&buffer[bi]);
- }
-
- /* If there is any thing in data position pull it in */
- buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
- if (buf_len == 0)
- goto out;
-
- if (length < (buf_len + hdr_size)) {
- hw_dbg(hw, "Buffer not large enough for reply message.\n");
- ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
- goto out;
- }
-
- /* Calculate length in DWORDs, add 3 for odd lengths */
- dword_len = (buf_len + 3) >> 2;
-
- /* Pull in the rest of the buffer (bi is where we left off)*/
- for (; bi <= dword_len; bi++) {
- buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
- IXGBE_LE32_TO_CPUS(&buffer[bi]);
- }
-
-out:
- return ret_val;
-}
-
-/**
- * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
- * @hw: pointer to the HW structure
- * @maj: driver version major number
- * @min: driver version minor number
- * @build: driver version build number
- * @sub: driver version sub build number
- *
- * Sends driver version number to firmware through the manageability
- * block. On success return 0
- * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
- * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
- **/
-s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
- u8 build, u8 sub)
-{
- struct ixgbe_hic_drv_info fw_cmd;
- int i;
- s32 ret_val = 0;
-
- if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
- != 0) {
- ret_val = IXGBE_ERR_SWFW_SYNC;
- goto out;
- }
-
- fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
- fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
- fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
- fw_cmd.port_num = (u8)hw->bus.func;
- fw_cmd.ver_maj = maj;
- fw_cmd.ver_min = min;
- fw_cmd.ver_build = build;
- fw_cmd.ver_sub = sub;
- fw_cmd.hdr.checksum = 0;
- fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
- (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
- fw_cmd.pad = 0;
- fw_cmd.pad2 = 0;
-
- for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
- ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
- sizeof(fw_cmd));
- if (ret_val != 0)
- continue;
-
- if (fw_cmd.hdr.cmd_or_resp.ret_status ==
- FW_CEM_RESP_STATUS_SUCCESS)
- ret_val = 0;
- else
- ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
-
- break;
- }
-
- hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
-out:
- return ret_val;
-}
-
-/**
- * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
- * @hw: pointer to hardware structure
- * @num_pb: number of packet buffers to allocate
- * @headroom: reserve n KB of headroom
- * @strategy: packet buffer allocation strategy
- **/
-void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
- int strategy)
-{
- u32 pbsize = hw->mac.rx_pb_size;
- int i = 0;
- u32 rxpktsize, txpktsize, txpbthresh;
-
- /* Reserve headroom */
- pbsize -= headroom;
-
- if (!num_pb)
- num_pb = 1;
-
- /* Divide remaining packet buffer space amongst the number of packet
- * buffers requested using supplied strategy.
- */
- switch (strategy) {
- case PBA_STRATEGY_WEIGHTED:
- /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
- * buffer with 5/8 of the packet buffer space.
- */
- rxpktsize = (pbsize * 5) / (num_pb * 4);
- pbsize -= rxpktsize * (num_pb / 2);
- rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
- for (; i < (num_pb / 2); i++)
- IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
- /* Fall through to configure remaining packet buffers */
- case PBA_STRATEGY_EQUAL:
- rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
- for (; i < num_pb; i++)
- IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
- break;
- default:
- break;
- }
-
- /* Only support an equally distributed Tx packet buffer strategy. */
- txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
- txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
- for (i = 0; i < num_pb; i++) {
- IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
- IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
- }
-
- /* Clear unused TCs, if any, to zero buffer size*/
- for (; i < IXGBE_MAX_PB; i++) {
- IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
- IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
- IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
- }
-}
-
-/**
- * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
- * @hw: pointer to the hardware structure
- *
- * The 82599 and x540 MACs can experience issues if TX work is still pending
- * when a reset occurs. This function prevents this by flushing the PCIe
- * buffers on the system.
- **/
-void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
-{
- u32 gcr_ext, hlreg0;
-
- /*
- * If double reset is not requested then all transactions should
- * already be clear and as such there is no work to do
- */
- if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
- return;
-
- /*
- * Set loopback enable to prevent any transmits from being sent
- * should the link come up. This assumes that the RXCTRL.RXEN bit
- * has already been cleared.
- */
- hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
- IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
-
- /* initiate cleaning flow for buffers in the PCIe transaction layer */
- gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
- IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
- gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
-
- /* Flush all writes and allow 20usec for all transactions to clear */
- IXGBE_WRITE_FLUSH(hw);
- udelay(20);
-
- /* restore previous register values */
- IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
- IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
-}
-
-static const u8 ixgbe_emc_temp_data[4] = {
- IXGBE_EMC_INTERNAL_DATA,
- IXGBE_EMC_DIODE1_DATA,
- IXGBE_EMC_DIODE2_DATA,
- IXGBE_EMC_DIODE3_DATA
-};
-static const u8 ixgbe_emc_therm_limit[4] = {
- IXGBE_EMC_INTERNAL_THERM_LIMIT,
- IXGBE_EMC_DIODE1_THERM_LIMIT,
- IXGBE_EMC_DIODE2_THERM_LIMIT,
- IXGBE_EMC_DIODE3_THERM_LIMIT
-};
-
-/**
- * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
- * @hw: pointer to hardware structure
- * @data: pointer to the thermal sensor data structure
- *
- * Returns the thermal sensor data structure
- **/
-s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
-{
- s32 status = 0;
- u16 ets_offset;
- u16 ets_cfg;
- u16 ets_sensor;
- u8 num_sensors;
- u8 sensor_index;
- u8 sensor_location;
- u8 i;
- struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
-
- /* Only support thermal sensors attached to 82599 physical port 0 */
- if ((hw->mac.type != ixgbe_mac_82599EB) ||
- (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
- status = IXGBE_NOT_IMPLEMENTED;
- goto out;
- }
-
- status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
- if (status)
- goto out;
-
- if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {
- status = IXGBE_NOT_IMPLEMENTED;
- goto out;
- }
-
- status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
- if (status)
- goto out;
-
- if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
- != IXGBE_ETS_TYPE_EMC) {
- status = IXGBE_NOT_IMPLEMENTED;
- goto out;
- }
-
- num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
- if (num_sensors > IXGBE_MAX_SENSORS)
- num_sensors = IXGBE_MAX_SENSORS;
-
- for (i = 0; i < num_sensors; i++) {
- status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
- &ets_sensor);
- if (status)
- goto out;
-
- sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
- IXGBE_ETS_DATA_INDEX_SHIFT);
- sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
- IXGBE_ETS_DATA_LOC_SHIFT);
-
- if (sensor_location != 0) {
- status = hw->phy.ops.read_i2c_byte(hw,
- ixgbe_emc_temp_data[sensor_index],
- IXGBE_I2C_THERMAL_SENSOR_ADDR,
- &data->sensor[i].temp);
- if (status)
- goto out;
- }
- }
-out:
- return status;
-}
-
-/**
- * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
- * @hw: pointer to hardware structure
- *
- * Inits the thermal sensor thresholds according to the NVM map
- * and save off the threshold and location values into mac.thermal_sensor_data
- **/
-s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
-{
- s32 status = 0;
- u16 ets_offset;
- u16 ets_cfg;
- u16 ets_sensor;
- u8 low_thresh_delta;
- u8 num_sensors;
- u8 sensor_index;
- u8 sensor_location;
- u8 therm_limit;
- u8 i;
- struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
-
- memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
-
- /* Only support thermal sensors attached to 82599 physical port 0 */
- if ((hw->mac.type != ixgbe_mac_82599EB) ||
- (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
- return IXGBE_NOT_IMPLEMENTED;
-
- hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
- if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
- return IXGBE_NOT_IMPLEMENTED;
-
- hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
- if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
- != IXGBE_ETS_TYPE_EMC)
- return IXGBE_NOT_IMPLEMENTED;
-
- low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
- IXGBE_ETS_LTHRES_DELTA_SHIFT);
- num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
-
- for (i = 0; i < num_sensors; i++) {
- hw->eeprom.ops.read(hw, (ets_offset + 1 + i), &ets_sensor);
- sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
- IXGBE_ETS_DATA_INDEX_SHIFT);
- sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
- IXGBE_ETS_DATA_LOC_SHIFT);
- therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
-
- hw->phy.ops.write_i2c_byte(hw,
- ixgbe_emc_therm_limit[sensor_index],
- IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
-
- if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {
- data->sensor[i].location = sensor_location;
- data->sensor[i].caution_thresh = therm_limit;
- data->sensor[i].max_op_thresh = therm_limit -
- low_thresh_delta;
- }
- }
- return status;
-}
diff --git a/kernel/linux/kni/ethtool/ixgbe/ixgbe_common.h b/kernel/linux/kni/ethtool/ixgbe/ixgbe_common.h
deleted file mode 100644
index 2989a80..0000000
--- a/kernel/linux/kni/ethtool/ixgbe/ixgbe_common.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*******************************************************************************
-
- Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2012 Intel Corporation.
-
- Contact Information:
- e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
- Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-
-#ifndef _IXGBE_COMMON_H_
-#define _IXGBE_COMMON_H_
-
-#include "ixgbe_type.h"
-
-u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
-
-s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
-s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
-s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);
-s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw);
-s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
-s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
- u32 pba_num_size);
-s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
-s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
-void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
-s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);
-
-s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);
-s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);
-
-s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
-s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
-s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
- u16 words, u16 *data);
-s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
-s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
- u16 words, u16 *data);
-s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
-s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
- u16 words, u16 *data);
-s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
- u16 *data);
-s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
- u16 words, u16 *data);
-u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw);
-s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
- u16 *checksum_val);
-s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);
-s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
-
-s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
- u32 enable_addr);
-s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index);
-s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);
-s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
- u32 mc_addr_count,
- ixgbe_mc_addr_itr func, bool clear);
-s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
- u32 addr_count, ixgbe_mc_addr_itr func);
-s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
-s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
-s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
-s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw);
-s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw);
-
-s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw);
-void ixgbe_fc_autoneg(struct ixgbe_hw *hw);
-
-s32 ixgbe_validate_mac_addr(u8 *mac_addr);
-s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask);
-void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask);
-s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
-
-s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index);
-s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index);
-
-s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);
-s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);
-
-s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
-s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq);
-s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
-s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
-s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw);
-s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan,
- u32 vind, bool vlan_on);
-s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
- bool vlan_on, bool *vfta_changed);
-s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);
-s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan);
-
-s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed,
- bool *link_up, bool link_up_wait_to_complete);
-
-s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
- u16 *wwpn_prefix);
-
-s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs);
-void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf);
-void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
-s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps);
-void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
- int strategy);
-s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
- u8 build, u8 ver);
-void ixgbe_clear_tx_pending(struct ixgbe_hw *hw);
-
-#define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8
-#define IXGBE_EMC_INTERNAL_DATA 0x00
-#define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20
-#define IXGBE_EMC_DIODE1_DATA 0x01
-#define IXGBE_EMC_DIODE1_THERM_LIMIT 0x19
-#define IXGBE_EMC_DIODE2_DATA 0x23
-#define IXGBE_EMC_DIODE2_THERM_LIMIT 0x1A
-#define IXGBE_EMC_DIODE3_DATA 0x2A
-#define IXGBE_EMC_DIODE3_THERM_LIMIT 0x30
-
-s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw);
-s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw);
-#endif /* IXGBE_COMMON */
diff --git a/kernel/linux/kni/ethtool/ixgbe/ixgbe_dcb.h b/kernel/linux/kni/ethtool/ixgbe/ixgbe_dcb.h
deleted file mode 100644
index e9a099d..0000000
--- a/kernel/linux/kni/ethtool/ixgbe/ixgbe_dcb.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*******************************************************************************
-
- Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2012 Intel Corporation.
-
- Contact Information:
- e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
- Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-
-#ifndef _IXGBE_DCB_H_
-#define _IXGBE_DCB_H_
-
-
-#include "ixgbe_type.h"
-
-/* DCB defines */
-/* DCB credit calculation defines */
-#define IXGBE_DCB_CREDIT_QUANTUM 64
-#define IXGBE_DCB_MAX_CREDIT_REFILL 200 /* 200 * 64B = 12800B */
-#define IXGBE_DCB_MAX_TSO_SIZE (32 * 1024) /* Max TSO pkt size in DCB*/
-#define IXGBE_DCB_MAX_CREDIT (2 * IXGBE_DCB_MAX_CREDIT_REFILL)
-
-/* 513 for 32KB TSO packet */
-#define IXGBE_DCB_MIN_TSO_CREDIT \
- ((IXGBE_DCB_MAX_TSO_SIZE / IXGBE_DCB_CREDIT_QUANTUM) + 1)
-
-/* DCB configuration defines */
-#define IXGBE_DCB_MAX_USER_PRIORITY 8
-#define IXGBE_DCB_MAX_BW_GROUP 8
-#define IXGBE_DCB_BW_PERCENT 100
-
-#define IXGBE_DCB_TX_CONFIG 0
-#define IXGBE_DCB_RX_CONFIG 1
-
-/* DCB capability defines */
-#define IXGBE_DCB_PG_SUPPORT 0x00000001
-#define IXGBE_DCB_PFC_SUPPORT 0x00000002
-#define IXGBE_DCB_BCN_SUPPORT 0x00000004
-#define IXGBE_DCB_UP2TC_SUPPORT 0x00000008
-#define IXGBE_DCB_GSP_SUPPORT 0x00000010
-
-struct ixgbe_dcb_support {
- u32 capabilities; /* DCB capabilities */
-
- /* Each bit represents a number of TCs configurable in the hw.
- * If 8 traffic classes can be configured, the value is 0x80. */
- u8 traffic_classes;
- u8 pfc_traffic_classes;
-};
-
-enum ixgbe_dcb_tsa {
- ixgbe_dcb_tsa_ets = 0,
- ixgbe_dcb_tsa_group_strict_cee,
- ixgbe_dcb_tsa_strict
-};
-
-/* Traffic class bandwidth allocation per direction */
-struct ixgbe_dcb_tc_path {
- u8 bwg_id; /* Bandwidth Group (BWG) ID */
- u8 bwg_percent; /* % of BWG's bandwidth */
- u8 link_percent; /* % of link bandwidth */
- u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */
- u16 data_credits_refill; /* Credit refill amount in 64B granularity */
- u16 data_credits_max; /* Max credits for a configured packet buffer
- * in 64B granularity.*/
- enum ixgbe_dcb_tsa tsa; /* Link or Group Strict Priority */
-};
-
-enum ixgbe_dcb_pfc {
- ixgbe_dcb_pfc_disabled = 0,
- ixgbe_dcb_pfc_enabled,
- ixgbe_dcb_pfc_enabled_txonly,
- ixgbe_dcb_pfc_enabled_rxonly
-};
-
-/* Traffic class configuration */
-struct ixgbe_dcb_tc_config {
- struct ixgbe_dcb_tc_path path[2]; /* One each for Tx/Rx */
- enum ixgbe_dcb_pfc pfc; /* Class based flow control setting */
-
- u16 desc_credits_max; /* For Tx Descriptor arbitration */
- u8 tc; /* Traffic class (TC) */
-};
-
-enum ixgbe_dcb_pba {
- /* PBA[0-7] each use 64KB FIFO */
- ixgbe_dcb_pba_equal = PBA_STRATEGY_EQUAL,
- /* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */
- ixgbe_dcb_pba_80_48 = PBA_STRATEGY_WEIGHTED
-};
-
-struct ixgbe_dcb_num_tcs {
- u8 pg_tcs;
- u8 pfc_tcs;
-};
-
-struct ixgbe_dcb_config {
- struct ixgbe_dcb_tc_config tc_config[IXGBE_DCB_MAX_TRAFFIC_CLASS];
- struct ixgbe_dcb_support support;
- struct ixgbe_dcb_num_tcs num_tcs;
- u8 bw_percentage[2][IXGBE_DCB_MAX_BW_GROUP]; /* One each for Tx/Rx */
- bool pfc_mode_enable;
- bool round_robin_enable;
-
- enum ixgbe_dcb_pba rx_pba_cfg;
-
- u32 dcb_cfg_version; /* Not used...OS-specific? */
- u32 link_speed; /* For bandwidth allocation validation purpose */
- bool vt_mode;
-};
-
-/* DCB driver APIs */
-
-/* DCB rule checking */
-s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *);
-
-/* DCB credits calculation */
-s32 ixgbe_dcb_calculate_tc_credits(u8 *, u16 *, u16 *, int);
-s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *,
- struct ixgbe_dcb_config *, u32, u8);
-
-/* DCB PFC */
-s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *, u8, u8 *);
-s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *);
-
-/* DCB stats */
-s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *);
-s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);
-s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);
-
-/* DCB config arbiters */
-s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *,
- struct ixgbe_dcb_config *);
-s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *,
- struct ixgbe_dcb_config *);
-s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *,
- struct ixgbe_dcb_config *);
-
-/* DCB unpack routines */
-void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *, u8 *, u8 *);
-void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *, int, u16 *);
-void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *, u16 *);
-void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *, int, u8 *);
-void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *, int, u8 *);
-void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *, int, u8 *);
-
-/* DCB initialization */
-s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, u16 *, u16 *, u8 *, u8 *, u8 *);
-s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *);
-#endif /* _IXGBE_DCB_H_ */
diff --git a/kernel/linux/kni/ethtool/ixgbe/ixgbe_ethtool.c b/kernel/linux/kni/ethtool/ixgbe/ixgbe_ethtool.c
deleted file mode 100644
index f2ded19..0000000
--- a/kernel/linux/kni/ethtool/ixgbe/ixgbe_ethtool.c
+++ /dev/null
@@ -1,2894 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*******************************************************************************
-
- Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2012 Intel Corporation.
-
- Contact Information:
- e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
- Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-
-/* ethtool support for ixgbe */
-
-#include <linux/types.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <linux/netdevice.h>
-#include <linux/ethtool.h>
-#include <linux/vmalloc.h>
-#include <linux/highmem.h>
-#ifdef SIOCETHTOOL
-#include <asm/uaccess.h>
-
-#include "ixgbe.h"
-
-#ifndef ETH_GSTRING_LEN
-#define ETH_GSTRING_LEN 32
-#endif
-
-#define IXGBE_ALL_RAR_ENTRIES 16
-
-#ifdef ETHTOOL_OPS_COMPAT
-#include "kcompat_ethtool.c"
-#endif
-#ifdef ETHTOOL_GSTATS
-struct ixgbe_stats {
- char stat_string[ETH_GSTRING_LEN];
- int sizeof_stat;
- int stat_offset;
-};
-
-#define IXGBE_NETDEV_STAT(_net_stat) { \
- .stat_string = #_net_stat, \
- .sizeof_stat = FIELD_SIZEOF(struct net_device_stats, _net_stat), \
- .stat_offset = offsetof(struct net_device_stats, _net_stat) \
-}
-static const struct ixgbe_stats ixgbe_gstrings_net_stats[] = {
- IXGBE_NETDEV_STAT(rx_packets),
- IXGBE_NETDEV_STAT(tx_packets),
- IXGBE_NETDEV_STAT(rx_bytes),
- IXGBE_NETDEV_STAT(tx_bytes),
- IXGBE_NETDEV_STAT(rx_errors),
- IXGBE_NETDEV_STAT(tx_errors),
- IXGBE_NETDEV_STAT(rx_dropped),
- IXGBE_NETDEV_STAT(tx_dropped),
- IXGBE_NETDEV_STAT(multicast),
- IXGBE_NETDEV_STAT(collisions),
- IXGBE_NETDEV_STAT(rx_over_errors),
- IXGBE_NETDEV_STAT(rx_crc_errors),
- IXGBE_NETDEV_STAT(rx_frame_errors),
- IXGBE_NETDEV_STAT(rx_fifo_errors),
- IXGBE_NETDEV_STAT(rx_missed_errors),
- IXGBE_NETDEV_STAT(tx_aborted_errors),
- IXGBE_NETDEV_STAT(tx_carrier_errors),
- IXGBE_NETDEV_STAT(tx_fifo_errors),
- IXGBE_NETDEV_STAT(tx_heartbeat_errors),
-};
-
-#define IXGBE_STAT(_name, _stat) { \
- .stat_string = _name, \
- .sizeof_stat = FIELD_SIZEOF(struct ixgbe_adapter, _stat), \
- .stat_offset = offsetof(struct ixgbe_adapter, _stat) \
-}
-static struct ixgbe_stats ixgbe_gstrings_stats[] = {
- IXGBE_STAT("rx_pkts_nic", stats.gprc),
- IXGBE_STAT("tx_pkts_nic", stats.gptc),
- IXGBE_STAT("rx_bytes_nic", stats.gorc),
- IXGBE_STAT("tx_bytes_nic", stats.gotc),
- IXGBE_STAT("lsc_int", lsc_int),
- IXGBE_STAT("tx_busy", tx_busy),
- IXGBE_STAT("non_eop_descs", non_eop_descs),
-#ifndef CONFIG_IXGBE_NAPI
- IXGBE_STAT("rx_dropped_backlog", rx_dropped_backlog),
-#endif
- IXGBE_STAT("broadcast", stats.bprc),
- IXGBE_STAT("rx_no_buffer_count", stats.rnbc[0]) ,
- IXGBE_STAT("tx_timeout_count", tx_timeout_count),
- IXGBE_STAT("tx_restart_queue", restart_queue),
- IXGBE_STAT("rx_long_length_errors", stats.roc),
- IXGBE_STAT("rx_short_length_errors", stats.ruc),
- IXGBE_STAT("tx_flow_control_xon", stats.lxontxc),
- IXGBE_STAT("rx_flow_control_xon", stats.lxonrxc),
- IXGBE_STAT("tx_flow_control_xoff", stats.lxofftxc),
- IXGBE_STAT("rx_flow_control_xoff", stats.lxoffrxc),
- IXGBE_STAT("rx_csum_offload_errors", hw_csum_rx_error),
- IXGBE_STAT("alloc_rx_page_failed", alloc_rx_page_failed),
- IXGBE_STAT("alloc_rx_buff_failed", alloc_rx_buff_failed),
-#ifndef IXGBE_NO_LRO
- IXGBE_STAT("lro_aggregated", lro_stats.coal),
- IXGBE_STAT("lro_flushed", lro_stats.flushed),
-#endif /* IXGBE_NO_LRO */
- IXGBE_STAT("rx_no_dma_resources", hw_rx_no_dma_resources),
- IXGBE_STAT("hw_rsc_aggregated", rsc_total_count),
- IXGBE_STAT("hw_rsc_flushed", rsc_total_flush),
-#ifdef HAVE_TX_MQ
- IXGBE_STAT("fdir_match", stats.fdirmatch),
- IXGBE_STAT("fdir_miss", stats.fdirmiss),
- IXGBE_STAT("fdir_overflow", fdir_overflow),
-#endif /* HAVE_TX_MQ */
-#ifdef IXGBE_FCOE
- IXGBE_STAT("fcoe_bad_fccrc", stats.fccrc),
- IXGBE_STAT("fcoe_last_errors", stats.fclast),
- IXGBE_STAT("rx_fcoe_dropped", stats.fcoerpdc),
- IXGBE_STAT("rx_fcoe_packets", stats.fcoeprc),
- IXGBE_STAT("rx_fcoe_dwords", stats.fcoedwrc),
- IXGBE_STAT("fcoe_noddp", stats.fcoe_noddp),
- IXGBE_STAT("fcoe_noddp_ext_buff", stats.fcoe_noddp_ext_buff),
- IXGBE_STAT("tx_fcoe_packets", stats.fcoeptc),
- IXGBE_STAT("tx_fcoe_dwords", stats.fcoedwtc),
-#endif /* IXGBE_FCOE */
- IXGBE_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
- IXGBE_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
- IXGBE_STAT("os2bmc_tx_by_host", stats.o2bspc),
- IXGBE_STAT("os2bmc_rx_by_host", stats.b2ogprc),
-};
-
-#define IXGBE_QUEUE_STATS_LEN \
- ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
- ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
- (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
-#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
-#define IXGBE_NETDEV_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_net_stats)
-#define IXGBE_PB_STATS_LEN ( \
- (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
- IXGBE_FLAG_DCB_ENABLED) ? \
- (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
- sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
- sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
- sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
- / sizeof(u64) : 0)
-#define IXGBE_VF_STATS_LEN \
- ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_vfs) * \
- (sizeof(struct vf_stats) / sizeof(u64)))
-#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
- IXGBE_NETDEV_STATS_LEN + \
- IXGBE_PB_STATS_LEN + \
- IXGBE_QUEUE_STATS_LEN + \
- IXGBE_VF_STATS_LEN)
-
-#endif /* ETHTOOL_GSTATS */
-#ifdef ETHTOOL_TEST
-static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
- "Register test (offline)", "Eeprom test (offline)",
- "Interrupt test (offline)", "Loopback test (offline)",
- "Link test (on/offline)"
-};
-#define IXGBE_TEST_LEN (sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN)
-#endif /* ETHTOOL_TEST */
-
-#ifndef ETHTOOL_GLINKSETTINGS
-int ixgbe_get_settings(struct net_device *netdev,
- struct ethtool_cmd *ecmd)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- struct ixgbe_hw *hw = &adapter->hw;
- u32 link_speed = 0;
- bool link_up;
-
- ecmd->supported = SUPPORTED_10000baseT_Full;
- ecmd->autoneg = AUTONEG_ENABLE;
- ecmd->transceiver = XCVR_EXTERNAL;
- if ((hw->phy.media_type == ixgbe_media_type_copper) ||
- (hw->phy.multispeed_fiber)) {
- ecmd->supported |= (SUPPORTED_1000baseT_Full |
- SUPPORTED_Autoneg);
- switch (hw->mac.type) {
- case ixgbe_mac_X540:
- ecmd->supported |= SUPPORTED_100baseT_Full;
- break;
- default:
- break;
- }
-
- ecmd->advertising = ADVERTISED_Autoneg;
- if (hw->phy.autoneg_advertised) {
- if (hw->phy.autoneg_advertised &
- IXGBE_LINK_SPEED_100_FULL)
- ecmd->advertising |= ADVERTISED_100baseT_Full;
- if (hw->phy.autoneg_advertised &
- IXGBE_LINK_SPEED_10GB_FULL)
- ecmd->advertising |= ADVERTISED_10000baseT_Full;
- if (hw->phy.autoneg_advertised &
- IXGBE_LINK_SPEED_1GB_FULL)
- ecmd->advertising |= ADVERTISED_1000baseT_Full;
- } else {
- /*
- * Default advertised modes in case
- * phy.autoneg_advertised isn't set.
- */
- ecmd->advertising |= (ADVERTISED_10000baseT_Full |
- ADVERTISED_1000baseT_Full);
- if (hw->mac.type == ixgbe_mac_X540)
- ecmd->advertising |= ADVERTISED_100baseT_Full;
- }
-
- if (hw->phy.media_type == ixgbe_media_type_copper) {
- ecmd->supported |= SUPPORTED_TP;
- ecmd->advertising |= ADVERTISED_TP;
- ecmd->port = PORT_TP;
- } else {
- ecmd->supported |= SUPPORTED_FIBRE;
- ecmd->advertising |= ADVERTISED_FIBRE;
- ecmd->port = PORT_FIBRE;
- }
- } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
- /* Set as FIBRE until SERDES defined in kernel */
- if (hw->device_id == IXGBE_DEV_ID_82598_BX) {
- ecmd->supported = (SUPPORTED_1000baseT_Full |
- SUPPORTED_FIBRE);
- ecmd->advertising = (ADVERTISED_1000baseT_Full |
- ADVERTISED_FIBRE);
- ecmd->port = PORT_FIBRE;
- ecmd->autoneg = AUTONEG_DISABLE;
- } else if ((hw->device_id == IXGBE_DEV_ID_82599_COMBO_BACKPLANE)
- || (hw->device_id == IXGBE_DEV_ID_82599_KX4_MEZZ)) {
- ecmd->supported |= (SUPPORTED_1000baseT_Full |
- SUPPORTED_Autoneg |
- SUPPORTED_FIBRE);
- ecmd->advertising = (ADVERTISED_10000baseT_Full |
- ADVERTISED_1000baseT_Full |
- ADVERTISED_Autoneg |
- ADVERTISED_FIBRE);
- ecmd->port = PORT_FIBRE;
- } else {
- ecmd->supported |= (SUPPORTED_1000baseT_Full |
- SUPPORTED_FIBRE);
- ecmd->advertising = (ADVERTISED_10000baseT_Full |
- ADVERTISED_1000baseT_Full |
- ADVERTISED_FIBRE);
- ecmd->port = PORT_FIBRE;
- }
- } else {
- ecmd->supported |= SUPPORTED_FIBRE;
- ecmd->advertising = (ADVERTISED_10000baseT_Full |
- ADVERTISED_FIBRE);
- ecmd->port = PORT_FIBRE;
- ecmd->autoneg = AUTONEG_DISABLE;
- }
-
-#ifdef HAVE_ETHTOOL_SFP_DISPLAY_PORT
- /* Get PHY type */
- switch (adapter->hw.phy.type) {
- case ixgbe_phy_tn:
- case ixgbe_phy_aq:
- case ixgbe_phy_cu_unknown:
- /* Copper 10G-BASET */
- ecmd->port = PORT_TP;
- break;
- case ixgbe_phy_qt:
- ecmd->port = PORT_FIBRE;
- break;
- case ixgbe_phy_nl:
- case ixgbe_phy_sfp_passive_tyco:
- case ixgbe_phy_sfp_passive_unknown:
- case ixgbe_phy_sfp_ftl:
- case ixgbe_phy_sfp_avago:
- case ixgbe_phy_sfp_intel:
- case ixgbe_phy_sfp_unknown:
- switch (adapter->hw.phy.sfp_type) {
- /* SFP+ devices, further checking needed */
- case ixgbe_sfp_type_da_cu:
- case ixgbe_sfp_type_da_cu_core0:
- case ixgbe_sfp_type_da_cu_core1:
- ecmd->port = PORT_DA;
- break;
- case ixgbe_sfp_type_sr:
- case ixgbe_sfp_type_lr:
- case ixgbe_sfp_type_srlr_core0:
- case ixgbe_sfp_type_srlr_core1:
- ecmd->port = PORT_FIBRE;
- break;
- case ixgbe_sfp_type_not_present:
- ecmd->port = PORT_NONE;
- break;
- case ixgbe_sfp_type_1g_cu_core0:
- case ixgbe_sfp_type_1g_cu_core1:
- ecmd->port = PORT_TP;
- ecmd->supported = SUPPORTED_TP;
- ecmd->advertising = (ADVERTISED_1000baseT_Full |
- ADVERTISED_TP);
- break;
- case ixgbe_sfp_type_1g_sx_core0:
- case ixgbe_sfp_type_1g_sx_core1:
- ecmd->port = PORT_FIBRE;
- ecmd->supported = SUPPORTED_FIBRE;
- ecmd->advertising = (ADVERTISED_1000baseT_Full |
- ADVERTISED_FIBRE);
- break;
- case ixgbe_sfp_type_unknown:
- default:
- ecmd->port = PORT_OTHER;
- break;
- }
- break;
- case ixgbe_phy_xaui:
- ecmd->port = PORT_NONE;
- break;
- case ixgbe_phy_unknown:
- case ixgbe_phy_generic:
- case ixgbe_phy_sfp_unsupported:
- default:
- ecmd->port = PORT_OTHER;
- break;
- }
-#endif
-
- if (!in_interrupt()) {
- hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
- } else {
- /*
- * this case is a special workaround for RHEL5 bonding
- * that calls this routine from interrupt context
- */
- link_speed = adapter->link_speed;
- link_up = adapter->link_up;
- }
-
- if (link_up) {
- switch (link_speed) {
- case IXGBE_LINK_SPEED_10GB_FULL:
- ecmd->speed = SPEED_10000;
- break;
- case IXGBE_LINK_SPEED_1GB_FULL:
- ecmd->speed = SPEED_1000;
- break;
- case IXGBE_LINK_SPEED_100_FULL:
- ecmd->speed = SPEED_100;
- break;
- default:
- break;
- }
- ecmd->duplex = DUPLEX_FULL;
- } else {
- ecmd->speed = -1;
- ecmd->duplex = -1;
- }
-
- return 0;
-}
-#endif
-
-#ifndef ETHTOOL_SLINKSETTINGS
-static int ixgbe_set_settings(struct net_device *netdev,
- struct ethtool_cmd *ecmd)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- struct ixgbe_hw *hw = &adapter->hw;
- u32 advertised, old;
- s32 err = 0;
-
- if ((hw->phy.media_type == ixgbe_media_type_copper) ||
- (hw->phy.multispeed_fiber)) {
- /*
- * this function does not support duplex forcing, but can
- * limit the advertising of the adapter to the specified speed
- */
- if (ecmd->autoneg == AUTONEG_DISABLE)
- return -EINVAL;
-
- if (ecmd->advertising & ~ecmd->supported)
- return -EINVAL;
-
- old = hw->phy.autoneg_advertised;
- advertised = 0;
- if (ecmd->advertising & ADVERTISED_10000baseT_Full)
- advertised |= IXGBE_LINK_SPEED_10GB_FULL;
-
- if (ecmd->advertising & ADVERTISED_1000baseT_Full)
- advertised |= IXGBE_LINK_SPEED_1GB_FULL;
-
- if (ecmd->advertising & ADVERTISED_100baseT_Full)
- advertised |= IXGBE_LINK_SPEED_100_FULL;
-
- if (old == advertised)
- return err;
- /* this sets the link speed and restarts auto-neg */
- hw->mac.autotry_restart = true;
- err = hw->mac.ops.setup_link(hw, advertised, true, true);
- if (err) {
- e_info(probe, "setup link failed with code %d\n", err);
- hw->mac.ops.setup_link(hw, old, true, true);
- }
- }
- return err;
-}
-#endif
-
-static void ixgbe_get_pauseparam(struct net_device *netdev,
- struct ethtool_pauseparam *pause)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- struct ixgbe_hw *hw = &adapter->hw;
-
- if (hw->fc.disable_fc_autoneg)
- pause->autoneg = 0;
- else
- pause->autoneg = 1;
-
- if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
- pause->rx_pause = 1;
- } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
- pause->tx_pause = 1;
- } else if (hw->fc.current_mode == ixgbe_fc_full) {
- pause->rx_pause = 1;
- pause->tx_pause = 1;
- }
-}
-
-static int ixgbe_set_pauseparam(struct net_device *netdev,
- struct ethtool_pauseparam *pause)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- struct ixgbe_hw *hw = &adapter->hw;
- struct ixgbe_fc_info fc = hw->fc;
-
- /* 82598 does no support link flow control with DCB enabled */
- if ((hw->mac.type == ixgbe_mac_82598EB) &&
- (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
- return -EINVAL;
-
- fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE);
-
- if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
- fc.requested_mode = ixgbe_fc_full;
- else if (pause->rx_pause)
- fc.requested_mode = ixgbe_fc_rx_pause;
- else if (pause->tx_pause)
- fc.requested_mode = ixgbe_fc_tx_pause;
- else
- fc.requested_mode = ixgbe_fc_none;
-
- /* if the thing changed then we'll update and use new autoneg */
- if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
- hw->fc = fc;
- if (netif_running(netdev))
- ixgbe_reinit_locked(adapter);
- else
- ixgbe_reset(adapter);
- }
-
- return 0;
-}
-
-static u32 ixgbe_get_msglevel(struct net_device *netdev)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- return adapter->msg_enable;
-}
-
-static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- adapter->msg_enable = data;
-}
-
-static int ixgbe_get_regs_len(struct net_device *netdev)
-{
-#define IXGBE_REGS_LEN 1129
- return IXGBE_REGS_LEN * sizeof(u32);
-}
-
-#define IXGBE_GET_STAT(_A_, _R_) (_A_->stats._R_)
-
-
-static void ixgbe_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
- void *p)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- struct ixgbe_hw *hw = &adapter->hw;
- u32 *regs_buff = p;
- u8 i;
-
- printk(KERN_DEBUG "ixgbe_get_regs_1\n");
- memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
- printk(KERN_DEBUG "ixgbe_get_regs_2 0x%p\n", hw->hw_addr);
-
- regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
-
- /* General Registers */
- regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
- printk(KERN_DEBUG "ixgbe_get_regs_3\n");
- regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
- regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
- regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
- regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
- regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
- regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
- regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
-
- printk(KERN_DEBUG "ixgbe_get_regs_4\n");
-
- /* NVM Register */
- regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
- regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
- regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
- regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
- regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
- regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
- regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
- regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
- regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
- regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
-
- /* Interrupt */
- /* don't read EICR because it can clear interrupt causes, instead
- * read EICS which is a shadow but doesn't clear EICR */
- regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
- regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
- regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
- regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
- regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
- regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
- regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
- regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
- regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
- regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
- regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
- regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
-
- /* Flow Control */
- regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
- regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
- regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
- regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
- regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
- for (i = 0; i < 8; i++) {
- switch (hw->mac.type) {
- case ixgbe_mac_82598EB:
- regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
- regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
- break;
- case ixgbe_mac_82599EB:
- case ixgbe_mac_X540:
- regs_buff[35 + i] = IXGBE_READ_REG(hw,
- IXGBE_FCRTL_82599(i));
- regs_buff[43 + i] = IXGBE_READ_REG(hw,
- IXGBE_FCRTH_82599(i));
- break;
- default:
- break;
- }
- }
- regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
- regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
-
- /* Receive DMA */
- for (i = 0; i < 64; i++)
- regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
- for (i = 0; i < 64; i++)
- regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
- for (i = 0; i < 64; i++)
- regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
- for (i = 0; i < 64; i++)
- regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
- for (i = 0; i < 64; i++)
- regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
- for (i = 0; i < 64; i++)
- regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
- for (i = 0; i < 16; i++)
- regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
- for (i = 0; i < 16; i++)
- regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
- regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
- for (i = 0; i < 8; i++)
- regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
- regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
- regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
-
- /* Receive */
- regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
- regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
- for (i = 0; i < 16; i++)
- regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
- for (i = 0; i < 16; i++)
- regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
- regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
- regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
- regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
- regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
- regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
- regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
- for (i = 0; i < 8; i++)
- regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
- for (i = 0; i < 8; i++)
- regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
- regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
-
- /* Transmit */
- for (i = 0; i < 32; i++)
- regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
- for (i = 0; i < 32; i++)
- regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
- for (i = 0; i < 32; i++)
- regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
- for (i = 0; i < 32; i++)
- regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
- for (i = 0; i < 32; i++)
- regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
- for (i = 0; i < 32; i++)
- regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
- for (i = 0; i < 32; i++)
- regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
- for (i = 0; i < 32; i++)
- regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
- regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
- for (i = 0; i < 16; i++)
- regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
- regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
- for (i = 0; i < 8; i++)
- regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
- regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
-
- /* Wake Up */
- regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
- regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
- regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
- regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
- regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
- regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
- regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
- regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
- regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
-
- /* DCB */
- regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
- regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
- regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
- regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
- for (i = 0; i < 8; i++)
- regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
- for (i = 0; i < 8; i++)
- regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
- for (i = 0; i < 8; i++)
- regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
- for (i = 0; i < 8; i++)
- regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
- for (i = 0; i < 8; i++)
- regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
- for (i = 0; i < 8; i++)
- regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
-
- /* Statistics */
- regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
- regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
- regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
- regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
- for (i = 0; i < 8; i++)
- regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
- regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
- regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
- regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
- regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
- regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
- regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
- regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
- for (i = 0; i < 8; i++)
- regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
- for (i = 0; i < 8; i++)
- regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
- for (i = 0; i < 8; i++)
- regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
- for (i = 0; i < 8; i++)
- regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
- regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
- regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
- regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
- regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
- regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
- regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
- regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
- regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
- regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
- regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
- regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
- regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
- for (i = 0; i < 8; i++)
- regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
- regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
- regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
- regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
- regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
- regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
- regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
- regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
- regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
- regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
- regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
- regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
- regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
- regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
- regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
- regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
- regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
- regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
- regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
- regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
- for (i = 0; i < 16; i++)
- regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
- for (i = 0; i < 16; i++)
- regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
- for (i = 0; i < 16; i++)
- regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
- for (i = 0; i < 16; i++)
- regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
-
- /* MAC */
- regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
- regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
- regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
- regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
- regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
- regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
- regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
- regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
- regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
- regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
- regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
- regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
- regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
- regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
- regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
- regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
- regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
- regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
- regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
- regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
- regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
- regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
- regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
- regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
- regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
- regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
- regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
- regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
- regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
- regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
- regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
- regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
- regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
-
- /* Diagnostic */
- regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
- for (i = 0; i < 8; i++)
- regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
- regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
- for (i = 0; i < 4; i++)
- regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
- regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
- regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
- for (i = 0; i < 8; i++)
- regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
- regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
- for (i = 0; i < 4; i++)
- regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
- regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
- regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
- regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
- regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
- regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
- regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
- regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
- regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
- regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
- regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
- regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
- for (i = 0; i < 8; i++)
- regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
- regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
- regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
- regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
- regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
- regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
- regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
- regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
- regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
- regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
-
- /* 82599 X540 specific registers */
- regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN);
-}
-
-static int ixgbe_get_eeprom_len(struct net_device *netdev)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- return adapter->hw.eeprom.word_size * 2;
-}
-
-static int ixgbe_get_eeprom(struct net_device *netdev,
- struct ethtool_eeprom *eeprom, u8 *bytes)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- struct ixgbe_hw *hw = &adapter->hw;
- u16 *eeprom_buff;
- int first_word, last_word, eeprom_len;
- int ret_val = 0;
- u16 i;
-
- if (eeprom->len == 0)
- return -EINVAL;
-
- eeprom->magic = hw->vendor_id | (hw->device_id << 16);
-
- first_word = eeprom->offset >> 1;
- last_word = (eeprom->offset + eeprom->len - 1) >> 1;
- eeprom_len = last_word - first_word + 1;
-
- eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
- if (!eeprom_buff)
- return -ENOMEM;
-
- ret_val = ixgbe_read_eeprom_buffer(hw, first_word, eeprom_len,
- eeprom_buff);
-
- /* Device's eeprom is always little-endian, word addressable */
- for (i = 0; i < eeprom_len; i++)
- le16_to_cpus(&eeprom_buff[i]);
-
- memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
- kfree(eeprom_buff);
-
- return ret_val;
-}
-
-static int ixgbe_set_eeprom(struct net_device *netdev,
- struct ethtool_eeprom *eeprom, u8 *bytes)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- struct ixgbe_hw *hw = &adapter->hw;
- u16 *eeprom_buff;
- void *ptr;
- int max_len, first_word, last_word, ret_val = 0;
- u16 i;
-
- if (eeprom->len == 0)
- return -EINVAL;
-
- if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
- return -EINVAL;
-
- max_len = hw->eeprom.word_size * 2;
-
- first_word = eeprom->offset >> 1;
- last_word = (eeprom->offset + eeprom->len - 1) >> 1;
- eeprom_buff = kmalloc(max_len, GFP_KERNEL);
- if (!eeprom_buff)
- return -ENOMEM;
-
- ptr = eeprom_buff;
-
- if (eeprom->offset & 1) {
- /*
- * need read/modify/write of first changed EEPROM word
- * only the second byte of the word is being modified
- */
- ret_val = ixgbe_read_eeprom(hw, first_word, &eeprom_buff[0]);
- if (ret_val)
- goto err;
-
- ptr++;
- }
- if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
- /*
- * need read/modify/write of last changed EEPROM word
- * only the first byte of the word is being modified
- */
- ret_val = ixgbe_read_eeprom(hw, last_word,
- &eeprom_buff[last_word - first_word]);
- if (ret_val)
- goto err;
- }
-
- /* Device's eeprom is always little-endian, word addressable */
- for (i = 0; i < last_word - first_word + 1; i++)
- le16_to_cpus(&eeprom_buff[i]);
-
- memcpy(ptr, bytes, eeprom->len);
-
- for (i = 0; i < last_word - first_word + 1; i++)
- cpu_to_le16s(&eeprom_buff[i]);
-
- ret_val = ixgbe_write_eeprom_buffer(hw, first_word,
- last_word - first_word + 1,
- eeprom_buff);
-
- /* Update the checksum */
- if (ret_val == 0)
- ixgbe_update_eeprom_checksum(hw);
-
-err:
- kfree(eeprom_buff);
- return ret_val;
-}
-
-static void ixgbe_get_drvinfo(struct net_device *netdev,
- struct ethtool_drvinfo *drvinfo)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
-
- strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
-
- strlcpy(drvinfo->version, ixgbe_driver_version,
- sizeof(drvinfo->version));
-
- strlcpy(drvinfo->fw_version, adapter->eeprom_id,
- sizeof(drvinfo->fw_version));
-
- strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
- sizeof(drvinfo->bus_info));
-
- drvinfo->n_stats = IXGBE_STATS_LEN;
- drvinfo->testinfo_len = IXGBE_TEST_LEN;
- drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
-}
-
-static void ixgbe_get_ringparam(struct net_device *netdev,
- struct ethtool_ringparam *ring)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
-
- ring->rx_max_pending = IXGBE_MAX_RXD;
- ring->tx_max_pending = IXGBE_MAX_TXD;
- ring->rx_mini_max_pending = 0;
- ring->rx_jumbo_max_pending = 0;
- ring->rx_pending = adapter->rx_ring_count;
- ring->tx_pending = adapter->tx_ring_count;
- ring->rx_mini_pending = 0;
- ring->rx_jumbo_pending = 0;
-}
-
-static int ixgbe_set_ringparam(struct net_device *netdev,
- struct ethtool_ringparam *ring)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- struct ixgbe_ring *tx_ring = NULL, *rx_ring = NULL;
- u32 new_rx_count, new_tx_count;
- int i, err = 0;
-
- if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
- return -EINVAL;
-
- new_tx_count = clamp_t(u32, ring->tx_pending,
- IXGBE_MIN_TXD, IXGBE_MAX_TXD);
- new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
-
- new_rx_count = clamp_t(u32, ring->rx_pending,
- IXGBE_MIN_RXD, IXGBE_MAX_RXD);
- new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
-
- /* if nothing to do return success */
- if ((new_tx_count == adapter->tx_ring_count) &&
- (new_rx_count == adapter->rx_ring_count))
- return 0;
-
- while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
- usleep_range(1000, 2000);
-
- if (!netif_running(adapter->netdev)) {
- for (i = 0; i < adapter->num_tx_queues; i++)
- adapter->tx_ring[i]->count = new_tx_count;
- for (i = 0; i < adapter->num_rx_queues; i++)
- adapter->rx_ring[i]->count = new_rx_count;
- adapter->tx_ring_count = new_tx_count;
- adapter->rx_ring_count = new_rx_count;
- goto clear_reset;
- }
-
- /* alloc updated Tx resources */
- if (new_tx_count != adapter->tx_ring_count) {
- tx_ring = vmalloc(adapter->num_tx_queues * sizeof(*tx_ring));
- if (!tx_ring) {
- err = -ENOMEM;
- goto clear_reset;
- }
-
- for (i = 0; i < adapter->num_tx_queues; i++) {
- /* clone ring and setup updated count */
- tx_ring[i] = *adapter->tx_ring[i];
- tx_ring[i].count = new_tx_count;
- err = ixgbe_setup_tx_resources(&tx_ring[i]);
- if (err) {
- while (i) {
- i--;
- ixgbe_free_tx_resources(&tx_ring[i]);
- }
-
- vfree(tx_ring);
- tx_ring = NULL;
-
- goto clear_reset;
- }
- }
- }
-
- /* alloc updated Rx resources */
- if (new_rx_count != adapter->rx_ring_count) {
- rx_ring = vmalloc(adapter->num_rx_queues * sizeof(*rx_ring));
- if (!rx_ring) {
- err = -ENOMEM;
- goto clear_reset;
- }
-
- for (i = 0; i < adapter->num_rx_queues; i++) {
- /* clone ring and setup updated count */
- rx_ring[i] = *adapter->rx_ring[i];
- rx_ring[i].count = new_rx_count;
- err = ixgbe_setup_rx_resources(&rx_ring[i]);
- if (err) {
- while (i) {
- i--;
- ixgbe_free_rx_resources(&rx_ring[i]);
- }
-
- vfree(rx_ring);
- rx_ring = NULL;
-
- goto clear_reset;
- }
- }
- }
-
- /* bring interface down to prepare for update */
- ixgbe_down(adapter);
-
- /* Tx */
- if (tx_ring) {
- for (i = 0; i < adapter->num_tx_queues; i++) {
- ixgbe_free_tx_resources(adapter->tx_ring[i]);
- *adapter->tx_ring[i] = tx_ring[i];
- }
- adapter->tx_ring_count = new_tx_count;
-
- vfree(tx_ring);
- tx_ring = NULL;
- }
-
- /* Rx */
- if (rx_ring) {
- for (i = 0; i < adapter->num_rx_queues; i++) {
- ixgbe_free_rx_resources(adapter->rx_ring[i]);
- *adapter->rx_ring[i] = rx_ring[i];
- }
- adapter->rx_ring_count = new_rx_count;
-
- vfree(rx_ring);
- rx_ring = NULL;
- }
-
- /* restore interface using new values */
- ixgbe_up(adapter);
-
-clear_reset:
- /* free Tx resources if Rx error is encountered */
- if (tx_ring) {
- for (i = 0; i < adapter->num_tx_queues; i++)
- ixgbe_free_tx_resources(&tx_ring[i]);
- vfree(tx_ring);
- }
-
- clear_bit(__IXGBE_RESETTING, &adapter->state);
- return err;
-}
-
-#ifndef HAVE_ETHTOOL_GET_SSET_COUNT
-static int ixgbe_get_stats_count(struct net_device *netdev)
-{
- return IXGBE_STATS_LEN;
-}
-
-#else /* HAVE_ETHTOOL_GET_SSET_COUNT */
-static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
-{
- switch (sset) {
- case ETH_SS_TEST:
- return IXGBE_TEST_LEN;
- case ETH_SS_STATS:
- return IXGBE_STATS_LEN;
- default:
- return -EOPNOTSUPP;
- }
-}
-
-#endif /* HAVE_ETHTOOL_GET_SSET_COUNT */
-static void ixgbe_get_ethtool_stats(struct net_device *netdev,
- struct ethtool_stats *stats, u64 *data)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
-#ifdef HAVE_NETDEV_STATS_IN_NETDEV
- struct net_device_stats *net_stats = &netdev->stats;
-#else
- struct net_device_stats *net_stats = &adapter->net_stats;
-#endif
- u64 *queue_stat;
- int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64);
- int i, j, k;
- char *p;
-
- printk(KERN_DEBUG "ixgbe_stats 0\n");
- ixgbe_update_stats(adapter);
- printk(KERN_DEBUG "ixgbe_stats 1\n");
-
- for (i = 0; i < IXGBE_NETDEV_STATS_LEN; i++) {
- p = (char *)net_stats + ixgbe_gstrings_net_stats[i].stat_offset;
- data[i] = (ixgbe_gstrings_net_stats[i].sizeof_stat ==
- sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
- }
- for (j = 0; j < IXGBE_GLOBAL_STATS_LEN; j++, i++) {
- p = (char *)adapter + ixgbe_gstrings_stats[j].stat_offset;
- data[i] = (ixgbe_gstrings_stats[j].sizeof_stat ==
- sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
- }
- printk(KERN_DEBUG "ixgbe_stats 2\n");
-#ifdef NO_VNIC
- for (j = 0; j < adapter->num_tx_queues; j++) {
- queue_stat = (u64 *)&adapter->tx_ring[j]->stats;
- for (k = 0; k < stat_count; k++)
- data[i + k] = queue_stat[k];
- i += k;
- }
- for (j = 0; j < adapter->num_rx_queues; j++) {
- queue_stat = (u64 *)&adapter->rx_ring[j]->stats;
- for (k = 0; k < stat_count; k++)
- data[i + k] = queue_stat[k];
- i += k;
- }
- printk(KERN_DEBUG "ixgbe_stats 3\n");
-#endif
- if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
- for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
- data[i++] = adapter->stats.pxontxc[j];
- data[i++] = adapter->stats.pxofftxc[j];
- }
- for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
- data[i++] = adapter->stats.pxonrxc[j];
- data[i++] = adapter->stats.pxoffrxc[j];
- }
- }
- printk(KERN_DEBUG "ixgbe_stats 4\n");
- stat_count = sizeof(struct vf_stats) / sizeof(u64);
- for (j = 0; j < adapter->num_vfs; j++) {
- queue_stat = (u64 *)&adapter->vfinfo[j].vfstats;
- for (k = 0; k < stat_count; k++)
- data[i + k] = queue_stat[k];
- queue_stat = (u64 *)&adapter->vfinfo[j].saved_rst_vfstats;
- for (k = 0; k < stat_count; k++)
- data[i + k] += queue_stat[k];
- i += k;
- }
-}
-
-static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
- u8 *data)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- char *p = (char *)data;
- int i;
-
- switch (stringset) {
- case ETH_SS_TEST:
- memcpy(data, *ixgbe_gstrings_test,
- IXGBE_TEST_LEN * ETH_GSTRING_LEN);
- break;
- case ETH_SS_STATS:
- for (i = 0; i < IXGBE_NETDEV_STATS_LEN; i++) {
- memcpy(p, ixgbe_gstrings_net_stats[i].stat_string,
- ETH_GSTRING_LEN);
- p += ETH_GSTRING_LEN;
- }
- for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
- memcpy(p, ixgbe_gstrings_stats[i].stat_string,
- ETH_GSTRING_LEN);
- p += ETH_GSTRING_LEN;
- }
- for (i = 0; i < adapter->num_tx_queues; i++) {
- sprintf(p, "tx_queue_%u_packets", i);
- p += ETH_GSTRING_LEN;
- sprintf(p, "tx_queue_%u_bytes", i);
- p += ETH_GSTRING_LEN;
- }
- for (i = 0; i < adapter->num_rx_queues; i++) {
- sprintf(p, "rx_queue_%u_packets", i);
- p += ETH_GSTRING_LEN;
- sprintf(p, "rx_queue_%u_bytes", i);
- p += ETH_GSTRING_LEN;
- }
- if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
- for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
- sprintf(p, "tx_pb_%u_pxon", i);
- p += ETH_GSTRING_LEN;
- sprintf(p, "tx_pb_%u_pxoff", i);
- p += ETH_GSTRING_LEN;
- }
- for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
- sprintf(p, "rx_pb_%u_pxon", i);
- p += ETH_GSTRING_LEN;
- sprintf(p, "rx_pb_%u_pxoff", i);
- p += ETH_GSTRING_LEN;
- }
- }
- for (i = 0; i < adapter->num_vfs; i++) {
- sprintf(p, "VF %d Rx Packets", i);
- p += ETH_GSTRING_LEN;
- sprintf(p, "VF %d Rx Bytes", i);
- p += ETH_GSTRING_LEN;
- sprintf(p, "VF %d Tx Packets", i);
- p += ETH_GSTRING_LEN;
- sprintf(p, "VF %d Tx Bytes", i);
- p += ETH_GSTRING_LEN;
- sprintf(p, "VF %d MC Packets", i);
- p += ETH_GSTRING_LEN;
- }
- /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
- break;
- }
-}
-
-static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
-{
- struct ixgbe_hw *hw = &adapter->hw;
- bool link_up;
- u32 link_speed = 0;
- *data = 0;
-
- hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
- if (link_up)
- return *data;
- else
- *data = 1;
- return *data;
-}
-
-/* ethtool register test data */
-struct ixgbe_reg_test {
- u16 reg;
- u8 array_len;
- u8 test_type;
- u32 mask;
- u32 write;
-};
-
-/* In the hardware, registers are laid out either singly, in arrays
- * spaced 0x40 bytes apart, or in contiguous tables. We assume
- * most tests take place on arrays or single registers (handled
- * as a single-element array) and special-case the tables.
- * Table tests are always pattern tests.
- *
- * We also make provision for some required setup steps by specifying
- * registers to be written without any read-back testing.
- */
-
-#define PATTERN_TEST 1
-#define SET_READ_TEST 2
-#define WRITE_NO_TEST 3
-#define TABLE32_TEST 4
-#define TABLE64_TEST_LO 5
-#define TABLE64_TEST_HI 6
-
-/* default 82599 register test */
-static struct ixgbe_reg_test reg_test_82599[] = {
- { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
- { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
- { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
- { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
- { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
- { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
- { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
- { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
- { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
- { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
- { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
- { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
- { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
- { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
- { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
- { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
- { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
- { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
- { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
- { 0, 0, 0, 0 }
-};
-
-/* default 82598 register test */
-static struct ixgbe_reg_test reg_test_82598[] = {
- { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
- { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
- { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
- { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
- { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
- { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
- { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
- /* Enable all four RX queues before testing. */
- { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
- /* RDH is read-only for 82598, only test RDT. */
- { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
- { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
- { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
- { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
- { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
- { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
- { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
- { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
- { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
- { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
- { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
- { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
- { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
- { 0, 0, 0, 0 }
-};
-
-#define REG_PATTERN_TEST(R, M, W) \
-{ \
- u32 pat, val, before; \
- const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
- for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { \
- before = readl(adapter->hw.hw_addr + R); \
- writel((_test[pat] & W), (adapter->hw.hw_addr + R)); \
- val = readl(adapter->hw.hw_addr + R); \
- if (val != (_test[pat] & W & M)) { \
- e_err(drv, "pattern test reg %04X failed: got " \
- "0x%08X expected 0x%08X\n", \
- R, val, (_test[pat] & W & M)); \
- *data = R; \
- writel(before, adapter->hw.hw_addr + R); \
- return 1; \
- } \
- writel(before, adapter->hw.hw_addr + R); \
- } \
-}
-
-#define REG_SET_AND_CHECK(R, M, W) \
-{ \
- u32 val, before; \
- before = readl(adapter->hw.hw_addr + R); \
- writel((W & M), (adapter->hw.hw_addr + R)); \
- val = readl(adapter->hw.hw_addr + R); \
- if ((W & M) != (val & M)) { \
- e_err(drv, "set/check reg %04X test failed: got 0x%08X " \
- "expected 0x%08X\n", R, (val & M), (W & M)); \
- *data = R; \
- writel(before, (adapter->hw.hw_addr + R)); \
- return 1; \
- } \
- writel(before, (adapter->hw.hw_addr + R)); \
-}
-
-static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
-{
- struct ixgbe_reg_test *test;
- u32 value, status_before, status_after;
- u32 i, toggle;
-
- switch (adapter->hw.mac.type) {
- case ixgbe_mac_82598EB:
- toggle = 0x7FFFF3FF;
- test = reg_test_82598;
- break;
- case ixgbe_mac_82599EB:
- case ixgbe_mac_X540:
- toggle = 0x7FFFF30F;
- test = reg_test_82599;
- break;
- default:
- *data = 1;
- return 1;
- break;
- }
-
- /*
- * Because the status register is such a special case,
- * we handle it separately from the rest of the register
- * tests. Some bits are read-only, some toggle, and some
- * are writeable on newer MACs.
- */
- status_before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
- value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
- IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
- status_after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
- if (value != status_after) {
- e_err(drv, "failed STATUS register test got: "
- "0x%08X expected: 0x%08X\n", status_after, value);
- *data = 1;
- return 1;
- }
- /* restore previous status */
- IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, status_before);
-
- /*
- * Perform the remainder of the register test, looping through
- * the test table until we either fail or reach the null entry.
- */
- while (test->reg) {
- for (i = 0; i < test->array_len; i++) {
- switch (test->test_type) {
- case PATTERN_TEST:
- REG_PATTERN_TEST(test->reg + (i * 0x40),
- test->mask,
- test->write);
- break;
- case SET_READ_TEST:
- REG_SET_AND_CHECK(test->reg + (i * 0x40),
- test->mask,
- test->write);
- break;
- case WRITE_NO_TEST:
- writel(test->write,
- (adapter->hw.hw_addr + test->reg)
- + (i * 0x40));
- break;
- case TABLE32_TEST:
- REG_PATTERN_TEST(test->reg + (i * 4),
- test->mask,
- test->write);
- break;
- case TABLE64_TEST_LO:
- REG_PATTERN_TEST(test->reg + (i * 8),
- test->mask,
- test->write);
- break;
- case TABLE64_TEST_HI:
- REG_PATTERN_TEST((test->reg + 4) + (i * 8),
- test->mask,
- test->write);
- break;
- }
- }
- test++;
- }
-
- *data = 0;
- return 0;
-}
-
-static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
-{
- if (ixgbe_validate_eeprom_checksum(&adapter->hw, NULL))
- *data = 1;
- else
- *data = 0;
- return *data;
-}
-
-static irqreturn_t ixgbe_test_intr(int irq, void *data)
-{
- struct net_device *netdev = data;
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
-
- adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
-
- return IRQ_HANDLED;
-}
-
-static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
-{
- struct net_device *netdev = adapter->netdev;
- u32 mask, i = 0, shared_int = true;
- u32 irq = adapter->pdev->irq;
-
- *data = 0;
-
- /* Hook up test interrupt handler just for this test */
- if (adapter->msix_entries) {
- /* NOTE: we don't test MSI-X interrupts here, yet */
- return 0;
- } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
- shared_int = false;
- if (request_irq(irq, &ixgbe_test_intr, 0, netdev->name,
- netdev)) {
- *data = 1;
- return -1;
- }
- } else if (!request_irq(irq, &ixgbe_test_intr, IRQF_PROBE_SHARED,
- netdev->name, netdev)) {
- shared_int = false;
- } else if (request_irq(irq, &ixgbe_test_intr, IRQF_SHARED,
- netdev->name, netdev)) {
- *data = 1;
- return -1;
- }
- e_info(hw, "testing %s interrupt\n",
- (shared_int ? "shared" : "unshared"));
-
- /* Disable all the interrupts */
- IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
- IXGBE_WRITE_FLUSH(&adapter->hw);
- usleep_range(10000, 20000);
-
- /* Test each interrupt */
- for (; i < 10; i++) {
- /* Interrupt to test */
- mask = 1 << i;
-
- if (!shared_int) {
- /*
- * Disable the interrupts to be reported in
- * the cause register and then force the same
- * interrupt and see if one gets posted. If
- * an interrupt was posted to the bus, the
- * test failed.
- */
- adapter->test_icr = 0;
- IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
- ~mask & 0x00007FFF);
- IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
- ~mask & 0x00007FFF);
- IXGBE_WRITE_FLUSH(&adapter->hw);
- usleep_range(10000, 20000);
-
- if (adapter->test_icr & mask) {
- *data = 3;
- break;
- }
- }
-
- /*
- * Enable the interrupt to be reported in the cause
- * register and then force the same interrupt and see
- * if one gets posted. If an interrupt was not posted
- * to the bus, the test failed.
- */
- adapter->test_icr = 0;
- IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
- IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
- IXGBE_WRITE_FLUSH(&adapter->hw);
- usleep_range(10000, 20000);
-
- if (!(adapter->test_icr & mask)) {
- *data = 4;
- break;
- }
-
- if (!shared_int) {
- /*
- * Disable the other interrupts to be reported in
- * the cause register and then force the other
- * interrupts and see if any get posted. If
- * an interrupt was posted to the bus, the
- * test failed.
- */
- adapter->test_icr = 0;
- IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
- ~mask & 0x00007FFF);
- IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
- ~mask & 0x00007FFF);
- IXGBE_WRITE_FLUSH(&adapter->hw);
- usleep_range(10000, 20000);
-
- if (adapter->test_icr) {
- *data = 5;
- break;
- }
- }
- }
-
- /* Disable all the interrupts */
- IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
- IXGBE_WRITE_FLUSH(&adapter->hw);
- usleep_range(10000, 20000);
-
- /* Unhook test interrupt handler */
- free_irq(irq, netdev);
-
- return *data;
-}
-
-
-
-static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
-{
- struct ixgbe_hw *hw = &adapter->hw;
- u32 reg_data;
-
- /* X540 needs to set the MACC.FLU bit to force link up */
- if (adapter->hw.mac.type == ixgbe_mac_X540) {
- reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
- reg_data |= IXGBE_MACC_FLU;
- IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
- }
-
- /* right now we only support MAC loopback in the driver */
- reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
- /* Setup MAC loopback */
- reg_data |= IXGBE_HLREG0_LPBK;
- IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);
-
- reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);
- reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
- IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
-
- reg_data = IXGBE_READ_REG(hw, IXGBE_AUTOC);
- reg_data &= ~IXGBE_AUTOC_LMS_MASK;
- reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
- IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
- IXGBE_WRITE_FLUSH(hw);
- usleep_range(10000, 20000);
-
- /* Disable Atlas Tx lanes; re-enabled in reset path */
- if (hw->mac.type == ixgbe_mac_82598EB) {
- u8 atlas;
-
- ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
- atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
- ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
-
- ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
- atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
- ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
-
- ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
- atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
- ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
-
- ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
- atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
- ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
- }
-
- return 0;
-}
-
-static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
-{
- u32 reg_data;
-
- reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
- reg_data &= ~IXGBE_HLREG0_LPBK;
- IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
-}
-
-
-
-
-
-
-static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
-{
-
- //*data = ixgbe_setup_desc_rings(adapter);
- //if (*data)
- // goto out;
- *data = ixgbe_setup_loopback_test(adapter);
- if (*data)
- goto err_loopback;
- //*data = ixgbe_run_loopback_test(adapter);
- ixgbe_loopback_cleanup(adapter);
-
-err_loopback:
- //ixgbe_free_desc_rings(adapter);
-//out:
- return *data;
-
-}
-
-#ifndef HAVE_ETHTOOL_GET_SSET_COUNT
-static int ixgbe_diag_test_count(struct net_device *netdev)
-{
- return IXGBE_TEST_LEN;
-}
-
-#endif /* HAVE_ETHTOOL_GET_SSET_COUNT */
-static void ixgbe_diag_test(struct net_device *netdev,
- struct ethtool_test *eth_test, u64 *data)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- bool if_running = netif_running(netdev);
-
- set_bit(__IXGBE_TESTING, &adapter->state);
- if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
- /* Offline tests */
-
- e_info(hw, "offline testing starting\n");
-
- /* Link test performed before hardware reset so autoneg doesn't
- * interfere with test result */
- if (ixgbe_link_test(adapter, &data[4]))
- eth_test->flags |= ETH_TEST_FL_FAILED;
-
- if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
- int i;
- for (i = 0; i < adapter->num_vfs; i++) {
- if (adapter->vfinfo[i].clear_to_send) {
- e_warn(drv, "Please take active VFS "
- "offline and restart the "
- "adapter before running NIC "
- "diagnostics\n");
- data[0] = 1;
- data[1] = 1;
- data[2] = 1;
- data[3] = 1;
- eth_test->flags |= ETH_TEST_FL_FAILED;
- clear_bit(__IXGBE_TESTING,
- &adapter->state);
- goto skip_ol_tests;
- }
- }
- }
-
- if (if_running)
- /* indicate we're in test mode */
- dev_close(netdev);
- else
- ixgbe_reset(adapter);
-
- e_info(hw, "register testing starting\n");
- if (ixgbe_reg_test(adapter, &data[0]))
- eth_test->flags |= ETH_TEST_FL_FAILED;
-
- ixgbe_reset(adapter);
- e_info(hw, "eeprom testing starting\n");
- if (ixgbe_eeprom_test(adapter, &data[1]))
- eth_test->flags |= ETH_TEST_FL_FAILED;
-
- ixgbe_reset(adapter);
- e_info(hw, "interrupt testing starting\n");
- if (ixgbe_intr_test(adapter, &data[2]))
- eth_test->flags |= ETH_TEST_FL_FAILED;
-
- /* If SRIOV or VMDq is enabled then skip MAC
- * loopback diagnostic. */
- if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
- IXGBE_FLAG_VMDQ_ENABLED)) {
- e_info(hw, "skip MAC loopback diagnostic in VT mode\n");
- data[3] = 0;
- goto skip_loopback;
- }
-
- ixgbe_reset(adapter);
- e_info(hw, "loopback testing starting\n");
- if (ixgbe_loopback_test(adapter, &data[3]))
- eth_test->flags |= ETH_TEST_FL_FAILED;
-
-skip_loopback:
- ixgbe_reset(adapter);
-
- clear_bit(__IXGBE_TESTING, &adapter->state);
- if (if_running)
- dev_open(netdev);
- } else {
- e_info(hw, "online testing starting\n");
- /* Online tests */
- if (ixgbe_link_test(adapter, &data[4]))
- eth_test->flags |= ETH_TEST_FL_FAILED;
-
- /* Online tests aren't run; pass by default */
- data[0] = 0;
- data[1] = 0;
- data[2] = 0;
- data[3] = 0;
-
- clear_bit(__IXGBE_TESTING, &adapter->state);
- }
-skip_ol_tests:
- msleep_interruptible(4 * 1000);
-}
-
-static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
- struct ethtool_wolinfo *wol)
-{
- struct ixgbe_hw *hw = &adapter->hw;
- int retval = 1;
- u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
-
- /* WOL not supported except for the following */
- switch (hw->device_id) {
- case IXGBE_DEV_ID_82599_SFP:
- /* Only these subdevice could supports WOL */
- switch (hw->subsystem_device_id) {
- case IXGBE_SUBDEV_ID_82599_560FLR:
- /* only support first port */
- if (hw->bus.func != 0) {
- wol->supported = 0;
- break;
- }
- case IXGBE_SUBDEV_ID_82599_SFP:
- retval = 0;
- break;
- default:
- wol->supported = 0;
- break;
- }
- break;
- case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
- /* All except this subdevice support WOL */
- if (hw->subsystem_device_id ==
- IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) {
- wol->supported = 0;
- break;
- }
- retval = 0;
- break;
- case IXGBE_DEV_ID_82599_KX4:
- retval = 0;
- break;
- case IXGBE_DEV_ID_X540T:
- /* check eeprom to see if enabled wol */
- if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
- ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
- (hw->bus.func == 0))) {
- retval = 0;
- break;
- }
-
- /* All others not supported */
- wol->supported = 0;
- break;
- default:
- wol->supported = 0;
- }
- return retval;
-}
-
-static void ixgbe_get_wol(struct net_device *netdev,
- struct ethtool_wolinfo *wol)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
-
- wol->supported = WAKE_UCAST | WAKE_MCAST |
- WAKE_BCAST | WAKE_MAGIC;
- wol->wolopts = 0;
-
- if (ixgbe_wol_exclusion(adapter, wol) ||
- !device_can_wakeup(&adapter->pdev->dev))
- return;
-
- if (adapter->wol & IXGBE_WUFC_EX)
- wol->wolopts |= WAKE_UCAST;
- if (adapter->wol & IXGBE_WUFC_MC)
- wol->wolopts |= WAKE_MCAST;
- if (adapter->wol & IXGBE_WUFC_BC)
- wol->wolopts |= WAKE_BCAST;
- if (adapter->wol & IXGBE_WUFC_MAG)
- wol->wolopts |= WAKE_MAGIC;
-}
-
-static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
-
- if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
- return -EOPNOTSUPP;
-
- if (ixgbe_wol_exclusion(adapter, wol))
- return wol->wolopts ? -EOPNOTSUPP : 0;
-
- adapter->wol = 0;
-
- if (wol->wolopts & WAKE_UCAST)
- adapter->wol |= IXGBE_WUFC_EX;
- if (wol->wolopts & WAKE_MCAST)
- adapter->wol |= IXGBE_WUFC_MC;
- if (wol->wolopts & WAKE_BCAST)
- adapter->wol |= IXGBE_WUFC_BC;
- if (wol->wolopts & WAKE_MAGIC)
- adapter->wol |= IXGBE_WUFC_MAG;
-
- device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
-
- return 0;
-}
-
-static int ixgbe_nway_reset(struct net_device *netdev)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
-
- if (netif_running(netdev))
- ixgbe_reinit_locked(adapter);
-
- return 0;
-}
-
-#ifdef HAVE_ETHTOOL_SET_PHYS_ID
-static int ixgbe_set_phys_id(struct net_device *netdev,
- enum ethtool_phys_id_state state)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- struct ixgbe_hw *hw = &adapter->hw;
-
- switch (state) {
- case ETHTOOL_ID_ACTIVE:
- adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
- return 2;
-
- case ETHTOOL_ID_ON:
- hw->mac.ops.led_on(hw, IXGBE_LED_ON);
- break;
-
- case ETHTOOL_ID_OFF:
- hw->mac.ops.led_off(hw, IXGBE_LED_ON);
- break;
-
- case ETHTOOL_ID_INACTIVE:
- /* Restore LED settings */
- IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
- break;
- }
-
- return 0;
-}
-#else
-static int ixgbe_phys_id(struct net_device *netdev, u32 data)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- struct ixgbe_hw *hw = &adapter->hw;
- u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
- u32 i;
-
- if (!data || data > 300)
- data = 300;
-
- for (i = 0; i < (data * 1000); i += 400) {
- ixgbe_led_on(hw, IXGBE_LED_ON);
- msleep_interruptible(200);
- ixgbe_led_off(hw, IXGBE_LED_ON);
- msleep_interruptible(200);
- }
-
- /* Restore LED settings */
- IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
-
- return 0;
-}
-#endif /* HAVE_ETHTOOL_SET_PHYS_ID */
-
-static int ixgbe_get_coalesce(struct net_device *netdev,
- struct ethtool_coalesce *ec)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
-
- ec->tx_max_coalesced_frames_irq = adapter->tx_work_limit;
-#ifndef CONFIG_IXGBE_NAPI
- ec->rx_max_coalesced_frames_irq = adapter->rx_work_limit;
-#endif /* CONFIG_IXGBE_NAPI */
- /* only valid if in constant ITR mode */
- if (adapter->rx_itr_setting <= 1)
- ec->rx_coalesce_usecs = adapter->rx_itr_setting;
- else
- ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
-
- /* if in mixed tx/rx queues per vector mode, report only rx settings */
- if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
- return 0;
-
- /* only valid if in constant ITR mode */
- if (adapter->tx_itr_setting <= 1)
- ec->tx_coalesce_usecs = adapter->tx_itr_setting;
- else
- ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
-
- return 0;
-}
-
-/*
- * this function must be called before setting the new value of
- * rx_itr_setting
- */
-#ifdef NO_VNIC
-static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter)
-{
- struct net_device *netdev = adapter->netdev;
-
- /* nothing to do if LRO or RSC are not enabled */
- if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) ||
- !(netdev->features & NETIF_F_LRO))
- return false;
-
- /* check the feature flag value and enable RSC if necessary */
- if (adapter->rx_itr_setting == 1 ||
- adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
- if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
- adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
- e_info(probe, "rx-usecs value high enough "
- "to re-enable RSC\n");
- return true;
- }
- /* if interrupt rate is too high then disable RSC */
- } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
- adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
-#ifdef IXGBE_NO_LRO
- e_info(probe, "rx-usecs set too low, disabling RSC\n");
-#else
- e_info(probe, "rx-usecs set too low, "
- "falling back to software LRO\n");
-#endif
- return true;
- }
- return false;
-}
-#endif
-
-static int ixgbe_set_coalesce(struct net_device *netdev,
- struct ethtool_coalesce *ec)
-{
-#ifdef NO_VNIC
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- struct ixgbe_q_vector *q_vector;
- int i;
- int num_vectors;
- u16 tx_itr_param, rx_itr_param;
- bool need_reset = false;
-
- /* don't accept tx specific changes if we've got mixed RxTx vectors */
- if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count
- && ec->tx_coalesce_usecs)
- return -EINVAL;
-
- if (ec->tx_max_coalesced_frames_irq)
- adapter->tx_work_limit = ec->tx_max_coalesced_frames_irq;
-
-#ifndef CONFIG_IXGBE_NAPI
- if (ec->rx_max_coalesced_frames_irq)
- adapter->rx_work_limit = ec->rx_max_coalesced_frames_irq;
-
-#endif
- if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) ||
- (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)))
- return -EINVAL;
-
- if (ec->rx_coalesce_usecs > 1)
- adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
- else
- adapter->rx_itr_setting = ec->rx_coalesce_usecs;
-
- if (adapter->rx_itr_setting == 1)
- rx_itr_param = IXGBE_20K_ITR;
- else
- rx_itr_param = adapter->rx_itr_setting;
-
- if (ec->tx_coalesce_usecs > 1)
- adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
- else
- adapter->tx_itr_setting = ec->tx_coalesce_usecs;
-
- if (adapter->tx_itr_setting == 1)
- tx_itr_param = IXGBE_10K_ITR;
- else
- tx_itr_param = adapter->tx_itr_setting;
-
- /* check the old value and enable RSC if necessary */
- need_reset = ixgbe_update_rsc(adapter);
-
- if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
- num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
- else
- num_vectors = 1;
-
- for (i = 0; i < num_vectors; i++) {
- q_vector = adapter->q_vector[i];
- q_vector->tx.work_limit = adapter->tx_work_limit;
- q_vector->rx.work_limit = adapter->rx_work_limit;
- if (q_vector->tx.count && !q_vector->rx.count)
- /* tx only */
- q_vector->itr = tx_itr_param;
- else
- /* rx only or mixed */
- q_vector->itr = rx_itr_param;
- ixgbe_write_eitr(q_vector);
- }
-
- /*
- * do reset here at the end to make sure EITR==0 case is handled
- * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
- * also locks in RSC enable/disable which requires reset
- */
- if (need_reset)
- ixgbe_do_reset(netdev);
-#endif
- return 0;
-}
-
-#ifndef HAVE_NDO_SET_FEATURES
-static u32 ixgbe_get_rx_csum(struct net_device *netdev)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- struct ixgbe_ring *ring = adapter->rx_ring[0];
- return test_bit(__IXGBE_RX_CSUM_ENABLED, &ring->state);
-}
-
-static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- int i;
-
- for (i = 0; i < adapter->num_rx_queues; i++) {
- struct ixgbe_ring *ring = adapter->rx_ring[i];
- if (data)
- set_bit(__IXGBE_RX_CSUM_ENABLED, &ring->state);
- else
- clear_bit(__IXGBE_RX_CSUM_ENABLED, &ring->state);
- }
-
- /* LRO and RSC both depend on RX checksum to function */
- if (!data && (netdev->features & NETIF_F_LRO)) {
- netdev->features &= ~NETIF_F_LRO;
-
- if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
- adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
- ixgbe_do_reset(netdev);
- }
- }
-
- return 0;
-}
-
-static u32 ixgbe_get_tx_csum(struct net_device *netdev)
-{
- return (netdev->features & NETIF_F_IP_CSUM) != 0;
-}
-
-static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- u32 feature_list;
-
-#ifdef NETIF_F_IPV6_CSUM
- feature_list = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
-#else
- feature_list = NETIF_F_IP_CSUM;
-#endif
- switch (adapter->hw.mac.type) {
- case ixgbe_mac_82599EB:
- case ixgbe_mac_X540:
- feature_list |= NETIF_F_SCTP_CSUM;
- break;
- default:
- break;
- }
- if (data)
- netdev->features |= feature_list;
- else
- netdev->features &= ~feature_list;
-
- return 0;
-}
-
-#ifdef NETIF_F_TSO
-static int ixgbe_set_tso(struct net_device *netdev, u32 data)
-{
- if (data) {
- netdev->features |= NETIF_F_TSO;
-#ifdef NETIF_F_TSO6
- netdev->features |= NETIF_F_TSO6;
-#endif
- } else {
-#ifndef HAVE_NETDEV_VLAN_FEATURES
-#ifdef NETIF_F_HW_VLAN_TX
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- /* disable TSO on all VLANs if they're present */
- if (adapter->vlgrp) {
- int i;
- struct net_device *v_netdev;
- for (i = 0; i < VLAN_N_VID; i++) {
- v_netdev =
- vlan_group_get_device(adapter->vlgrp, i);
- if (v_netdev) {
- v_netdev->features &= ~NETIF_F_TSO;
-#ifdef NETIF_F_TSO6
- v_netdev->features &= ~NETIF_F_TSO6;
-#endif
- vlan_group_set_device(adapter->vlgrp, i,
- v_netdev);
- }
- }
- }
-#endif
-#endif /* HAVE_NETDEV_VLAN_FEATURES */
- netdev->features &= ~NETIF_F_TSO;
-#ifdef NETIF_F_TSO6
- netdev->features &= ~NETIF_F_TSO6;
-#endif
- }
- return 0;
-}
-
-#endif /* NETIF_F_TSO */
-#ifdef ETHTOOL_GFLAGS
-static int ixgbe_set_flags(struct net_device *netdev, u32 data)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- u32 supported_flags = ETH_FLAG_RXVLAN | ETH_FLAG_TXVLAN;
- u32 changed = netdev->features ^ data;
- bool need_reset = false;
- int rc;
-
-#ifndef HAVE_VLAN_RX_REGISTER
- if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
- !(data & ETH_FLAG_RXVLAN))
- return -EINVAL;
-
-#endif
-#ifdef NETIF_F_RXHASH
- if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
- supported_flags |= ETH_FLAG_RXHASH;
-#endif
-#ifdef IXGBE_NO_LRO
- if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
-#endif
- supported_flags |= ETH_FLAG_LRO;
-
-#ifdef ETHTOOL_GRXRINGS
- switch (adapter->hw.mac.type) {
- case ixgbe_mac_X540:
- case ixgbe_mac_82599EB:
- supported_flags |= ETH_FLAG_NTUPLE;
- default:
- break;
- }
-
-#endif
- rc = ethtool_op_set_flags(netdev, data, supported_flags);
- if (rc)
- return rc;
-
-#ifndef HAVE_VLAN_RX_REGISTER
- if (changed & ETH_FLAG_RXVLAN)
- ixgbe_vlan_mode(netdev, netdev->features);
-
-#endif
- /* if state changes we need to update adapter->flags and reset */
- if (!(netdev->features & NETIF_F_LRO)) {
- if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
- need_reset = true;
- adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
- } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
- !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
- if (adapter->rx_itr_setting == 1 ||
- adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
- adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
- need_reset = true;
- } else if (changed & ETH_FLAG_LRO) {
-#ifdef IXGBE_NO_LRO
- e_info(probe, "rx-usecs set too low, "
- "disabling RSC\n");
-#else
- e_info(probe, "rx-usecs set too low, "
- "falling back to software LRO\n");
-#endif
- }
- }
-
-#ifdef ETHTOOL_GRXRINGS
- /*
- * Check if Flow Director n-tuple support was enabled or disabled. If
- * the state changed, we need to reset.
- */
- if (!(netdev->features & NETIF_F_NTUPLE)) {
- if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
- /* turn off Flow Director, set ATR and reset */
- if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
- !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
- adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
- need_reset = true;
- }
- adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
- } else if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
- /* turn off ATR, enable perfect filters and reset */
- adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
- adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
- need_reset = true;
- }
-
-#endif /* ETHTOOL_GRXRINGS */
- if (need_reset)
- ixgbe_do_reset(netdev);
-
- return 0;
-}
-
-#endif /* ETHTOOL_GFLAGS */
-#endif /* HAVE_NDO_SET_FEATURES */
-#ifdef ETHTOOL_GRXRINGS
-static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
- struct ethtool_rxnfc *cmd)
-{
- union ixgbe_atr_input *mask = &adapter->fdir_mask;
- struct ethtool_rx_flow_spec *fsp =
- (struct ethtool_rx_flow_spec *)&cmd->fs;
- struct hlist_node *node, *node2;
- struct ixgbe_fdir_filter *rule = NULL;
-
- /* report total rule count */
- cmd->data = (1024 << adapter->fdir_pballoc) - 2;
-
- hlist_for_each_entry_safe(rule, node, node2,
- &adapter->fdir_filter_list, fdir_node) {
- if (fsp->location <= rule->sw_idx)
- break;
- }
-
- if (!rule || fsp->location != rule->sw_idx)
- return -EINVAL;
-
- /* fill out the flow spec entry */
-
- /* set flow type field */
- switch (rule->filter.formatted.flow_type) {
- case IXGBE_ATR_FLOW_TYPE_TCPV4:
- fsp->flow_type = TCP_V4_FLOW;
- break;
- case IXGBE_ATR_FLOW_TYPE_UDPV4:
- fsp->flow_type = UDP_V4_FLOW;
- break;
- case IXGBE_ATR_FLOW_TYPE_SCTPV4:
- fsp->flow_type = SCTP_V4_FLOW;
- break;
- case IXGBE_ATR_FLOW_TYPE_IPV4:
- fsp->flow_type = IP_USER_FLOW;
- fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
- fsp->h_u.usr_ip4_spec.proto = 0;
- fsp->m_u.usr_ip4_spec.proto = 0;
- break;
- default:
- return -EINVAL;
- }
-
- fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
- fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
- fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
- fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
- fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
- fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
- fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
- fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
- fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
- fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
- fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
- fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
- fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
- fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
- fsp->flow_type |= FLOW_EXT;
-
- /* record action */
- if (rule->action == IXGBE_FDIR_DROP_QUEUE)
- fsp->ring_cookie = RX_CLS_FLOW_DISC;
- else
- fsp->ring_cookie = rule->action;
-
- return 0;
-}
-
-static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
- struct ethtool_rxnfc *cmd,
- u32 *rule_locs)
-{
- struct hlist_node *node, *node2;
- struct ixgbe_fdir_filter *rule;
- int cnt = 0;
-
- /* report total rule count */
- cmd->data = (1024 << adapter->fdir_pballoc) - 2;
-
- hlist_for_each_entry_safe(rule, node, node2,
- &adapter->fdir_filter_list, fdir_node) {
- if (cnt == cmd->rule_cnt)
- return -EMSGSIZE;
- rule_locs[cnt] = rule->sw_idx;
- cnt++;
- }
-
- cmd->rule_cnt = cnt;
-
- return 0;
-}
-
-static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter,
- struct ethtool_rxnfc *cmd)
-{
- cmd->data = 0;
-
- /* if RSS is disabled then report no hashing */
- if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
- return 0;
-
- /* Report default options for RSS on ixgbe */
- switch (cmd->flow_type) {
- case TCP_V4_FLOW:
- cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
- case UDP_V4_FLOW:
- if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
- cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
- case SCTP_V4_FLOW:
- case AH_ESP_V4_FLOW:
- case AH_V4_FLOW:
- case ESP_V4_FLOW:
- case IPV4_FLOW:
- cmd->data |= RXH_IP_SRC | RXH_IP_DST;
- break;
- case TCP_V6_FLOW:
- cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
- case UDP_V6_FLOW:
- if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
- cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
- case SCTP_V6_FLOW:
- case AH_ESP_V6_FLOW:
- case AH_V6_FLOW:
- case ESP_V6_FLOW:
- case IPV6_FLOW:
- cmd->data |= RXH_IP_SRC | RXH_IP_DST;
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
-#ifdef HAVE_ETHTOOL_GET_RXNFC_VOID_RULE_LOCS
- void *rule_locs)
-#else
- u32 *rule_locs)
-#endif
-{
- struct ixgbe_adapter *adapter = netdev_priv(dev);
- int ret = -EOPNOTSUPP;
-
- switch (cmd->cmd) {
- case ETHTOOL_GRXRINGS:
- cmd->data = adapter->num_rx_queues;
- ret = 0;
- break;
- case ETHTOOL_GRXCLSRLCNT:
- cmd->rule_cnt = adapter->fdir_filter_count;
- ret = 0;
- break;
- case ETHTOOL_GRXCLSRULE:
- ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
- break;
- case ETHTOOL_GRXCLSRLALL:
- ret = ixgbe_get_ethtool_fdir_all(adapter, cmd,
- rule_locs);
- break;
- case ETHTOOL_GRXFH:
- ret = ixgbe_get_rss_hash_opts(adapter, cmd);
- break;
- default:
- break;
- }
-
- return ret;
-}
-
-static int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
- struct ixgbe_fdir_filter *input,
- u16 sw_idx)
-{
- struct ixgbe_hw *hw = &adapter->hw;
- struct hlist_node *node, *node2, *parent;
- struct ixgbe_fdir_filter *rule;
- int err = -EINVAL;
-
- parent = NULL;
- rule = NULL;
-
- hlist_for_each_entry_safe(rule, node, node2,
- &adapter->fdir_filter_list, fdir_node) {
- /* hash found, or no matching entry */
- if (rule->sw_idx >= sw_idx)
- break;
- parent = node;
- }
-
- /* if there is an old rule occupying our place remove it */
- if (rule && (rule->sw_idx == sw_idx)) {
- if (!input || (rule->filter.formatted.bkt_hash !=
- input->filter.formatted.bkt_hash)) {
- err = ixgbe_fdir_erase_perfect_filter_82599(hw,
- &rule->filter,
- sw_idx);
- }
-
- hlist_del(&rule->fdir_node);
- kfree(rule);
- adapter->fdir_filter_count--;
- }
-
- /*
- * If no input this was a delete, err should be 0 if a rule was
- * successfully found and removed from the list else -EINVAL
- */
- if (!input)
- return err;
-
- /* initialize node and set software index */
- INIT_HLIST_NODE(&input->fdir_node);
-
- /* add filter to the list */
- if (parent)
- hlist_add_after(parent, &input->fdir_node);
- else
- hlist_add_head(&input->fdir_node,
- &adapter->fdir_filter_list);
-
- /* update counts */
- adapter->fdir_filter_count++;
-
- return 0;
-}
-
-static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
- u8 *flow_type)
-{
- switch (fsp->flow_type & ~FLOW_EXT) {
- case TCP_V4_FLOW:
- *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
- break;
- case UDP_V4_FLOW:
- *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
- break;
- case SCTP_V4_FLOW:
- *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
- break;
- case IP_USER_FLOW:
- switch (fsp->h_u.usr_ip4_spec.proto) {
- case IPPROTO_TCP:
- *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
- break;
- case IPPROTO_UDP:
- *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
- break;
- case IPPROTO_SCTP:
- *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
- break;
- case 0:
- if (!fsp->m_u.usr_ip4_spec.proto) {
- *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
- break;
- }
- default:
- return 0;
- }
- break;
- default:
- return 0;
- }
-
- return 1;
-}
-
-static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
- struct ethtool_rxnfc *cmd)
-{
- struct ethtool_rx_flow_spec *fsp =
- (struct ethtool_rx_flow_spec *)&cmd->fs;
- struct ixgbe_hw *hw = &adapter->hw;
- struct ixgbe_fdir_filter *input;
- union ixgbe_atr_input mask;
- int err;
-
- if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
- return -EOPNOTSUPP;
-
- /*
- * Don't allow programming if the action is a queue greater than
- * the number of online Rx queues.
- */
- if ((fsp->ring_cookie != RX_CLS_FLOW_DISC) &&
- (fsp->ring_cookie >= adapter->num_rx_queues))
- return -EINVAL;
-
- /* Don't allow indexes to exist outside of available space */
- if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
- e_err(drv, "Location out of range\n");
- return -EINVAL;
- }
-
- input = kzalloc(sizeof(*input), GFP_ATOMIC);
- if (!input)
- return -ENOMEM;
-
- memset(&mask, 0, sizeof(union ixgbe_atr_input));
-
- /* set SW index */
- input->sw_idx = fsp->location;
-
- /* record flow type */
- if (!ixgbe_flowspec_to_flow_type(fsp,
- &input->filter.formatted.flow_type)) {
- e_err(drv, "Unrecognized flow type\n");
- goto err_out;
- }
-
- mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
- IXGBE_ATR_L4TYPE_MASK;
-
- if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
- mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
-
- /* Copy input into formatted structures */
- input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
- mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
- input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
- mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
- input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
- mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
- input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
- mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
-
- if (fsp->flow_type & FLOW_EXT) {
- input->filter.formatted.vm_pool =
- (unsigned char)ntohl(fsp->h_ext.data[1]);
- mask.formatted.vm_pool =
- (unsigned char)ntohl(fsp->m_ext.data[1]);
- input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
- mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
- input->filter.formatted.flex_bytes =
- fsp->h_ext.vlan_etype;
- mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
- }
-
- /* determine if we need to drop or route the packet */
- if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
- input->action = IXGBE_FDIR_DROP_QUEUE;
- else
- input->action = fsp->ring_cookie;
-
- spin_lock(&adapter->fdir_perfect_lock);
-
- if (hlist_empty(&adapter->fdir_filter_list)) {
- /* save mask and program input mask into HW */
- memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
- err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
- if (err) {
- e_err(drv, "Error writing mask\n");
- goto err_out_w_lock;
- }
- } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
- e_err(drv, "Only one mask supported per port\n");
- goto err_out_w_lock;
- }
-
- /* apply mask and compute/store hash */
- ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
-
- /* program filters to filter memory */
- err = ixgbe_fdir_write_perfect_filter_82599(hw,
- &input->filter, input->sw_idx,
- (input->action == IXGBE_FDIR_DROP_QUEUE) ?
- IXGBE_FDIR_DROP_QUEUE :
- adapter->rx_ring[input->action]->reg_idx);
- if (err)
- goto err_out_w_lock;
-
- ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
-
- spin_unlock(&adapter->fdir_perfect_lock);
-
- kfree(input);
- return err;
-err_out_w_lock:
- spin_unlock(&adapter->fdir_perfect_lock);
-err_out:
- kfree(input);
- return -EINVAL;
-}
-
-static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
- struct ethtool_rxnfc *cmd)
-{
- struct ethtool_rx_flow_spec *fsp =
- (struct ethtool_rx_flow_spec *)&cmd->fs;
- int err;
-
- spin_lock(&adapter->fdir_perfect_lock);
- err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, (u16)(fsp->location));
- spin_unlock(&adapter->fdir_perfect_lock);
-
- return err;
-}
-
-#ifdef ETHTOOL_SRXNTUPLE
-/*
- * We need to keep this around for kernels 2.6.33 - 2.6.39 in order to avoid
- * a null pointer dereference as it was assumend if the NETIF_F_NTUPLE flag
- * was defined that this function was present.
- */
-static int ixgbe_set_rx_ntuple(struct net_device *dev,
- struct ethtool_rx_ntuple *cmd)
-{
- return -EOPNOTSUPP;
-}
-
-#endif
-#define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \
- IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
-static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter,
- struct ethtool_rxnfc *nfc)
-{
- u32 flags2 = adapter->flags2;
-
- /*
- * RSS does not support anything other than hashing
- * to queues on src and dst IPs and ports
- */
- if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
- RXH_L4_B_0_1 | RXH_L4_B_2_3))
- return -EINVAL;
-
- switch (nfc->flow_type) {
- case TCP_V4_FLOW:
- case TCP_V6_FLOW:
- if (!(nfc->data & RXH_IP_SRC) ||
- !(nfc->data & RXH_IP_DST) ||
- !(nfc->data & RXH_L4_B_0_1) ||
- !(nfc->data & RXH_L4_B_2_3))
- return -EINVAL;
- break;
- case UDP_V4_FLOW:
- if (!(nfc->data & RXH_IP_SRC) ||
- !(nfc->data & RXH_IP_DST))
- return -EINVAL;
- switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
- case 0:
- flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
- break;
- case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
- flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
- break;
- default:
- return -EINVAL;
- }
- break;
- case UDP_V6_FLOW:
- if (!(nfc->data & RXH_IP_SRC) ||
- !(nfc->data & RXH_IP_DST))
- return -EINVAL;
- switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
- case 0:
- flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
- break;
- case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
- flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
- break;
- default:
- return -EINVAL;
- }
- break;
- case AH_ESP_V4_FLOW:
- case AH_V4_FLOW:
- case ESP_V4_FLOW:
- case SCTP_V4_FLOW:
- case AH_ESP_V6_FLOW:
- case AH_V6_FLOW:
- case ESP_V6_FLOW:
- case SCTP_V6_FLOW:
- if (!(nfc->data & RXH_IP_SRC) ||
- !(nfc->data & RXH_IP_DST) ||
- (nfc->data & RXH_L4_B_0_1) ||
- (nfc->data & RXH_L4_B_2_3))
- return -EINVAL;
- break;
- default:
- return -EINVAL;
- }
-
- /* if we changed something we need to update flags */
- if (flags2 != adapter->flags2) {
- struct ixgbe_hw *hw = &adapter->hw;
- u32 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
-
- if ((flags2 & UDP_RSS_FLAGS) &&
- !(adapter->flags2 & UDP_RSS_FLAGS))
- e_warn(drv, "enabling UDP RSS: fragmented packets"
- " may arrive out of order to the stack above\n");
-
- adapter->flags2 = flags2;
-
- /* Perform hash on these packet types */
- mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
- | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
- | IXGBE_MRQC_RSS_FIELD_IPV6
- | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
-
- mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
- IXGBE_MRQC_RSS_FIELD_IPV6_UDP);
-
- if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
- mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
-
- if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
- mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
-
- IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
- }
-
- return 0;
-}
-
-static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
-{
- struct ixgbe_adapter *adapter = netdev_priv(dev);
- int ret = -EOPNOTSUPP;
-
- switch (cmd->cmd) {
- case ETHTOOL_SRXCLSRLINS:
- ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
- break;
- case ETHTOOL_SRXCLSRLDEL:
- ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
- break;
- case ETHTOOL_SRXFH:
- ret = ixgbe_set_rss_hash_opt(adapter, cmd);
- break;
- default:
- break;
- }
-
- return ret;
-}
-
-#endif /* ETHTOOL_GRXRINGS */
-//static
-struct ethtool_ops ixgbe_ethtool_ops = {
-#ifndef ETHTOOL_GLINKSETTINGS
- .get_settings = ixgbe_get_settings,
-#endif
-#ifndef ETHTOOL_SLINKSETTINGS
- .set_settings = ixgbe_set_settings,
-#endif
- .get_drvinfo = ixgbe_get_drvinfo,
- .get_regs_len = ixgbe_get_regs_len,
- .get_regs = ixgbe_get_regs,
- .get_wol = ixgbe_get_wol,
- .set_wol = ixgbe_set_wol,
- .nway_reset = ixgbe_nway_reset,
- .get_link = ethtool_op_get_link,
- .get_eeprom_len = ixgbe_get_eeprom_len,
- .get_eeprom = ixgbe_get_eeprom,
- .set_eeprom = ixgbe_set_eeprom,
- .get_ringparam = ixgbe_get_ringparam,
- .set_ringparam = ixgbe_set_ringparam,
- .get_pauseparam = ixgbe_get_pauseparam,
- .set_pauseparam = ixgbe_set_pauseparam,
- .get_msglevel = ixgbe_get_msglevel,
- .set_msglevel = ixgbe_set_msglevel,
-#ifndef HAVE_ETHTOOL_GET_SSET_COUNT
- .self_test_count = ixgbe_diag_test_count,
-#endif /* HAVE_ETHTOOL_GET_SSET_COUNT */
- .self_test = ixgbe_diag_test,
- .get_strings = ixgbe_get_strings,
-#ifdef HAVE_ETHTOOL_SET_PHYS_ID
- .set_phys_id = ixgbe_set_phys_id,
-#else
- .phys_id = ixgbe_phys_id,
-#endif /* HAVE_ETHTOOL_SET_PHYS_ID */
-#ifndef HAVE_ETHTOOL_GET_SSET_COUNT
- .get_stats_count = ixgbe_get_stats_count,
-#else /* HAVE_ETHTOOL_GET_SSET_COUNT */
- .get_sset_count = ixgbe_get_sset_count,
-#endif /* HAVE_ETHTOOL_GET_SSET_COUNT */
- .get_ethtool_stats = ixgbe_get_ethtool_stats,
-#ifdef HAVE_ETHTOOL_GET_PERM_ADDR
- .get_perm_addr = ethtool_op_get_perm_addr,
-#endif
- .get_coalesce = ixgbe_get_coalesce,
- .set_coalesce = ixgbe_set_coalesce,
-#ifndef HAVE_NDO_SET_FEATURES
- .get_rx_csum = ixgbe_get_rx_csum,
- .set_rx_csum = ixgbe_set_rx_csum,
- .get_tx_csum = ixgbe_get_tx_csum,
- .set_tx_csum = ixgbe_set_tx_csum,
- .get_sg = ethtool_op_get_sg,
- .set_sg = ethtool_op_set_sg,
-#ifdef NETIF_F_TSO
- .get_tso = ethtool_op_get_tso,
- .set_tso = ixgbe_set_tso,
-#endif
-#ifdef ETHTOOL_GFLAGS
- .get_flags = ethtool_op_get_flags,
- .set_flags = ixgbe_set_flags,
-#endif
-#endif /* HAVE_NDO_SET_FEATURES */
-#ifdef ETHTOOL_GRXRINGS
- .get_rxnfc = ixgbe_get_rxnfc,
- .set_rxnfc = ixgbe_set_rxnfc,
-#ifdef ETHTOOL_SRXNTUPLE
- .set_rx_ntuple = ixgbe_set_rx_ntuple,
-#endif
-#endif
-};
-
-void ixgbe_set_ethtool_ops(struct net_device *netdev)
-{
- SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
-}
-#endif /* SIOCETHTOOL */
diff --git a/kernel/linux/kni/ethtool/ixgbe/ixgbe_fcoe.h b/kernel/linux/kni/ethtool/ixgbe/ixgbe_fcoe.h
deleted file mode 100644
index eec86cb..0000000
--- a/kernel/linux/kni/ethtool/ixgbe/ixgbe_fcoe.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*******************************************************************************
-
- Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2012 Intel Corporation.
-
- Contact Information:
- e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
- Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-
-#ifndef _IXGBE_FCOE_H
-#define _IXGBE_FCOE_H
-
-#ifdef IXGBE_FCOE
-
-#include <scsi/fc/fc_fs.h>
-#include <scsi/fc/fc_fcoe.h>
-
-/* shift bits within STAT fo FCSTAT */
-#define IXGBE_RXDADV_FCSTAT_SHIFT 4
-
-/* ddp user buffer */
-#define IXGBE_BUFFCNT_MAX 256 /* 8 bits bufcnt */
-#define IXGBE_FCPTR_ALIGN 16
-#define IXGBE_FCPTR_MAX (IXGBE_BUFFCNT_MAX * sizeof(dma_addr_t))
-#define IXGBE_FCBUFF_4KB 0x0
-#define IXGBE_FCBUFF_8KB 0x1
-#define IXGBE_FCBUFF_16KB 0x2
-#define IXGBE_FCBUFF_64KB 0x3
-#define IXGBE_FCBUFF_MAX 65536 /* 64KB max */
-#define IXGBE_FCBUFF_MIN 4096 /* 4KB min */
-#define IXGBE_FCOE_DDP_MAX 512 /* 9 bits xid */
-
-/* Default traffic class to use for FCoE */
-#define IXGBE_FCOE_DEFTC 3
-
-/* fcerr */
-#define IXGBE_FCERR_BADCRC 0x00100000
-#define IXGBE_FCERR_EOFSOF 0x00200000
-#define IXGBE_FCERR_NOFIRST 0x00300000
-#define IXGBE_FCERR_OOOSEQ 0x00400000
-#define IXGBE_FCERR_NODMA 0x00500000
-#define IXGBE_FCERR_PKTLOST 0x00600000
-
-/* FCoE DDP for target mode */
-#define __IXGBE_FCOE_TARGET 1
-
-struct ixgbe_fcoe_ddp {
- int len;
- u32 err;
- unsigned int sgc;
- struct scatterlist *sgl;
- dma_addr_t udp;
- u64 *udl;
- struct pci_pool *pool;
-};
-
-struct ixgbe_fcoe {
- struct pci_pool **pool;
- atomic_t refcnt;
- spinlock_t lock;
- struct ixgbe_fcoe_ddp ddp[IXGBE_FCOE_DDP_MAX];
- unsigned char *extra_ddp_buffer;
- dma_addr_t extra_ddp_buffer_dma;
- u64 __percpu *pcpu_noddp;
- u64 __percpu *pcpu_noddp_ext_buff;
- unsigned long mode;
- u8 tc;
- u8 up;
- u8 up_set;
-};
-#endif /* IXGBE_FCOE */
-
-#endif /* _IXGBE_FCOE_H */
diff --git a/kernel/linux/kni/ethtool/ixgbe/ixgbe_main.c b/kernel/linux/kni/ethtool/ixgbe/ixgbe_main.c
deleted file mode 100644
index a5acf19..0000000
--- a/kernel/linux/kni/ethtool/ixgbe/ixgbe_main.c
+++ /dev/null
@@ -1,2951 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*******************************************************************************
-
- Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2012 Intel Corporation.
-
- Contact Information:
- e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
- Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-
-/******************************************************************************
- Copyright (c)2006 - 2007 Myricom, Inc. for some LRO specific code
-******************************************************************************/
-#include <linux/types.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <linux/netdevice.h>
-#include <linux/vmalloc.h>
-#include <linux/highmem.h>
-#include <linux/string.h>
-#include <linux/in.h>
-#include <linux/ip.h>
-#include <linux/tcp.h>
-#ifdef HAVE_SCTP
-#include <linux/sctp.h>
-#endif
-#include <linux/pkt_sched.h>
-#include <linux/ipv6.h>
-#ifdef NETIF_F_TSO
-#include <net/checksum.h>
-#ifdef NETIF_F_TSO6
-#include <net/ip6_checksum.h>
-#endif
-#endif
-#ifdef SIOCETHTOOL
-#include <linux/ethtool.h>
-#endif
-
-#include "ixgbe.h"
-
-#undef CONFIG_DCA
-#undef CONFIG_DCA_MODULE
-
-char ixgbe_driver_name[] = "ixgbe";
-#define DRV_HW_PERF
-
-#ifndef CONFIG_IXGBE_NAPI
-#define DRIVERNAPI
-#else
-#define DRIVERNAPI "-NAPI"
-#endif
-
-#define FPGA
-
-#define VMDQ_TAG
-
-#define MAJ 3
-#define MIN 9
-#define BUILD 17
-#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
- __stringify(BUILD) DRIVERNAPI DRV_HW_PERF FPGA VMDQ_TAG
-const char ixgbe_driver_version[] = DRV_VERSION;
-
-/* ixgbe_pci_tbl - PCI Device ID Table
- *
- * Wildcard entries (PCI_ANY_ID) should come last
- * Last entry must be all 0s
- *
- * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
- * Class, Class Mask, private data (not used) }
- */
-const struct pci_device_id ixgbe_pci_tbl[] = {
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP)},
- {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP)},
- /* required last entry */
- {0, }
-};
-
-#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
-static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
- void *p);
-static struct notifier_block dca_notifier = {
- .notifier_call = ixgbe_notify_dca,
- .next = NULL,
- .priority = 0
-};
-
-#endif
-MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
-MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
-MODULE_LICENSE("GPL");
-MODULE_VERSION(DRV_VERSION);
-
-#define DEFAULT_DEBUG_LEVEL_SHIFT 3
-
-
-static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
-{
- u32 ctrl_ext;
-
- /* Let firmware take over control of h/w */
- ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
- IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
- ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
-}
-
-#ifdef NO_VNIC
-static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
-{
- u32 ctrl_ext;
-
- /* Let firmware know the driver has taken over */
- ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
- IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
- ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
-}
-#endif
-
-
-static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
-{
- struct ixgbe_hw *hw = &adapter->hw;
- struct ixgbe_hw_stats *hwstats = &adapter->stats;
- int i;
- u32 data;
-
- if ((hw->fc.current_mode != ixgbe_fc_full) &&
- (hw->fc.current_mode != ixgbe_fc_rx_pause))
- return;
-
- switch (hw->mac.type) {
- case ixgbe_mac_82598EB:
- data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
- break;
- default:
- data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
- }
- hwstats->lxoffrxc += data;
-
- /* refill credits (no tx hang) if we received xoff */
- if (!data)
- return;
-
- for (i = 0; i < adapter->num_tx_queues; i++)
- clear_bit(__IXGBE_HANG_CHECK_ARMED,
- &adapter->tx_ring[i]->state);
-}
-
-static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
-{
- struct ixgbe_hw *hw = &adapter->hw;
- struct ixgbe_hw_stats *hwstats = &adapter->stats;
- u32 xoff[8] = {0};
- int i;
- bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
-
-#ifdef HAVE_DCBNL_IEEE
- if (adapter->ixgbe_ieee_pfc)
- pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
-
-#endif
- if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
- ixgbe_update_xoff_rx_lfc(adapter);
- return;
- }
-
- /* update stats for each tc, only valid with PFC enabled */
- for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
- switch (hw->mac.type) {
- case ixgbe_mac_82598EB:
- xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
- break;
- default:
- xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
- }
- hwstats->pxoffrxc[i] += xoff[i];
- }
-
- /* disarm tx queues that have received xoff frames */
- for (i = 0; i < adapter->num_tx_queues; i++) {
- struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
- u8 tc = tx_ring->dcb_tc;
-
- if ((tc <= 7) && (xoff[tc]))
- clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
- }
-}
-
-
-
-
-#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
-
-
-
-
-#ifdef HAVE_8021P_SUPPORT
-/**
- * ixgbe_vlan_stripping_disable - helper to disable vlan tag stripping
- * @adapter: driver data
- */
-void ixgbe_vlan_stripping_disable(struct ixgbe_adapter *adapter)
-{
- struct ixgbe_hw *hw = &adapter->hw;
- u32 vlnctrl;
- int i;
-
- /* leave vlan tag stripping enabled for DCB */
- if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
- return;
-
- switch (hw->mac.type) {
- case ixgbe_mac_82598EB:
- vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
- vlnctrl &= ~IXGBE_VLNCTRL_VME;
- IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
- break;
- case ixgbe_mac_82599EB:
- case ixgbe_mac_X540:
- for (i = 0; i < adapter->num_rx_queues; i++) {
- u8 reg_idx = adapter->rx_ring[i]->reg_idx;
- vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
- vlnctrl &= ~IXGBE_RXDCTL_VME;
- IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), vlnctrl);
- }
- break;
- default:
- break;
- }
-}
-
-#endif
-/**
- * ixgbe_vlan_stripping_enable - helper to enable vlan tag stripping
- * @adapter: driver data
- */
-void ixgbe_vlan_stripping_enable(struct ixgbe_adapter *adapter)
-{
- struct ixgbe_hw *hw = &adapter->hw;
- u32 vlnctrl;
- int i;
-
- switch (hw->mac.type) {
- case ixgbe_mac_82598EB:
- vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
- vlnctrl |= IXGBE_VLNCTRL_VME;
- IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
- break;
- case ixgbe_mac_82599EB:
- case ixgbe_mac_X540:
- for (i = 0; i < adapter->num_rx_queues; i++) {
- u8 reg_idx = adapter->rx_ring[i]->reg_idx;
- vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
- vlnctrl |= IXGBE_RXDCTL_VME;
- IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), vlnctrl);
- }
- break;
- default:
- break;
- }
-}
-
-#ifdef HAVE_VLAN_RX_REGISTER
-void ixgbe_vlan_mode(struct net_device *netdev, struct vlan_group *grp)
-#else
-void ixgbe_vlan_mode(struct net_device *netdev, u32 features)
-#endif
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
-#ifdef HAVE_8021P_SUPPORT
- bool enable;
-#endif
-#ifdef HAVE_VLAN_RX_REGISTER
-
- //if (!test_bit(__IXGBE_DOWN, &adapter->state))
- // ixgbe_irq_disable(adapter);
-
- adapter->vlgrp = grp;
-
- //if (!test_bit(__IXGBE_DOWN, &adapter->state))
- // ixgbe_irq_enable(adapter, true, true);
-#endif
-#ifdef HAVE_8021P_SUPPORT
-#ifdef HAVE_VLAN_RX_REGISTER
- enable = (grp || (adapter->flags & IXGBE_FLAG_DCB_ENABLED));
-#else
- enable = !!(features & NETIF_F_HW_VLAN_RX);
-#endif
- if (enable)
- /* enable VLAN tag insert/strip */
- ixgbe_vlan_stripping_enable(adapter);
- else
- /* disable VLAN tag insert/strip */
- ixgbe_vlan_stripping_disable(adapter);
-
-#endif
-}
-
-static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
-{
-#ifdef NETDEV_HW_ADDR_T_MULTICAST
- struct netdev_hw_addr *mc_ptr;
-#else
- struct dev_mc_list *mc_ptr;
-#endif
- struct ixgbe_adapter *adapter = hw->back;
- u8 *addr = *mc_addr_ptr;
-
- *vmdq = adapter->num_vfs;
-
-#ifdef NETDEV_HW_ADDR_T_MULTICAST
- mc_ptr = container_of(addr, struct netdev_hw_addr, addr[0]);
- if (mc_ptr->list.next) {
- struct netdev_hw_addr *ha;
-
- ha = list_entry(mc_ptr->list.next, struct netdev_hw_addr, list);
- *mc_addr_ptr = ha->addr;
- }
-#else
- mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
- if (mc_ptr->next)
- *mc_addr_ptr = mc_ptr->next->dmi_addr;
-#endif
- else
- *mc_addr_ptr = NULL;
-
- return addr;
-}
-
-/**
- * ixgbe_write_mc_addr_list - write multicast addresses to MTA
- * @netdev: network interface device structure
- *
- * Writes multicast address list to the MTA hash table.
- * Returns: -ENOMEM on failure
- * 0 on no addresses written
- * X on writing X addresses to MTA
- **/
-int ixgbe_write_mc_addr_list(struct net_device *netdev)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- struct ixgbe_hw *hw = &adapter->hw;
-#ifdef NETDEV_HW_ADDR_T_MULTICAST
- struct netdev_hw_addr *ha;
-#endif
- u8 *addr_list = NULL;
- int addr_count = 0;
-
- if (!hw->mac.ops.update_mc_addr_list)
- return -ENOMEM;
-
- if (!netif_running(netdev))
- return 0;
-
-
- hw->mac.ops.update_mc_addr_list(hw, NULL, 0,
- ixgbe_addr_list_itr, true);
-
- if (!netdev_mc_empty(netdev)) {
-#ifdef NETDEV_HW_ADDR_T_MULTICAST
- ha = list_first_entry(&netdev->mc.list,
- struct netdev_hw_addr, list);
- addr_list = ha->addr;
-#else
- addr_list = netdev->mc_list->dmi_addr;
-#endif
- addr_count = netdev_mc_count(netdev);
-
- hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
- ixgbe_addr_list_itr, false);
- }
-
-#ifdef CONFIG_PCI_IOV
- //ixgbe_restore_vf_multicasts(adapter);
-#endif
- return addr_count;
-}
-
-
-void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
-{
- struct ixgbe_hw *hw = &adapter->hw;
- int i;
- for (i = 0; i < hw->mac.num_rar_entries; i++) {
- if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE) {
- hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,
- adapter->mac_table[i].queue,
- IXGBE_RAH_AV);
- } else {
- hw->mac.ops.clear_rar(hw, i);
- }
- }
-}
-
-void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
-{
- struct ixgbe_hw *hw = &adapter->hw;
- int i;
- for (i = 0; i < hw->mac.num_rar_entries; i++) {
- if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {
- if (adapter->mac_table[i].state &
- IXGBE_MAC_STATE_IN_USE) {
- hw->mac.ops.set_rar(hw, i,
- adapter->mac_table[i].addr,
- adapter->mac_table[i].queue,
- IXGBE_RAH_AV);
- } else {
- hw->mac.ops.clear_rar(hw, i);
- }
- adapter->mac_table[i].state &=
- ~(IXGBE_MAC_STATE_MODIFIED);
- }
- }
-}
-
-int ixgbe_available_rars(struct ixgbe_adapter *adapter)
-{
- struct ixgbe_hw *hw = &adapter->hw;
- int i, count = 0;
-
- for (i = 0; i < hw->mac.num_rar_entries; i++) {
- if (adapter->mac_table[i].state == 0)
- count++;
- }
- return count;
-}
-
-int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
-{
- struct ixgbe_hw *hw = &adapter->hw;
- int i;
-
- if (is_zero_ether_addr(addr))
- return 0;
-
- for (i = 0; i < hw->mac.num_rar_entries; i++) {
- if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
- continue;
- adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |
- IXGBE_MAC_STATE_IN_USE);
- memcpy(adapter->mac_table[i].addr, addr, ETH_ALEN);
- adapter->mac_table[i].queue = queue;
- ixgbe_sync_mac_table(adapter);
- return i;
- }
- return -ENOMEM;
-}
-
-void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
-{
- int i;
- struct ixgbe_hw *hw = &adapter->hw;
-
- for (i = 0; i < hw->mac.num_rar_entries; i++) {
- adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
- adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
- memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
- adapter->mac_table[i].queue = 0;
- }
- ixgbe_sync_mac_table(adapter);
-}
-
-void ixgbe_del_mac_filter_by_index(struct ixgbe_adapter *adapter, int index)
-{
- adapter->mac_table[index].state |= IXGBE_MAC_STATE_MODIFIED;
- adapter->mac_table[index].state &= ~IXGBE_MAC_STATE_IN_USE;
- memset(adapter->mac_table[index].addr, 0, ETH_ALEN);
- adapter->mac_table[index].queue = 0;
- ixgbe_sync_mac_table(adapter);
-}
-
-int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8* addr, u16 queue)
-{
- /* search table for addr, if found, set to 0 and sync */
- int i;
- struct ixgbe_hw *hw = &adapter->hw;
-
- if (is_zero_ether_addr(addr))
- return 0;
- for (i = 0; i < hw->mac.num_rar_entries; i++) {
- if (ether_addr_equal(addr, adapter->mac_table[i].addr) &&
- adapter->mac_table[i].queue == queue) {
- adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
- adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
- memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
- adapter->mac_table[i].queue = 0;
- ixgbe_sync_mac_table(adapter);
- return 0;
- }
- }
- return -ENOMEM;
-}
-#ifdef HAVE_SET_RX_MODE
-/**
- * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
- * @netdev: network interface device structure
- *
- * Writes unicast address list to the RAR table.
- * Returns: -ENOMEM on failure/insufficient address space
- * 0 on no addresses written
- * X on writing X addresses to the RAR table
- **/
-int ixgbe_write_uc_addr_list(struct ixgbe_adapter *adapter,
- struct net_device *netdev, unsigned int vfn)
-{
- int count = 0;
-
- /* return ENOMEM indicating insufficient memory for addresses */
- if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))
- return -ENOMEM;
-
- if (!netdev_uc_empty(netdev)) {
-#ifdef NETDEV_HW_ADDR_T_UNICAST
- struct netdev_hw_addr *ha;
-#else
- struct dev_mc_list *ha;
-#endif
- netdev_for_each_uc_addr(ha, netdev) {
-#ifdef NETDEV_HW_ADDR_T_UNICAST
- ixgbe_del_mac_filter(adapter, ha->addr, (u16)vfn);
- ixgbe_add_mac_filter(adapter, ha->addr, (u16)vfn);
-#else
- ixgbe_del_mac_filter(adapter, ha->da_addr, (u16)vfn);
- ixgbe_add_mac_filter(adapter, ha->da_addr, (u16)vfn);
-#endif
- count++;
- }
- }
- return count;
-}
-
-#endif
-/**
- * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
- * @netdev: network interface device structure
- *
- * The set_rx_method entry point is called whenever the unicast/multicast
- * address list or the network interface flags are updated. This routine is
- * responsible for configuring the hardware for proper unicast, multicast and
- * promiscuous mode.
- **/
-void ixgbe_set_rx_mode(struct net_device *netdev)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- struct ixgbe_hw *hw = &adapter->hw;
- u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
- u32 vlnctrl;
- int count;
-
- /* Check for Promiscuous and All Multicast modes */
- fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
- vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
-
- /* set all bits that we expect to always be set */
- fctrl |= IXGBE_FCTRL_BAM;
- fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
- fctrl |= IXGBE_FCTRL_PMCF;
-
- /* clear the bits we are changing the status of */
- fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
- vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
-
- if (netdev->flags & IFF_PROMISC) {
- hw->addr_ctrl.user_set_promisc = true;
- fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
- vmolr |= IXGBE_VMOLR_MPE;
- } else {
- if (netdev->flags & IFF_ALLMULTI) {
- fctrl |= IXGBE_FCTRL_MPE;
- vmolr |= IXGBE_VMOLR_MPE;
- } else {
- /*
- * Write addresses to the MTA, if the attempt fails
- * then we should just turn on promiscuous mode so
- * that we can at least receive multicast traffic
- */
- count = ixgbe_write_mc_addr_list(netdev);
- if (count < 0) {
- fctrl |= IXGBE_FCTRL_MPE;
- vmolr |= IXGBE_VMOLR_MPE;
- } else if (count) {
- vmolr |= IXGBE_VMOLR_ROMPE;
- }
- }
-#ifdef NETIF_F_HW_VLAN_TX
- /* enable hardware vlan filtering */
- vlnctrl |= IXGBE_VLNCTRL_VFE;
-#endif
- hw->addr_ctrl.user_set_promisc = false;
-#ifdef HAVE_SET_RX_MODE
- /*
- * Write addresses to available RAR registers, if there is not
- * sufficient space to store all the addresses then enable
- * unicast promiscuous mode
- */
- count = ixgbe_write_uc_addr_list(adapter, netdev,
- adapter->num_vfs);
- if (count < 0) {
- fctrl |= IXGBE_FCTRL_UPE;
- vmolr |= IXGBE_VMOLR_ROPE;
- }
-#endif
- }
-
- if (hw->mac.type != ixgbe_mac_82598EB) {
- vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
- ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
- IXGBE_VMOLR_ROPE);
- IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
- }
-
- IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
- IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
-}
-
-
-
-
-
-
-
-
-/* Additional bittime to account for IXGBE framing */
-#define IXGBE_ETH_FRAMING 20
-
-/*
- * ixgbe_hpbthresh - calculate high water mark for flow control
- *
- * @adapter: board private structure to calculate for
- * @pb - packet buffer to calculate
- */
-static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
-{
- struct ixgbe_hw *hw = &adapter->hw;
- struct net_device *dev = adapter->netdev;
- int link, tc, kb, marker;
- u32 dv_id, rx_pba;
-
- /* Calculate max LAN frame size */
- tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
-
-#ifdef IXGBE_FCOE
- /* FCoE traffic class uses FCOE jumbo frames */
- if (dev->features & NETIF_F_FCOE_MTU) {
- int fcoe_pb = 0;
-
- fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
-
- if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
- tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
- }
-#endif
-
- /* Calculate delay value for device */
- switch (hw->mac.type) {
- case ixgbe_mac_X540:
- dv_id = IXGBE_DV_X540(link, tc);
- break;
- default:
- dv_id = IXGBE_DV(link, tc);
- break;
- }
-
- /* Loopback switch introduces additional latency */
- if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
- dv_id += IXGBE_B2BT(tc);
-
- /* Delay value is calculated in bit times convert to KB */
- kb = IXGBE_BT2KB(dv_id);
- rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
-
- marker = rx_pba - kb;
-
- /* It is possible that the packet buffer is not large enough
- * to provide required headroom. In this case throw an error
- * to user and a do the best we can.
- */
- if (marker < 0) {
- e_warn(drv, "Packet Buffer(%i) can not provide enough"
- "headroom to suppport flow control."
- "Decrease MTU or number of traffic classes\n", pb);
- marker = tc + 1;
- }
-
- return marker;
-}
-
-/*
- * ixgbe_lpbthresh - calculate low water mark for for flow control
- *
- * @adapter: board private structure to calculate for
- * @pb - packet buffer to calculate
- */
-static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
-{
- struct ixgbe_hw *hw = &adapter->hw;
- struct net_device *dev = adapter->netdev;
- int tc;
- u32 dv_id;
-
- /* Calculate max LAN frame size */
- tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
-
-#ifdef IXGBE_FCOE
- /* FCoE traffic class uses FCOE jumbo frames */
- if (dev->features & NETIF_F_FCOE_MTU) {
- int fcoe_pb = 0;
-
- fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
-
- if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
- tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
- }
-#endif
-
- /* Calculate delay value for device */
- switch (hw->mac.type) {
- case ixgbe_mac_X540:
- dv_id = IXGBE_LOW_DV_X540(tc);
- break;
- default:
- dv_id = IXGBE_LOW_DV(tc);
- break;
- }
-
- /* Delay value is calculated in bit times convert to KB */
- return IXGBE_BT2KB(dv_id);
-}
-
-/*
- * ixgbe_pbthresh_setup - calculate and setup high low water marks
- */
-static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
-{
- struct ixgbe_hw *hw = &adapter->hw;
- int num_tc = netdev_get_num_tc(adapter->netdev);
- int i;
-
- if (!num_tc)
- num_tc = 1;
- if (num_tc > IXGBE_DCB_MAX_TRAFFIC_CLASS)
- num_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
-
- for (i = 0; i < num_tc; i++) {
- hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
- hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
-
- /* Low water marks must not be larger than high water marks */
- if (hw->fc.low_water[i] > hw->fc.high_water[i])
- hw->fc.low_water[i] = 0;
- }
-
- for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++)
- hw->fc.high_water[i] = 0;
-}
-
-
-
-#ifdef NO_VNIC
-static void ixgbe_configure(struct ixgbe_adapter *adapter)
-{
- struct ixgbe_hw *hw = &adapter->hw;
-
- ixgbe_configure_pb(adapter);
- ixgbe_configure_dcb(adapter);
-
- ixgbe_set_rx_mode(adapter->netdev);
-#ifdef NETIF_F_HW_VLAN_TX
- ixgbe_restore_vlan(adapter);
-#endif
-
-#ifdef IXGBE_FCOE
- if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
- ixgbe_configure_fcoe(adapter);
-
-#endif /* IXGBE_FCOE */
-
- if (adapter->hw.mac.type != ixgbe_mac_82598EB)
- hw->mac.ops.disable_sec_rx_path(hw);
-
- if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
- ixgbe_init_fdir_signature_82599(&adapter->hw,
- adapter->fdir_pballoc);
- } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
- ixgbe_init_fdir_perfect_82599(&adapter->hw,
- adapter->fdir_pballoc);
- ixgbe_fdir_filter_restore(adapter);
- }
-
- if (adapter->hw.mac.type != ixgbe_mac_82598EB)
- hw->mac.ops.enable_sec_rx_path(hw);
-
- ixgbe_configure_virtualization(adapter);
-
- ixgbe_configure_tx(adapter);
- ixgbe_configure_rx(adapter);
-}
-#endif
-
-static bool ixgbe_is_sfp(struct ixgbe_hw *hw)
-{
- switch (hw->phy.type) {
- case ixgbe_phy_sfp_avago:
- case ixgbe_phy_sfp_ftl:
- case ixgbe_phy_sfp_intel:
- case ixgbe_phy_sfp_unknown:
- case ixgbe_phy_sfp_passive_tyco:
- case ixgbe_phy_sfp_passive_unknown:
- case ixgbe_phy_sfp_active_unknown:
- case ixgbe_phy_sfp_ftl_active:
- return true;
- case ixgbe_phy_nl:
- if (hw->mac.type == ixgbe_mac_82598EB)
- return true;
- default:
- return false;
- }
-}
-
-
-/**
- * ixgbe_clear_vf_stats_counters - Clear out VF stats after reset
- * @adapter: board private structure
- *
- * On a reset we need to clear out the VF stats or accounting gets
- * messed up because they're not clear on read.
- **/
-void ixgbe_clear_vf_stats_counters(struct ixgbe_adapter *adapter)
-{
- struct ixgbe_hw *hw = &adapter->hw;
- int i;
-
- for (i = 0; i < adapter->num_vfs; i++) {
- adapter->vfinfo[i].last_vfstats.gprc =
- IXGBE_READ_REG(hw, IXGBE_PVFGPRC(i));
- adapter->vfinfo[i].saved_rst_vfstats.gprc +=
- adapter->vfinfo[i].vfstats.gprc;
- adapter->vfinfo[i].vfstats.gprc = 0;
- adapter->vfinfo[i].last_vfstats.gptc =
- IXGBE_READ_REG(hw, IXGBE_PVFGPTC(i));
- adapter->vfinfo[i].saved_rst_vfstats.gptc +=
- adapter->vfinfo[i].vfstats.gptc;
- adapter->vfinfo[i].vfstats.gptc = 0;
- adapter->vfinfo[i].last_vfstats.gorc =
- IXGBE_READ_REG(hw, IXGBE_PVFGORC_LSB(i));
- adapter->vfinfo[i].saved_rst_vfstats.gorc +=
- adapter->vfinfo[i].vfstats.gorc;
- adapter->vfinfo[i].vfstats.gorc = 0;
- adapter->vfinfo[i].last_vfstats.gotc =
- IXGBE_READ_REG(hw, IXGBE_PVFGOTC_LSB(i));
- adapter->vfinfo[i].saved_rst_vfstats.gotc +=
- adapter->vfinfo[i].vfstats.gotc;
- adapter->vfinfo[i].vfstats.gotc = 0;
- adapter->vfinfo[i].last_vfstats.mprc =
- IXGBE_READ_REG(hw, IXGBE_PVFMPRC(i));
- adapter->vfinfo[i].saved_rst_vfstats.mprc +=
- adapter->vfinfo[i].vfstats.mprc;
- adapter->vfinfo[i].vfstats.mprc = 0;
- }
-}
-
-
-
-void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
-{
-#ifdef NO_VNIC
- WARN_ON(in_interrupt());
- /* put off any impending NetWatchDogTimeout */
- adapter->netdev->trans_start = jiffies;
-
- while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
- usleep_range(1000, 2000);
- ixgbe_down(adapter);
- /*
- * If SR-IOV enabled then wait a bit before bringing the adapter
- * back up to give the VFs time to respond to the reset. The
- * two second wait is based upon the watchdog timer cycle in
- * the VF driver.
- */
- if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
- msleep(2000);
- ixgbe_up(adapter);
- clear_bit(__IXGBE_RESETTING, &adapter->state);
-#endif
-}
-
-void ixgbe_up(struct ixgbe_adapter *adapter)
-{
- /* hardware has been reset, we need to reload some things */
- //ixgbe_configure(adapter);
-
- //ixgbe_up_complete(adapter);
-}
-
-void ixgbe_reset(struct ixgbe_adapter *adapter)
-{
- struct ixgbe_hw *hw = &adapter->hw;
- struct net_device *netdev = adapter->netdev;
- int err;
-
- /* lock SFP init bit to prevent race conditions with the watchdog */
- while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
- usleep_range(1000, 2000);
-
- /* clear all SFP and link config related flags while holding SFP_INIT */
- adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
- IXGBE_FLAG2_SFP_NEEDS_RESET);
- adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
-
- err = hw->mac.ops.init_hw(hw);
- switch (err) {
- case 0:
- case IXGBE_ERR_SFP_NOT_PRESENT:
- case IXGBE_ERR_SFP_NOT_SUPPORTED:
- break;
- case IXGBE_ERR_MASTER_REQUESTS_PENDING:
- e_dev_err("master disable timed out\n");
- break;
- case IXGBE_ERR_EEPROM_VERSION:
- /* We are running on a pre-production device, log a warning */
- e_dev_warn("This device is a pre-production adapter/LOM. "
- "Please be aware there may be issues associated "
- "with your hardware. If you are experiencing "
- "problems please contact your Intel or hardware "
- "representative who provided you with this "
- "hardware.\n");
- break;
- default:
- e_dev_err("Hardware Error: %d\n", err);
- }
-
- clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
-
- ixgbe_flush_sw_mac_table(adapter);
- memcpy(&adapter->mac_table[0].addr, hw->mac.perm_addr,
- netdev->addr_len);
- adapter->mac_table[0].queue = adapter->num_vfs;
- adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
- IXGBE_MAC_STATE_IN_USE);
- hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
- adapter->mac_table[0].queue,
- IXGBE_RAH_AV);
-}
-
-
-
-
-
-
-void ixgbe_down(struct ixgbe_adapter *adapter)
-{
-#ifdef NO_VNIC
- struct net_device *netdev = adapter->netdev;
- struct ixgbe_hw *hw = &adapter->hw;
- u32 rxctrl;
- int i;
-
- /* signal that we are down to the interrupt handler */
- set_bit(__IXGBE_DOWN, &adapter->state);
-
- /* disable receives */
- rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
- IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
-
- /* disable all enabled rx queues */
- for (i = 0; i < adapter->num_rx_queues; i++)
- /* this call also flushes the previous write */
- ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
-
- usleep_range(10000, 20000);
-
- netif_tx_stop_all_queues(netdev);
-
- /* call carrier off first to avoid false dev_watchdog timeouts */
- netif_carrier_off(netdev);
- netif_tx_disable(netdev);
-
- ixgbe_irq_disable(adapter);
-
- ixgbe_napi_disable_all(adapter);
-
- adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
- IXGBE_FLAG2_RESET_REQUESTED);
- adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
-
- del_timer_sync(&adapter->service_timer);
-
- if (adapter->num_vfs) {
- /* Clear EITR Select mapping */
- IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
-
- /* Mark all the VFs as inactive */
- for (i = 0 ; i < adapter->num_vfs; i++)
- adapter->vfinfo[i].clear_to_send = 0;
-
- /* ping all the active vfs to let them know we are going down */
- ixgbe_ping_all_vfs(adapter);
-
- /* Disable all VFTE/VFRE TX/RX */
- ixgbe_disable_tx_rx(adapter);
- }
-
- /* disable transmits in the hardware now that interrupts are off */
- for (i = 0; i < adapter->num_tx_queues; i++) {
- u8 reg_idx = adapter->tx_ring[i]->reg_idx;
- IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
- }
-
- /* Disable the Tx DMA engine on 82599 and X540 */
- switch (hw->mac.type) {
- case ixgbe_mac_82599EB:
- case ixgbe_mac_X540:
- IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
- (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
- ~IXGBE_DMATXCTL_TE));
- break;
- default:
- break;
- }
-
-#ifdef HAVE_PCI_ERS
- if (!pci_channel_offline(adapter->pdev))
-#endif
- ixgbe_reset(adapter);
- /* power down the optics */
- if ((hw->phy.multispeed_fiber) ||
- ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
- (hw->mac.type == ixgbe_mac_82599EB)))
- ixgbe_disable_tx_laser(hw);
-
- ixgbe_clean_all_tx_rings(adapter);
- ixgbe_clean_all_rx_rings(adapter);
-
-#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
- /* since we reset the hardware DCA settings were cleared */
- ixgbe_setup_dca(adapter);
-#endif
-
-#endif /* NO_VNIC */
-}
-
-#ifndef NO_VNIC
-
-#undef IXGBE_FCOE
-
-/* Artificial max queue cap per traffic class in DCB mode */
-#define DCB_QUEUE_CAP 8
-
-/**
- * ixgbe_set_dcb_queues: Allocate queues for a DCB-enabled device
- * @adapter: board private structure to initialize
- *
- * When DCB (Data Center Bridging) is enabled, allocate queues for
- * each traffic class. If multiqueue isn't available,then abort DCB
- * initialization.
- *
- * This function handles all combinations of DCB, RSS, and FCoE.
- *
- **/
-static bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
-{
- int tcs;
-#ifdef HAVE_MQPRIO
- int rss_i, i, offset = 0;
- struct net_device *dev = adapter->netdev;
-
- /* Map queue offset and counts onto allocated tx queues */
- tcs = netdev_get_num_tc(dev);
-
- if (!tcs)
- return false;
-
- rss_i = min_t(int, dev->num_tx_queues / tcs, num_online_cpus());
-
- if (rss_i > DCB_QUEUE_CAP)
- rss_i = DCB_QUEUE_CAP;
-
- for (i = 0; i < tcs; i++) {
- netdev_set_tc_queue(dev, i, rss_i, offset);
- offset += rss_i;
- }
-
- adapter->num_tx_queues = rss_i * tcs;
- adapter->num_rx_queues = rss_i * tcs;
-
-#ifdef IXGBE_FCOE
- /* FCoE enabled queues require special configuration indexed
- * by feature specific indices and mask. Here we map FCoE
- * indices onto the DCB queue pairs allowing FCoE to own
- * configuration later.
- */
-
- if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
- struct ixgbe_ring_feature *f;
- int tc;
- u8 prio_tc[IXGBE_DCB_MAX_USER_PRIORITY] = {0};
-
- ixgbe_dcb_unpack_map_cee(&adapter->dcb_cfg,
- IXGBE_DCB_TX_CONFIG,
- prio_tc);
- tc = prio_tc[adapter->fcoe.up];
-
- f = &adapter->ring_feature[RING_F_FCOE];
- f->indices = min_t(int, rss_i, f->indices);
- f->mask = rss_i * tc;
- }
-#endif /* IXGBE_FCOE */
-#else
- if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
- return false;
-
- /* Enable one Queue per traffic class */
- tcs = adapter->tc;
- if (!tcs)
- return false;
-
-#ifdef IXGBE_FCOE
- if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
- struct ixgbe_ring_feature *f;
- int tc = netdev_get_prio_tc_map(adapter->netdev,
- adapter->fcoe.up);
-
- f = &adapter->ring_feature[RING_F_FCOE];
-
- /*
- * We have max 8 queues for FCoE, where 8 the is
- * FCoE redirection table size. We must also share
- * ring resources with network traffic so if FCoE TC is
- * 4 or greater and we are in 8 TC mode we can only use
- * 7 queues.
- */
- if ((tcs > 4) && (tc >= 4) && (f->indices > 7))
- f->indices = 7;
-
- f->indices = min_t(int, num_online_cpus(), f->indices);
- f->mask = tcs;
-
- adapter->num_rx_queues = f->indices + tcs;
- adapter->num_tx_queues = f->indices + tcs;
-
- return true;
- }
-
-#endif /* IXGBE_FCOE */
- adapter->num_rx_queues = tcs;
- adapter->num_tx_queues = tcs;
-#endif /* HAVE_MQ */
-
- return true;
-}
-
-/**
- * ixgbe_set_vmdq_queues: Allocate queues for VMDq devices
- * @adapter: board private structure to initialize
- *
- * When VMDq (Virtual Machine Devices queue) is enabled, allocate queues
- * and VM pools where appropriate. If RSS is available, then also try and
- * enable RSS and map accordingly.
- *
- **/
-static bool ixgbe_set_vmdq_queues(struct ixgbe_adapter *adapter)
-{
- int vmdq_i = adapter->ring_feature[RING_F_VMDQ].indices;
- int vmdq_m = 0;
- int rss_i = adapter->ring_feature[RING_F_RSS].indices;
- unsigned long i;
- int rss_shift;
- bool ret = false;
-
-
- switch (adapter->flags & (IXGBE_FLAG_RSS_ENABLED
- | IXGBE_FLAG_DCB_ENABLED
- | IXGBE_FLAG_VMDQ_ENABLED)) {
-
- case (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_VMDQ_ENABLED):
- switch (adapter->hw.mac.type) {
- case ixgbe_mac_82599EB:
- case ixgbe_mac_X540:
- vmdq_i = min((int)IXGBE_MAX_VMDQ_INDICES, vmdq_i);
- if (vmdq_i > 32)
- rss_i = 2;
- else
- rss_i = 4;
- i = rss_i;
- rss_shift = find_first_bit(&i, sizeof(i) * 8);
- vmdq_m = ((IXGBE_MAX_VMDQ_INDICES - 1) <<
- rss_shift) & (MAX_RX_QUEUES - 1);
- break;
- default:
- break;
- }
- adapter->num_rx_queues = vmdq_i * rss_i;
- adapter->num_tx_queues = min((int)MAX_TX_QUEUES, vmdq_i * rss_i);
- ret = true;
- break;
-
- case (IXGBE_FLAG_VMDQ_ENABLED):
- switch (adapter->hw.mac.type) {
- case ixgbe_mac_82598EB:
- vmdq_m = (IXGBE_MAX_VMDQ_INDICES - 1);
- break;
- case ixgbe_mac_82599EB:
- case ixgbe_mac_X540:
- vmdq_m = (IXGBE_MAX_VMDQ_INDICES - 1) << 1;
- break;
- default:
- break;
- }
- adapter->num_rx_queues = vmdq_i;
- adapter->num_tx_queues = vmdq_i;
- ret = true;
- break;
-
- default:
- ret = false;
- goto vmdq_queues_out;
- }
-
- if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
- adapter->num_rx_pools = vmdq_i;
- adapter->num_rx_queues_per_pool = adapter->num_rx_queues /
- vmdq_i;
- } else {
- adapter->num_rx_pools = adapter->num_rx_queues;
- adapter->num_rx_queues_per_pool = 1;
- }
- /* save the mask for later use */
- adapter->ring_feature[RING_F_VMDQ].mask = vmdq_m;
-vmdq_queues_out:
- return ret;
-}
-
-/**
- * ixgbe_set_rss_queues: Allocate queues for RSS
- * @adapter: board private structure to initialize
- *
- * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
- * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
- *
- **/
-static bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
-{
- struct ixgbe_ring_feature *f;
-
- if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
- adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
- return false;
- }
-
- /* set mask for 16 queue limit of RSS */
- f = &adapter->ring_feature[RING_F_RSS];
- f->mask = 0xF;
-
- /*
- * Use Flow Director in addition to RSS to ensure the best
- * distribution of flows across cores, even when an FDIR flow
- * isn't matched.
- */
- if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
- f = &adapter->ring_feature[RING_F_FDIR];
-
- f->indices = min_t(int, num_online_cpus(), f->indices);
- f->mask = 0;
- }
-
- adapter->num_rx_queues = f->indices;
-#ifdef HAVE_TX_MQ
- adapter->num_tx_queues = f->indices;
-#endif
-
- return true;
-}
-
-#ifdef IXGBE_FCOE
-/**
- * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
- * @adapter: board private structure to initialize
- *
- * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
- * The ring feature mask is not used as a mask for FCoE, as it can take any 8
- * rx queues out of the max number of rx queues, instead, it is used as the
- * index of the first rx queue used by FCoE.
- *
- **/
-static bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
-{
- struct ixgbe_ring_feature *f;
-
- if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
- return false;
-
- ixgbe_set_rss_queues(adapter);
-
- f = &adapter->ring_feature[RING_F_FCOE];
- f->indices = min_t(int, num_online_cpus(), f->indices);
-
- /* adding FCoE queues */
- f->mask = adapter->num_rx_queues;
- adapter->num_rx_queues += f->indices;
- adapter->num_tx_queues += f->indices;
-
- return true;
-}
-
-#endif /* IXGBE_FCOE */
-/*
- * ixgbe_set_num_queues: Allocate queues for device, feature dependent
- * @adapter: board private structure to initialize
- *
- * This is the top level queue allocation routine. The order here is very
- * important, starting with the "most" number of features turned on at once,
- * and ending with the smallest set of features. This way large combinations
- * can be allocated if they're turned on, and smaller combinations are the
- * fallthrough conditions.
- *
- **/
-static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
-{
- /* Start with base case */
- adapter->num_rx_queues = 1;
- adapter->num_tx_queues = 1;
- adapter->num_rx_pools = adapter->num_rx_queues;
- adapter->num_rx_queues_per_pool = 1;
-
- if (ixgbe_set_vmdq_queues(adapter))
- return;
-
- if (ixgbe_set_dcb_queues(adapter))
- return;
-
-#ifdef IXGBE_FCOE
- if (ixgbe_set_fcoe_queues(adapter))
- return;
-
-#endif /* IXGBE_FCOE */
- ixgbe_set_rss_queues(adapter);
-}
-
-#endif
-
-
-/**
- * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
- * @adapter: board private structure to initialize
- *
- * ixgbe_sw_init initializes the Adapter private data structure.
- * Fields are initialized based on PCI device information and
- * OS network device settings (MTU size).
- **/
-static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
-{
- struct ixgbe_hw *hw = &adapter->hw;
- struct pci_dev *pdev = adapter->pdev;
- int err;
-
- /* PCI config space info */
-
- hw->vendor_id = pdev->vendor;
- hw->device_id = pdev->device;
- pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
- hw->subsystem_vendor_id = pdev->subsystem_vendor;
- hw->subsystem_device_id = pdev->subsystem_device;
-
- err = ixgbe_init_shared_code(hw);
- if (err) {
- e_err(probe, "init_shared_code failed: %d\n", err);
- goto out;
- }
- adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
- hw->mac.num_rar_entries,
- GFP_ATOMIC);
- /* Set capability flags */
- switch (hw->mac.type) {
- case ixgbe_mac_82598EB:
- adapter->flags |= IXGBE_FLAG_MSI_CAPABLE |
- IXGBE_FLAG_MSIX_CAPABLE |
- IXGBE_FLAG_MQ_CAPABLE |
- IXGBE_FLAG_RSS_CAPABLE;
- adapter->flags |= IXGBE_FLAG_DCB_CAPABLE;
-#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
- adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
-#endif
- adapter->flags &= ~IXGBE_FLAG_SRIOV_CAPABLE;
- adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
-
- if (hw->device_id == IXGBE_DEV_ID_82598AT)
- adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
-
- adapter->max_msix_q_vectors = IXGBE_MAX_MSIX_Q_VECTORS_82598;
- break;
- case ixgbe_mac_X540:
- adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
- case ixgbe_mac_82599EB:
- adapter->flags |= IXGBE_FLAG_MSI_CAPABLE |
- IXGBE_FLAG_MSIX_CAPABLE |
- IXGBE_FLAG_MQ_CAPABLE |
- IXGBE_FLAG_RSS_CAPABLE;
- adapter->flags |= IXGBE_FLAG_DCB_CAPABLE;
-#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
- adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
-#endif
- adapter->flags |= IXGBE_FLAG_SRIOV_CAPABLE;
- adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
-#ifdef IXGBE_FCOE
- adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
- adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
- adapter->ring_feature[RING_F_FCOE].indices = 0;
-#ifdef CONFIG_DCB
- /* Default traffic class to use for FCoE */
- adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
- adapter->fcoe.up = IXGBE_FCOE_DEFTC;
- adapter->fcoe.up_set = IXGBE_FCOE_DEFTC;
-#endif
-#endif
- if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
- adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
-#ifndef IXGBE_NO_SMART_SPEED
- hw->phy.smart_speed = ixgbe_smart_speed_on;
-#else
- hw->phy.smart_speed = ixgbe_smart_speed_off;
-#endif
- adapter->max_msix_q_vectors = IXGBE_MAX_MSIX_Q_VECTORS_82599;
- default:
- break;
- }
-
- /* n-tuple support exists, always init our spinlock */
- //spin_lock_init(&adapter->fdir_perfect_lock);
-
- if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) {
- int j;
- struct ixgbe_dcb_tc_config *tc;
- int dcb_i = IXGBE_DCB_MAX_TRAFFIC_CLASS;
-
-
- adapter->dcb_cfg.num_tcs.pg_tcs = dcb_i;
- adapter->dcb_cfg.num_tcs.pfc_tcs = dcb_i;
- for (j = 0; j < dcb_i; j++) {
- tc = &adapter->dcb_cfg.tc_config[j];
- tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = 0;
- tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 100 / dcb_i;
- tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = 0;
- tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 100 / dcb_i;
- tc->pfc = ixgbe_dcb_pfc_disabled;
- if (j == 0) {
- /* total of all TCs bandwidth needs to be 100 */
- tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent +=
- 100 % dcb_i;
- tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent +=
- 100 % dcb_i;
- }
- }
-
- /* Initialize default user to priority mapping, UPx->TC0 */
- tc = &adapter->dcb_cfg.tc_config[0];
- tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
- tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
-
- adapter->dcb_cfg.bw_percentage[IXGBE_DCB_TX_CONFIG][0] = 100;
- adapter->dcb_cfg.bw_percentage[IXGBE_DCB_RX_CONFIG][0] = 100;
- adapter->dcb_cfg.rx_pba_cfg = ixgbe_dcb_pba_equal;
- adapter->dcb_cfg.pfc_mode_enable = false;
- adapter->dcb_cfg.round_robin_enable = false;
- adapter->dcb_set_bitmap = 0x00;
-#ifdef CONFIG_DCB
- adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
-#endif /* CONFIG_DCB */
-
- if (hw->mac.type == ixgbe_mac_X540) {
- adapter->dcb_cfg.num_tcs.pg_tcs = 4;
- adapter->dcb_cfg.num_tcs.pfc_tcs = 4;
- }
- }
-#ifdef CONFIG_DCB
- /* XXX does this need to be initialized even w/o DCB? */
- //memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
- // sizeof(adapter->temp_dcb_cfg));
-
-#endif
- //if (hw->mac.type == ixgbe_mac_82599EB ||
- // hw->mac.type == ixgbe_mac_X540)
- // hw->mbx.ops.init_params(hw);
-
- /* default flow control settings */
- hw->fc.requested_mode = ixgbe_fc_full;
- hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
-
- adapter->last_lfc_mode = hw->fc.current_mode;
- ixgbe_pbthresh_setup(adapter);
- hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
- hw->fc.send_xon = true;
- hw->fc.disable_fc_autoneg = false;
-
- /* set default ring sizes */
- adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
- adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
-
- /* set default work limits */
- adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
- adapter->rx_work_limit = IXGBE_DEFAULT_RX_WORK;
-
- set_bit(__IXGBE_DOWN, &adapter->state);
-out:
- return err;
-}
-
-/**
- * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
- * @tx_ring: tx descriptor ring (for a specific queue) to setup
- *
- * Return 0 on success, negative on failure
- **/
-int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
-{
- struct device *dev = tx_ring->dev;
- //int orig_node = dev_to_node(dev);
- int numa_node = -1;
- int size;
-
- size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
-
- if (tx_ring->q_vector)
- numa_node = tx_ring->q_vector->numa_node;
-
- tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
- if (!tx_ring->tx_buffer_info)
- tx_ring->tx_buffer_info = vzalloc(size);
- if (!tx_ring->tx_buffer_info)
- goto err;
-
- /* round up to nearest 4K */
- tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
- tx_ring->size = ALIGN(tx_ring->size, 4096);
-
- //set_dev_node(dev, numa_node);
- //tx_ring->desc = dma_alloc_coherent(dev,
- // tx_ring->size,
- // &tx_ring->dma,
- // GFP_KERNEL);
- //set_dev_node(dev, orig_node);
- //if (!tx_ring->desc)
- // tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
- // &tx_ring->dma, GFP_KERNEL);
- //if (!tx_ring->desc)
- // goto err;
-
- return 0;
-
-err:
- vfree(tx_ring->tx_buffer_info);
- tx_ring->tx_buffer_info = NULL;
- dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
- return -ENOMEM;
-}
-
-/**
- * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
- * @adapter: board private structure
- *
- * If this function returns with an error, then it's possible one or
- * more of the rings is populated (while the rest are not). It is the
- * callers duty to clean those orphaned rings.
- *
- * Return 0 on success, negative on failure
- **/
-static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
-{
- int i, err = 0;
-
- for (i = 0; i < adapter->num_tx_queues; i++) {
- err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
- if (!err)
- continue;
- e_err(probe, "Allocation for Tx Queue %u failed\n", i);
- break;
- }
-
- return err;
-}
-
-/**
- * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
- * @rx_ring: rx descriptor ring (for a specific queue) to setup
- *
- * Returns 0 on success, negative on failure
- **/
-int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
-{
- struct device *dev = rx_ring->dev;
- //int orig_node = dev_to_node(dev);
- int numa_node = -1;
- int size;
-
- size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
-
- if (rx_ring->q_vector)
- numa_node = rx_ring->q_vector->numa_node;
-
- rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
- if (!rx_ring->rx_buffer_info)
- rx_ring->rx_buffer_info = vzalloc(size);
- if (!rx_ring->rx_buffer_info)
- goto err;
-
- /* Round up to nearest 4K */
- rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
- rx_ring->size = ALIGN(rx_ring->size, 4096);
-
-#ifdef NO_VNIC
- set_dev_node(dev, numa_node);
- rx_ring->desc = dma_alloc_coherent(dev,
- rx_ring->size,
- &rx_ring->dma,
- GFP_KERNEL);
- set_dev_node(dev, orig_node);
- if (!rx_ring->desc)
- rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
- &rx_ring->dma, GFP_KERNEL);
- if (!rx_ring->desc)
- goto err;
-
-#ifndef CONFIG_IXGBE_DISABLE_PACKET_SPLIT
- ixgbe_init_rx_page_offset(rx_ring);
-
-#endif
-
-#endif /* NO_VNIC */
- return 0;
-err:
- vfree(rx_ring->rx_buffer_info);
- rx_ring->rx_buffer_info = NULL;
- dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
- return -ENOMEM;
-}
-
-/**
- * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
- * @adapter: board private structure
- *
- * If this function returns with an error, then it's possible one or
- * more of the rings is populated (while the rest are not). It is the
- * callers duty to clean those orphaned rings.
- *
- * Return 0 on success, negative on failure
- **/
-static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
-{
- int i, err = 0;
-
- for (i = 0; i < adapter->num_rx_queues; i++) {
- err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
- if (!err)
- continue;
- e_err(probe, "Allocation for Rx Queue %u failed\n", i);
- break;
- }
-
- return err;
-}
-
-/**
- * ixgbe_free_tx_resources - Free Tx Resources per Queue
- * @tx_ring: Tx descriptor ring for a specific queue
- *
- * Free all transmit software resources
- **/
-void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
-{
- //ixgbe_clean_tx_ring(tx_ring);
-
- vfree(tx_ring->tx_buffer_info);
- tx_ring->tx_buffer_info = NULL;
-
- /* if not set, then don't free */
- if (!tx_ring->desc)
- return;
-
- //dma_free_coherent(tx_ring->dev, tx_ring->size,
- // tx_ring->desc, tx_ring->dma);
-
- tx_ring->desc = NULL;
-}
-
-/**
- * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
- * @adapter: board private structure
- *
- * Free all transmit software resources
- **/
-static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
-{
- int i;
-
- for (i = 0; i < adapter->num_tx_queues; i++)
- if (adapter->tx_ring[i]->desc)
- ixgbe_free_tx_resources(adapter->tx_ring[i]);
-}
-
-/**
- * ixgbe_free_rx_resources - Free Rx Resources
- * @rx_ring: ring to clean the resources from
- *
- * Free all receive software resources
- **/
-void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
-{
- //ixgbe_clean_rx_ring(rx_ring);
-
- vfree(rx_ring->rx_buffer_info);
- rx_ring->rx_buffer_info = NULL;
-
- /* if not set, then don't free */
- if (!rx_ring->desc)
- return;
-
- //dma_free_coherent(rx_ring->dev, rx_ring->size,
- // rx_ring->desc, rx_ring->dma);
-
- rx_ring->desc = NULL;
-}
-
-/**
- * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
- * @adapter: board private structure
- *
- * Free all receive software resources
- **/
-static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
-{
- int i;
-
- for (i = 0; i < adapter->num_rx_queues; i++)
- if (adapter->rx_ring[i]->desc)
- ixgbe_free_rx_resources(adapter->rx_ring[i]);
-}
-
-
-/**
- * ixgbe_open - Called when a network interface is made active
- * @netdev: network interface device structure
- *
- * Returns 0 on success, negative value on failure
- *
- * The open entry point is called when a network interface is made
- * active by the system (IFF_UP). At this point all resources needed
- * for transmit and receive operations are allocated, the interrupt
- * handler is registered with the OS, the watchdog timer is started,
- * and the stack is notified that the interface is ready.
- **/
-//static
-int ixgbe_open(struct net_device *netdev)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- int err;
-
- /* disallow open during test */
- if (test_bit(__IXGBE_TESTING, &adapter->state))
- return -EBUSY;
-
- netif_carrier_off(netdev);
-
- /* allocate transmit descriptors */
- err = ixgbe_setup_all_tx_resources(adapter);
- if (err)
- goto err_setup_tx;
-
- /* allocate receive descriptors */
- err = ixgbe_setup_all_rx_resources(adapter);
- if (err)
- goto err_setup_rx;
-
-#ifdef NO_VNIC
- ixgbe_configure(adapter);
-
- err = ixgbe_request_irq(adapter);
- if (err)
- goto err_req_irq;
-
- ixgbe_up_complete(adapter);
-
-err_req_irq:
-#else
- return 0;
-#endif
-err_setup_rx:
- ixgbe_free_all_rx_resources(adapter);
-err_setup_tx:
- ixgbe_free_all_tx_resources(adapter);
- ixgbe_reset(adapter);
-
- return err;
-}
-
-/**
- * ixgbe_close - Disables a network interface
- * @netdev: network interface device structure
- *
- * Returns 0, this is not allowed to fail
- *
- * The close entry point is called when an interface is de-activated
- * by the OS. The hardware is still under the drivers control, but
- * needs to be disabled. A global MAC reset is issued to stop the
- * hardware, and all transmit and receive resources are freed.
- **/
-//static
-int ixgbe_close(struct net_device *netdev)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
-
- //ixgbe_down(adapter);
- //ixgbe_free_irq(adapter);
-
- //ixgbe_fdir_filter_exit(adapter);
-
- //ixgbe_free_all_tx_resources(adapter);
- //ixgbe_free_all_rx_resources(adapter);
-
- ixgbe_release_hw_control(adapter);
-
- return 0;
-}
-
-
-
-
-
-/**
- * ixgbe_get_stats - Get System Network Statistics
- * @netdev: network interface device structure
- *
- * Returns the address of the device statistics structure.
- * The statistics are actually updated from the timer callback.
- **/
-//static
-struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
-
- /* update the stats data */
- ixgbe_update_stats(adapter);
-
-#ifdef HAVE_NETDEV_STATS_IN_NETDEV
- /* only return the current stats */
- return &netdev->stats;
-#else
- /* only return the current stats */
- return &adapter->net_stats;
-#endif /* HAVE_NETDEV_STATS_IN_NETDEV */
-}
-
-/**
- * ixgbe_update_stats - Update the board statistics counters.
- * @adapter: board private structure
- **/
-void ixgbe_update_stats(struct ixgbe_adapter *adapter)
-{
-#ifdef HAVE_NETDEV_STATS_IN_NETDEV
- struct net_device_stats *net_stats = &adapter->netdev->stats;
-#else
- struct net_device_stats *net_stats = &adapter->net_stats;
-#endif /* HAVE_NETDEV_STATS_IN_NETDEV */
- struct ixgbe_hw *hw = &adapter->hw;
- struct ixgbe_hw_stats *hwstats = &adapter->stats;
- u64 total_mpc = 0;
- u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
- u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
- u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
- u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
-#ifndef IXGBE_NO_LRO
- u32 flushed = 0, coal = 0;
- int num_q_vectors = 1;
-#endif
-#ifdef IXGBE_FCOE
- struct ixgbe_fcoe *fcoe = &adapter->fcoe;
- unsigned int cpu;
- u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
-#endif /* IXGBE_FCOE */
-
- printk(KERN_DEBUG "ixgbe_update_stats, tx_queues=%d, rx_queues=%d\n",
- adapter->num_tx_queues, adapter->num_rx_queues);
-
- if (test_bit(__IXGBE_DOWN, &adapter->state) ||
- test_bit(__IXGBE_RESETTING, &adapter->state))
- return;
-
-#ifndef IXGBE_NO_LRO
- if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
- num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
-
-#endif
- if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
- u64 rsc_count = 0;
- u64 rsc_flush = 0;
- for (i = 0; i < adapter->num_rx_queues; i++) {
- rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
- rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
- }
- adapter->rsc_total_count = rsc_count;
- adapter->rsc_total_flush = rsc_flush;
- }
-
-#ifndef IXGBE_NO_LRO
- for (i = 0; i < num_q_vectors; i++) {
- struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
- if (!q_vector)
- continue;
- flushed += q_vector->lrolist.stats.flushed;
- coal += q_vector->lrolist.stats.coal;
- }
- adapter->lro_stats.flushed = flushed;
- adapter->lro_stats.coal = coal;
-
-#endif
- for (i = 0; i < adapter->num_rx_queues; i++) {
- struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
- non_eop_descs += rx_ring->rx_stats.non_eop_descs;
- alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
- alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
- hw_csum_rx_error += rx_ring->rx_stats.csum_err;
- bytes += rx_ring->stats.bytes;
- packets += rx_ring->stats.packets;
-
- }
- adapter->non_eop_descs = non_eop_descs;
- adapter->alloc_rx_page_failed = alloc_rx_page_failed;
- adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
- adapter->hw_csum_rx_error = hw_csum_rx_error;
- net_stats->rx_bytes = bytes;
- net_stats->rx_packets = packets;
-
- bytes = 0;
- packets = 0;
- /* gather some stats to the adapter struct that are per queue */
- for (i = 0; i < adapter->num_tx_queues; i++) {
- struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
- restart_queue += tx_ring->tx_stats.restart_queue;
- tx_busy += tx_ring->tx_stats.tx_busy;
- bytes += tx_ring->stats.bytes;
- packets += tx_ring->stats.packets;
- }
- adapter->restart_queue = restart_queue;
- adapter->tx_busy = tx_busy;
- net_stats->tx_bytes = bytes;
- net_stats->tx_packets = packets;
-
- hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
-
- /* 8 register reads */
- for (i = 0; i < 8; i++) {
- /* for packet buffers not used, the register should read 0 */
- mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
- missed_rx += mpc;
- hwstats->mpc[i] += mpc;
- total_mpc += hwstats->mpc[i];
- hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
- hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
- switch (hw->mac.type) {
- case ixgbe_mac_82598EB:
- hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
- hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
- hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
- hwstats->pxonrxc[i] +=
- IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
- break;
- case ixgbe_mac_82599EB:
- case ixgbe_mac_X540:
- hwstats->pxonrxc[i] +=
- IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
- break;
- default:
- break;
- }
- }
-
- /*16 register reads */
- for (i = 0; i < 16; i++) {
- hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
- hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
- if ((hw->mac.type == ixgbe_mac_82599EB) ||
- (hw->mac.type == ixgbe_mac_X540)) {
- hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
- IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
- hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
- IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
- }
- }
-
- hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
- /* work around hardware counting issue */
- hwstats->gprc -= missed_rx;
-
- ixgbe_update_xoff_received(adapter);
-
- /* 82598 hardware only has a 32 bit counter in the high register */
- switch (hw->mac.type) {
- case ixgbe_mac_82598EB:
- hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
- hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
- hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
- hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
- break;
- case ixgbe_mac_X540:
- /* OS2BMC stats are X540 only*/
- hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
- hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
- hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
- hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
- case ixgbe_mac_82599EB:
- for (i = 0; i < 16; i++)
- adapter->hw_rx_no_dma_resources +=
- IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
- hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
- IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
- hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
- IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
- hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
- IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
- hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
-#ifdef HAVE_TX_MQ
- hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
- hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
-#endif /* HAVE_TX_MQ */
-#ifdef IXGBE_FCOE
- hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
- hwstats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
- hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
- hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
- hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
- hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
- hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
- /* Add up per cpu counters for total ddp aloc fail */
- if (fcoe && fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
- for_each_possible_cpu(cpu) {
- fcoe_noddp_counts_sum +=
- *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
- fcoe_noddp_ext_buff_counts_sum +=
- *per_cpu_ptr(fcoe->
- pcpu_noddp_ext_buff, cpu);
- }
- }
- hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
- hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
-
-#endif /* IXGBE_FCOE */
- break;
- default:
- break;
- }
- bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
- hwstats->bprc += bprc;
- hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
- if (hw->mac.type == ixgbe_mac_82598EB)
- hwstats->mprc -= bprc;
- hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
- hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
- hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
- hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
- hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
- hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
- hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
- hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
- lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
- hwstats->lxontxc += lxon;
- lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
- hwstats->lxofftxc += lxoff;
- hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
- hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
- /*
- * 82598 errata - tx of flow control packets is included in tx counters
- */
- xon_off_tot = lxon + lxoff;
- hwstats->gptc -= xon_off_tot;
- hwstats->mptc -= xon_off_tot;
- hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
- hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
- hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
- hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
- hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
- hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
- hwstats->ptc64 -= xon_off_tot;
- hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
- hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
- hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
- hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
- hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
- hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
- /* Fill out the OS statistics structure */
- net_stats->multicast = hwstats->mprc;
-
- /* Rx Errors */
- net_stats->rx_errors = hwstats->crcerrs +
- hwstats->rlec;
- net_stats->rx_dropped = 0;
- net_stats->rx_length_errors = hwstats->rlec;
- net_stats->rx_crc_errors = hwstats->crcerrs;
- net_stats->rx_missed_errors = total_mpc;
-
- /*
- * VF Stats Collection - skip while resetting because these
- * are not clear on read and otherwise you'll sometimes get
- * crazy values.
- */
- if (!test_bit(__IXGBE_RESETTING, &adapter->state)) {
- for (i = 0; i < adapter->num_vfs; i++) {
- UPDATE_VF_COUNTER_32bit(IXGBE_PVFGPRC(i), \
- adapter->vfinfo[i].last_vfstats.gprc, \
- adapter->vfinfo[i].vfstats.gprc);
- UPDATE_VF_COUNTER_32bit(IXGBE_PVFGPTC(i), \
- adapter->vfinfo[i].last_vfstats.gptc, \
- adapter->vfinfo[i].vfstats.gptc);
- UPDATE_VF_COUNTER_36bit(IXGBE_PVFGORC_LSB(i), \
- IXGBE_PVFGORC_MSB(i), \
- adapter->vfinfo[i].last_vfstats.gorc, \
- adapter->vfinfo[i].vfstats.gorc);
- UPDATE_VF_COUNTER_36bit(IXGBE_PVFGOTC_LSB(i), \
- IXGBE_PVFGOTC_MSB(i), \
- adapter->vfinfo[i].last_vfstats.gotc, \
- adapter->vfinfo[i].vfstats.gotc);
- UPDATE_VF_COUNTER_32bit(IXGBE_PVFMPRC(i), \
- adapter->vfinfo[i].last_vfstats.mprc, \
- adapter->vfinfo[i].vfstats.mprc);
- }
- }
-}
-
-
-#ifdef NO_VNIC
-
-/**
- * ixgbe_watchdog_update_link - update the link status
- * @adapter - pointer to the device adapter structure
- * @link_speed - pointer to a u32 to store the link_speed
- **/
-static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
-{
- struct ixgbe_hw *hw = &adapter->hw;
- u32 link_speed = adapter->link_speed;
- bool link_up = adapter->link_up;
- bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
-
- if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
- return;
-
- if (hw->mac.ops.check_link) {
- hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
- } else {
- /* always assume link is up, if no check link function */
- link_speed = IXGBE_LINK_SPEED_10GB_FULL;
- link_up = true;
- }
-
-#ifdef HAVE_DCBNL_IEEE
- if (adapter->ixgbe_ieee_pfc)
- pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
-
-#endif
- if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
- hw->mac.ops.fc_enable(hw);
- //ixgbe_set_rx_drop_en(adapter);
- }
-
- if (link_up ||
- time_after(jiffies, (adapter->link_check_timeout +
- IXGBE_TRY_LINK_TIMEOUT))) {
- adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
- IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
- IXGBE_WRITE_FLUSH(hw);
- }
-
- adapter->link_up = link_up;
- adapter->link_speed = link_speed;
-}
-#endif
-
-
-
-#ifdef NO_VNIC
-
-/**
- * ixgbe_service_task - manages and runs subtasks
- * @work: pointer to work_struct containing our data
- **/
-static void ixgbe_service_task(struct work_struct *work)
-{
- //struct ixgbe_adapter *adapter = container_of(work,
- // struct ixgbe_adapter,
- // service_task);
-
- //ixgbe_reset_subtask(adapter);
- //ixgbe_sfp_detection_subtask(adapter);
- //ixgbe_sfp_link_config_subtask(adapter);
- //ixgbe_check_overtemp_subtask(adapter);
- //ixgbe_watchdog_subtask(adapter);
-#ifdef HAVE_TX_MQ
- //ixgbe_fdir_reinit_subtask(adapter);
-#endif
- //ixgbe_check_hang_subtask(adapter);
-
- //ixgbe_service_event_complete(adapter);
-}
-
-
-
-
-#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
- IXGBE_TXD_CMD_RS)
-
-
-/**
- * ixgbe_set_mac - Change the Ethernet Address of the NIC
- * @netdev: network interface device structure
- * @p: pointer to an address structure
- *
- * Returns 0 on success, negative on failure
- **/
-static int ixgbe_set_mac(struct net_device *netdev, void *p)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
- struct ixgbe_hw *hw = &adapter->hw;
- struct sockaddr *addr = p;
- int ret;
-
- if (!is_valid_ether_addr(addr->sa_data))
- return -EADDRNOTAVAIL;
-
- ixgbe_del_mac_filter(adapter, hw->mac.addr,
- adapter->num_vfs);
- memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
- memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
-
-
- /* set the correct pool for the new PF MAC address in entry 0 */
- ret = ixgbe_add_mac_filter(adapter, hw->mac.addr,
- adapter->num_vfs);
- return ret > 0 ? 0 : ret;
-}
-
-
-/**
- * ixgbe_ioctl -
- * @netdev:
- * @ifreq:
- * @cmd:
- **/
-static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
-{
- switch (cmd) {
-#ifdef ETHTOOL_OPS_COMPAT
- case SIOCETHTOOL:
- return ethtool_ioctl(ifr);
-#endif
- default:
- return -EOPNOTSUPP;
- }
-}
-#endif /* NO_VNIC */
-
-
-void ixgbe_do_reset(struct net_device *netdev)
-{
- struct ixgbe_adapter *adapter = netdev_priv(netdev);
-
- if (netif_running(netdev))
- ixgbe_reinit_locked(adapter);
- else
- ixgbe_reset(adapter);
-}
-
-
-
-
-
-
-/**
- * ixgbe_probe - Device Initialization Routine
- * @pdev: PCI device information struct
- * @ent: entry in ixgbe_pci_tbl
- *
- * Returns 0 on success, negative on failure
- *
- * ixgbe_probe initializes an adapter identified by a pci_dev structure.
- * The OS initialization, configuring of the adapter private structure,
- * and a hardware reset occur.
- **/
-//static
-int ixgbe_kni_probe(struct pci_dev *pdev,
- struct net_device **lad_dev)
-{
- size_t count;
- struct net_device *netdev;
- struct ixgbe_adapter *adapter = NULL;
- struct ixgbe_hw *hw = NULL;
- static int cards_found;
- int i, err;
- u16 offset;
- u16 eeprom_verh, eeprom_verl, eeprom_cfg_blkh, eeprom_cfg_blkl;
- u32 etrack_id;
- u16 build, major, patch;
- char *info_string, *i_s_var;
- u8 part_str[IXGBE_PBANUM_LENGTH];
- enum ixgbe_mac_type mac_type = ixgbe_mac_unknown;
-#ifdef HAVE_TX_MQ
- unsigned int indices = num_possible_cpus();
-#endif /* HAVE_TX_MQ */
-#ifdef IXGBE_FCOE
- u16 device_caps;
-#endif
- u16 wol_cap;
-
- err = pci_enable_device_mem(pdev);
- if (err)
- return err;
-
-
-#ifdef NO_VNIC
- err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
- IORESOURCE_MEM), ixgbe_driver_name);
- if (err) {
- dev_err(pci_dev_to_dev(pdev),
- "pci_request_selected_regions failed 0x%x\n", err);
- goto err_pci_reg;
- }
-#endif
-
- /*
- * The mac_type is needed before we have the adapter is set up
- * so rather than maintain two devID -> MAC tables we dummy up
- * an ixgbe_hw stuct and use ixgbe_set_mac_type.
- */
- hw = vmalloc(sizeof(struct ixgbe_hw));
- if (!hw) {
- pr_info("Unable to allocate memory for early mac "
- "check\n");
- } else {
- hw->vendor_id = pdev->vendor;
- hw->device_id = pdev->device;
- ixgbe_set_mac_type(hw);
- mac_type = hw->mac.type;
- vfree(hw);
- }
-
-#ifdef NO_VNIC
- /*
- * Workaround of Silicon errata on 82598. Disable LOs in the PCI switch
- * port to which the 82598 is connected to prevent duplicate
- * completions caused by LOs. We need the mac type so that we only
- * do this on 82598 devices, ixgbe_set_mac_type does this for us if
- * we set it's device ID.
- */
- if (mac_type == ixgbe_mac_82598EB)
- pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
-
- pci_enable_pcie_error_reporting(pdev);
-
- pci_set_master(pdev);
-#endif
-
-#ifdef HAVE_TX_MQ
-#ifdef CONFIG_DCB
-#ifdef HAVE_MQPRIO
- indices *= IXGBE_DCB_MAX_TRAFFIC_CLASS;
-#else
- indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
-#endif /* HAVE_MQPRIO */
-#endif /* CONFIG_DCB */
-
- if (mac_type == ixgbe_mac_82598EB)
- indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
- else
- indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
-
-#ifdef IXGBE_FCOE
- indices += min_t(unsigned int, num_possible_cpus(),
- IXGBE_MAX_FCOE_INDICES);
-#endif
- netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
-#else /* HAVE_TX_MQ */
- netdev = alloc_etherdev(sizeof(struct ixgbe_adapter));
-#endif /* HAVE_TX_MQ */
- if (!netdev) {
- err = -ENOMEM;
- goto err_alloc_etherdev;
- }
-
- SET_NETDEV_DEV(netdev, &pdev->dev);
-
- adapter = netdev_priv(netdev);
- //pci_set_drvdata(pdev, adapter);
-
- adapter->netdev = netdev;
- adapter->pdev = pdev;
- hw = &adapter->hw;
- hw->back = adapter;
- adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
-
-#ifdef HAVE_PCI_ERS
- /*
- * call save state here in standalone driver because it relies on
- * adapter struct to exist, and needs to call netdev_priv
- */
- pci_save_state(pdev);
-
-#endif
- hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
- pci_resource_len(pdev, 0));
- if (!hw->hw_addr) {
- err = -EIO;
- goto err_ioremap;
- }
- //ixgbe_assign_netdev_ops(netdev);
- ixgbe_set_ethtool_ops(netdev);
-
- strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
-
- adapter->bd_number = cards_found;
-
- /* setup the private structure */
- err = ixgbe_sw_init(adapter);
- if (err)
- goto err_sw_init;
-
- /* Make it possible the adapter to be woken up via WOL */
- switch (adapter->hw.mac.type) {
- case ixgbe_mac_82599EB:
- case ixgbe_mac_X540:
- IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
- break;
- default:
- break;
- }
-
- /*
- * check_options must be called before setup_link to set up
- * hw->fc completely
- */
- //ixgbe_check_options(adapter);
-
-#ifndef NO_VNIC
- /* reset_hw fills in the perm_addr as well */
- hw->phy.reset_if_overtemp = true;
- err = hw->mac.ops.reset_hw(hw);
- hw->phy.reset_if_overtemp = false;
- if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
- hw->mac.type == ixgbe_mac_82598EB) {
- err = 0;
- } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
- e_dev_err("failed to load because an unsupported SFP+ "
- "module type was detected.\n");
- e_dev_err("Reload the driver after installing a supported "
- "module.\n");
- goto err_sw_init;
- } else if (err) {
- e_dev_err("HW Init failed: %d\n", err);
- goto err_sw_init;
- }
-#endif
-
- //if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
- // ixgbe_probe_vf(adapter);
-
-
-#ifdef MAX_SKB_FRAGS
- netdev->features |= NETIF_F_SG |
- NETIF_F_IP_CSUM;
-
-#ifdef NETIF_F_IPV6_CSUM
- netdev->features |= NETIF_F_IPV6_CSUM;
-#endif
-
-#ifdef NETIF_F_HW_VLAN_TX
- netdev->features |= NETIF_F_HW_VLAN_TX |
- NETIF_F_HW_VLAN_RX;
-#endif
-#ifdef NETIF_F_TSO
- netdev->features |= NETIF_F_TSO;
-#endif /* NETIF_F_TSO */
-#ifdef NETIF_F_TSO6
- netdev->features |= NETIF_F_TSO6;
-#endif /* NETIF_F_TSO6 */
-#ifdef NETIF_F_RXHASH
- netdev->features |= NETIF_F_RXHASH;
-#endif /* NETIF_F_RXHASH */
-
-#ifdef HAVE_NDO_SET_FEATURES
- netdev->features |= NETIF_F_RXCSUM;
-
- /* copy netdev features into list of user selectable features */
- netdev->hw_features |= netdev->features;
-
- /* give us the option of enabling RSC/LRO later */
-#ifdef IXGBE_NO_LRO
- if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
-#endif
- netdev->hw_features |= NETIF_F_LRO;
-
-#else
-#ifdef NETIF_F_GRO
-
- /* this is only needed on kernels prior to 2.6.39 */
- netdev->features |= NETIF_F_GRO;
-#endif /* NETIF_F_GRO */
-#endif
-
-#ifdef NETIF_F_HW_VLAN_TX
- /* set this bit last since it cannot be part of hw_features */
- netdev->features |= NETIF_F_HW_VLAN_FILTER;
-#endif
- switch (adapter->hw.mac.type) {
- case ixgbe_mac_82599EB:
- case ixgbe_mac_X540:
- netdev->features |= NETIF_F_SCTP_CSUM;
-#ifdef HAVE_NDO_SET_FEATURES
- netdev->hw_features |= NETIF_F_SCTP_CSUM |
- NETIF_F_NTUPLE;
-#endif
- break;
- default:
- break;
- }
-
-#ifdef HAVE_NETDEV_VLAN_FEATURES
- netdev->vlan_features |= NETIF_F_SG |
- NETIF_F_IP_CSUM |
- NETIF_F_IPV6_CSUM |
- NETIF_F_TSO |
- NETIF_F_TSO6;
-
-#endif /* HAVE_NETDEV_VLAN_FEATURES */
- /*
- * If perfect filters were enabled in check_options(), enable them
- * on the netdevice too.
- */
- if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
- netdev->features |= NETIF_F_NTUPLE;
- if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)
- adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
- if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
- adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
- if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
- adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
- /* clear n-tuple support in the netdev unconditionally */
- netdev->features &= ~NETIF_F_NTUPLE;
- }
-
-#ifdef NETIF_F_RXHASH
- if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
- netdev->features &= ~NETIF_F_RXHASH;
-
-#endif /* NETIF_F_RXHASH */
- if (netdev->features & NETIF_F_LRO) {
- if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
- ((adapter->rx_itr_setting == 1) ||
- (adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR))) {
- adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
- } else if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) {
-#ifdef IXGBE_NO_LRO
- e_info(probe, "InterruptThrottleRate set too high, "
- "disabling RSC\n");
-#else
- e_info(probe, "InterruptThrottleRate set too high, "
- "falling back to software LRO\n");
-#endif
- }
- }
-#ifdef CONFIG_DCB
- //netdev->dcbnl_ops = &dcbnl_ops;
-#endif
-
-#ifdef IXGBE_FCOE
-#ifdef NETIF_F_FSO
- if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
- ixgbe_get_device_caps(hw, &device_caps);
- if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) {
- adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
- adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
- e_info(probe, "FCoE offload feature is not available. "
- "Disabling FCoE offload feature\n");
- }
-#ifndef HAVE_NETDEV_OPS_FCOE_ENABLE
- else {
- adapter->flags |= IXGBE_FLAG_FCOE_ENABLED;
- adapter->ring_feature[RING_F_FCOE].indices =
- IXGBE_FCRETA_SIZE;
- netdev->features |= NETIF_F_FSO |
- NETIF_F_FCOE_CRC |
- NETIF_F_FCOE_MTU;
- netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1;
- }
-#endif /* HAVE_NETDEV_OPS_FCOE_ENABLE */
-#ifdef HAVE_NETDEV_VLAN_FEATURES
- netdev->vlan_features |= NETIF_F_FSO |
- NETIF_F_FCOE_CRC |
- NETIF_F_FCOE_MTU;
-#endif /* HAVE_NETDEV_VLAN_FEATURES */
- }
-#endif /* NETIF_F_FSO */
-#endif /* IXGBE_FCOE */
-
-#endif /* MAX_SKB_FRAGS */
- /* make sure the EEPROM is good */
- if (hw->eeprom.ops.validate_checksum &&
- (hw->eeprom.ops.validate_checksum(hw, NULL) < 0)) {
- e_dev_err("The EEPROM Checksum Is Not Valid\n");
- err = -EIO;
- goto err_sw_init;
- }
-
- memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
-#ifdef ETHTOOL_GPERMADDR
- memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
-
- if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
- e_dev_err("invalid MAC address\n");
- err = -EIO;
- goto err_sw_init;
- }
-#else
- if (ixgbe_validate_mac_addr(netdev->dev_addr)) {
- e_dev_err("invalid MAC address\n");
- err = -EIO;
- goto err_sw_init;
- }
-#endif
- memcpy(&adapter->mac_table[0].addr, hw->mac.perm_addr,
- netdev->addr_len);
- adapter->mac_table[0].queue = adapter->num_vfs;
- adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
- IXGBE_MAC_STATE_IN_USE);
- hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
- adapter->mac_table[0].queue,
- IXGBE_RAH_AV);
-
- //setup_timer(&adapter->service_timer, &ixgbe_service_timer,
- // (unsigned long) adapter);
-
- //INIT_WORK(&adapter->service_task, ixgbe_service_task);
- //clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
-
- //err = ixgbe_init_interrupt_scheme(adapter);
- //if (err)
- // goto err_sw_init;
-
- //adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
- ixgbe_set_num_queues(adapter);
-
- adapter->wol = 0;
- /* WOL not supported for all but the following */
- switch (pdev->device) {
- case IXGBE_DEV_ID_82599_SFP:
- /* Only these subdevice supports WOL */
- switch (pdev->subsystem_device) {
- case IXGBE_SUBDEV_ID_82599_560FLR:
- /* only support first port */
- if (hw->bus.func != 0)
- break;
- case IXGBE_SUBDEV_ID_82599_SFP:
- adapter->wol = IXGBE_WUFC_MAG;
- break;
- }
- break;
- case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
- /* All except this subdevice support WOL */
- if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
- adapter->wol = IXGBE_WUFC_MAG;
- break;
- case IXGBE_DEV_ID_82599_KX4:
- adapter->wol = IXGBE_WUFC_MAG;
- break;
- case IXGBE_DEV_ID_X540T:
- /* Check eeprom to see if it is enabled */
- ixgbe_read_eeprom(hw, 0x2c, &adapter->eeprom_cap);
- wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
-
- if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
- ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
- (hw->bus.func == 0)))
- adapter->wol = IXGBE_WUFC_MAG;
- break;
- }
- //device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
-
-
- /*
- * Save off EEPROM version number and Option Rom version which
- * together make a unique identify for the eeprom
- */
- ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
- ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
-
- etrack_id = (eeprom_verh << 16) | eeprom_verl;
-
- ixgbe_read_eeprom(hw, 0x17, &offset);
-
- /* Make sure offset to SCSI block is valid */
- if (!(offset == 0x0) && !(offset == 0xffff)) {
- ixgbe_read_eeprom(hw, offset + 0x84, &eeprom_cfg_blkh);
- ixgbe_read_eeprom(hw, offset + 0x83, &eeprom_cfg_blkl);
-
- /* Only display Option Rom if exist */
- if (eeprom_cfg_blkl && eeprom_cfg_blkh) {
- major = eeprom_cfg_blkl >> 8;
- build = (eeprom_cfg_blkl << 8) | (eeprom_cfg_blkh >> 8);
- patch = eeprom_cfg_blkh & 0x00ff;
-
- snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
- "0x%08x, %d.%d.%d", etrack_id, major, build,
- patch);
- } else {
- snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
- "0x%08x", etrack_id);
- }
- } else {
- snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
- "0x%08x", etrack_id);
- }
-
- /* reset the hardware with the new settings */
- err = hw->mac.ops.start_hw(hw);
- if (err == IXGBE_ERR_EEPROM_VERSION) {
- /* We are running on a pre-production device, log a warning */
- e_dev_warn("This device is a pre-production adapter/LOM. "
- "Please be aware there may be issues associated "
- "with your hardware. If you are experiencing "
- "problems please contact your Intel or hardware "
- "representative who provided you with this "
- "hardware.\n");
- }
- /* pick up the PCI bus settings for reporting later */
- if (hw->mac.ops.get_bus_info)
- hw->mac.ops.get_bus_info(hw);
-
- strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
- *lad_dev = netdev;
-
- adapter->netdev_registered = true;
-#ifdef NO_VNIC
- /* power down the optics */
- if ((hw->phy.multispeed_fiber) ||
- ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
- (hw->mac.type == ixgbe_mac_82599EB)))
- ixgbe_disable_tx_laser(hw);
-
- /* carrier off reporting is important to ethtool even BEFORE open */
- netif_carrier_off(netdev);
- /* keep stopping all the transmit queues for older kernels */
- netif_tx_stop_all_queues(netdev);
-#endif
-
- /* print all messages at the end so that we use our eth%d name */
- /* print bus type/speed/width info */
- e_dev_info("(PCI Express:%s:%s) ",
- (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
- hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
- "Unknown"),
- (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
- hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
- hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
- "Unknown"));
-
- /* print the MAC address */
- for (i = 0; i < 6; i++)
- pr_cont("%2.2x%c", netdev->dev_addr[i], i == 5 ? '\n' : ':');
-
- /* First try to read PBA as a string */
- err = ixgbe_read_pba_string(hw, part_str, IXGBE_PBANUM_LENGTH);
- if (err)
- strlcpy(part_str, "Unknown", sizeof(part_str));
- if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
- e_info(probe, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
- hw->mac.type, hw->phy.type, hw->phy.sfp_type, part_str);
- else
- e_info(probe, "MAC: %d, PHY: %d, PBA No: %s\n",
- hw->mac.type, hw->phy.type, part_str);
-
- if (((hw->bus.speed == ixgbe_bus_speed_2500) &&
- (hw->bus.width <= ixgbe_bus_width_pcie_x4)) ||
- (hw->bus.width <= ixgbe_bus_width_pcie_x2)) {
- e_dev_warn("PCI-Express bandwidth available for this "
- "card is not sufficient for optimal "
- "performance.\n");
- e_dev_warn("For optimal performance a x8 PCI-Express "
- "slot is required.\n");
- }
-
-#define INFO_STRING_LEN 255
- info_string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
- if (!info_string) {
- e_err(probe, "allocation for info string failed\n");
- goto no_info_string;
- }
- count = 0;
- i_s_var = info_string;
- count += snprintf(i_s_var, INFO_STRING_LEN, "Enabled Features: ");
-
- i_s_var = info_string + count;
- count += snprintf(i_s_var, (INFO_STRING_LEN - count),
- "RxQ: %d TxQ: %d ", adapter->num_rx_queues,
- adapter->num_tx_queues);
- i_s_var = info_string + count;
-#ifdef IXGBE_FCOE
- if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
- count += snprintf(i_s_var, INFO_STRING_LEN - count, "FCoE ");
- i_s_var = info_string + count;
- }
-#endif
- if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
- count += snprintf(i_s_var, INFO_STRING_LEN - count,
- "FdirHash ");
- i_s_var = info_string + count;
- }
- if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
- count += snprintf(i_s_var, INFO_STRING_LEN - count,
- "FdirPerfect ");
- i_s_var = info_string + count;
- }
- if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
- count += snprintf(i_s_var, INFO_STRING_LEN - count, "DCB ");
- i_s_var = info_string + count;
- }
- if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
- count += snprintf(i_s_var, INFO_STRING_LEN - count, "RSS ");
- i_s_var = info_string + count;
- }
- if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
- count += snprintf(i_s_var, INFO_STRING_LEN - count, "DCA ");
- i_s_var = info_string + count;
- }
- if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
- count += snprintf(i_s_var, INFO_STRING_LEN - count, "RSC ");
- i_s_var = info_string + count;
- }
-#ifndef IXGBE_NO_LRO
- else if (netdev->features & NETIF_F_LRO) {
- count += snprintf(i_s_var, INFO_STRING_LEN - count, "LRO ");
- i_s_var = info_string + count;
- }
-#endif
-
- BUG_ON(i_s_var > (info_string + INFO_STRING_LEN));
- /* end features printing */
- e_info(probe, "%s\n", info_string);
- kfree(info_string);
-no_info_string:
-
- /* firmware requires blank driver version */
- ixgbe_set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF);
-
-#if defined(HAVE_NETDEV_STORAGE_ADDRESS) && defined(NETDEV_HW_ADDR_T_SAN)
- /* add san mac addr to netdev */
- //ixgbe_add_sanmac_netdev(netdev);
-
-#endif /* (HAVE_NETDEV_STORAGE_ADDRESS) && (NETDEV_HW_ADDR_T_SAN) */
- e_info(probe, "Intel(R) 10 Gigabit Network Connection\n");
- cards_found++;
-
-#ifdef IXGBE_SYSFS
- //if (ixgbe_sysfs_init(adapter))
- // e_err(probe, "failed to allocate sysfs resources\n");
-#else
-#ifdef IXGBE_PROCFS
- //if (ixgbe_procfs_init(adapter))
- // e_err(probe, "failed to allocate procfs resources\n");
-#endif /* IXGBE_PROCFS */
-#endif /* IXGBE_SYSFS */
-
- return 0;
-
-//err_register:
- //ixgbe_clear_interrupt_scheme(adapter);
- //ixgbe_release_hw_control(adapter);
-err_sw_init:
- adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
- if (adapter->mac_table)
- kfree(adapter->mac_table);
- iounmap(hw->hw_addr);
-err_ioremap:
- free_netdev(netdev);
-err_alloc_etherdev:
- //pci_release_selected_regions(pdev,
- // pci_select_bars(pdev, IORESOURCE_MEM));
-//err_pci_reg:
-//err_dma:
- pci_disable_device(pdev);
- return err;
-}
-
-/**
- * ixgbe_remove - Device Removal Routine
- * @pdev: PCI device information struct
- *
- * ixgbe_remove is called by the PCI subsystem to alert the driver
- * that it should release a PCI device. The could be caused by a
- * Hot-Plug event, or because the driver is going to be removed from
- * memory.
- **/
-void ixgbe_kni_remove(struct pci_dev *pdev)
-{
- pci_disable_device(pdev);
-}
-
-
-u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
-{
- u16 value;
- struct ixgbe_adapter *adapter = hw->back;
-
- pci_read_config_word(adapter->pdev, reg, &value);
- return value;
-}
-
-void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
-{
- struct ixgbe_adapter *adapter = hw->back;
-
- pci_write_config_word(adapter->pdev, reg, value);
-}
-
-void ewarn(struct ixgbe_hw *hw, const char *st, u32 status)
-{
- struct ixgbe_adapter *adapter = hw->back;
-
- netif_warn(adapter, drv, adapter->netdev, "%s", st);
-}
diff --git a/kernel/linux/kni/ethtool/ixgbe/ixgbe_mbx.h b/kernel/linux/kni/ethtool/ixgbe/ixgbe_mbx.h
deleted file mode 100644
index 53ace94..0000000
--- a/kernel/linux/kni/ethtool/ixgbe/ixgbe_mbx.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*******************************************************************************
-
- Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2012 Intel Corporation.
-
- Contact Information:
- e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
- Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-
-#ifndef _IXGBE_MBX_H_
-#define _IXGBE_MBX_H_
-
-#include "ixgbe_type.h"
-
-#define IXGBE_VFMAILBOX_SIZE 16 /* 16 32 bit words - 64 bytes */
-#define IXGBE_ERR_MBX -100
-
-#define IXGBE_VFMAILBOX 0x002FC
-#define IXGBE_VFMBMEM 0x00200
-
-/* Define mailbox register bits */
-#define IXGBE_VFMAILBOX_REQ 0x00000001 /* Request for PF Ready bit */
-#define IXGBE_VFMAILBOX_ACK 0x00000002 /* Ack PF message received */
-#define IXGBE_VFMAILBOX_VFU 0x00000004 /* VF owns the mailbox buffer */
-#define IXGBE_VFMAILBOX_PFU 0x00000008 /* PF owns the mailbox buffer */
-#define IXGBE_VFMAILBOX_PFSTS 0x00000010 /* PF wrote a message in the MB */
-#define IXGBE_VFMAILBOX_PFACK 0x00000020 /* PF ack the previous VF msg */
-#define IXGBE_VFMAILBOX_RSTI 0x00000040 /* PF has reset indication */
-#define IXGBE_VFMAILBOX_RSTD 0x00000080 /* PF has indicated reset done */
-#define IXGBE_VFMAILBOX_R2C_BITS 0x000000B0 /* All read to clear bits */
-
-#define IXGBE_PFMAILBOX_STS 0x00000001 /* Initiate message send to VF */
-#define IXGBE_PFMAILBOX_ACK 0x00000002 /* Ack message recv'd from VF */
-#define IXGBE_PFMAILBOX_VFU 0x00000004 /* VF owns the mailbox buffer */
-#define IXGBE_PFMAILBOX_PFU 0x00000008 /* PF owns the mailbox buffer */
-#define IXGBE_PFMAILBOX_RVFU 0x00000010 /* Reset VFU - used when VF stuck */
-
-#define IXGBE_MBVFICR_VFREQ_MASK 0x0000FFFF /* bits for VF messages */
-#define IXGBE_MBVFICR_VFREQ_VF1 0x00000001 /* bit for VF 1 message */
-#define IXGBE_MBVFICR_VFACK_MASK 0xFFFF0000 /* bits for VF acks */
-#define IXGBE_MBVFICR_VFACK_VF1 0x00010000 /* bit for VF 1 ack */
-
-
-/* If it's a IXGBE_VF_* msg then it originates in the VF and is sent to the
- * PF. The reverse is true if it is IXGBE_PF_*.
- * Message ACK's are the value or'd with 0xF0000000
- */
-#define IXGBE_VT_MSGTYPE_ACK 0x80000000 /* Messages below or'd with
- * this are the ACK */
-#define IXGBE_VT_MSGTYPE_NACK 0x40000000 /* Messages below or'd with
- * this are the NACK */
-#define IXGBE_VT_MSGTYPE_CTS 0x20000000 /* Indicates that VF is still
- * clear to send requests */
-#define IXGBE_VT_MSGINFO_SHIFT 16
-/* bits 23:16 are used for extra info for certain messages */
-#define IXGBE_VT_MSGINFO_MASK (0xFF << IXGBE_VT_MSGINFO_SHIFT)
-
-#define IXGBE_VF_RESET 0x01 /* VF requests reset */
-#define IXGBE_VF_SET_MAC_ADDR 0x02 /* VF requests PF to set MAC addr */
-#define IXGBE_VF_SET_MULTICAST 0x03 /* VF requests PF to set MC addr */
-#define IXGBE_VF_SET_VLAN 0x04 /* VF requests PF to set VLAN */
-#define IXGBE_VF_SET_LPE 0x05 /* VF requests PF to set VMOLR.LPE */
-#define IXGBE_VF_SET_MACVLAN 0x06 /* VF requests PF for unicast filter */
-
-/* length of permanent address message returned from PF */
-#define IXGBE_VF_PERMADDR_MSG_LEN 4
-/* word in permanent address message with the current multicast type */
-#define IXGBE_VF_MC_TYPE_WORD 3
-
-#define IXGBE_PF_CONTROL_MSG 0x0100 /* PF control message */
-
-
-#define IXGBE_VF_MBX_INIT_TIMEOUT 2000 /* number of retries on mailbox */
-#define IXGBE_VF_MBX_INIT_DELAY 500 /* microseconds between retries */
-
-s32 ixgbe_read_mbx(struct ixgbe_hw *, u32 *, u16, u16);
-s32 ixgbe_write_mbx(struct ixgbe_hw *, u32 *, u16, u16);
-s32 ixgbe_read_posted_mbx(struct ixgbe_hw *, u32 *, u16, u16);
-s32 ixgbe_write_posted_mbx(struct ixgbe_hw *, u32 *, u16, u16);
-s32 ixgbe_check_for_msg(struct ixgbe_hw *, u16);
-s32 ixgbe_check_for_ack(struct ixgbe_hw *, u16);
-s32 ixgbe_check_for_rst(struct ixgbe_hw *, u16);
-void ixgbe_init_mbx_ops_generic(struct ixgbe_hw *hw);
-void ixgbe_init_mbx_params_vf(struct ixgbe_hw *);
-void ixgbe_init_mbx_params_pf(struct ixgbe_hw *);
-
-#endif /* _IXGBE_MBX_H_ */
diff --git a/kernel/linux/kni/ethtool/ixgbe/ixgbe_osdep.h b/kernel/linux/kni/ethtool/ixgbe/ixgbe_osdep.h
deleted file mode 100644
index 7b3f8c5..0000000
--- a/kernel/linux/kni/ethtool/ixgbe/ixgbe_osdep.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*******************************************************************************
-
- Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2012 Intel Corporation.
-
- Contact Information:
- e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
- Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-
-
-/* glue for the OS independent part of ixgbe
- * includes register access macros
- */
-
-#ifndef _IXGBE_OSDEP_H_
-#define _IXGBE_OSDEP_H_
-
-#include <linux/pci.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/if_ether.h>
-#include <linux/sched.h>
-#include "kcompat.h"
-
-
-#ifndef msleep
-#define msleep(x) do { if (in_interrupt()) { \
- /* Don't mdelay in interrupt context! */ \
- BUG(); \
- } else { \
- msleep(x); \
- } } while (0)
-
-#endif
-
-#undef ASSERT
-
-#ifdef DBG
-#define hw_dbg(hw, S, A...) printk(KERN_DEBUG S, ## A)
-#else
-#define hw_dbg(hw, S, A...) do {} while (0)
-#endif
-
-#define e_dev_info(format, arg...) \
- dev_info(pci_dev_to_dev(adapter->pdev), format, ## arg)
-#define e_dev_warn(format, arg...) \
- dev_warn(pci_dev_to_dev(adapter->pdev), format, ## arg)
-#define e_dev_err(format, arg...) \
- dev_err(pci_dev_to_dev(adapter->pdev), format, ## arg)
-#define e_dev_notice(format, arg...) \
- dev_notice(pci_dev_to_dev(adapter->pdev), format, ## arg)
-#define e_info(msglvl, format, arg...) \
- netif_info(adapter, msglvl, adapter->netdev, format, ## arg)
-#define e_err(msglvl, format, arg...) \
- netif_err(adapter, msglvl, adapter->netdev, format, ## arg)
-#define e_warn(msglvl, format, arg...) \
- netif_warn(adapter, msglvl, adapter->netdev, format, ## arg)
-#define e_crit(msglvl, format, arg...) \
- netif_crit(adapter, msglvl, adapter->netdev, format, ## arg)
-
-
-#ifdef DBG
-#define IXGBE_WRITE_REG(a, reg, value) do {\
- switch (reg) { \
- case IXGBE_EIMS: \
- case IXGBE_EIMC: \
- case IXGBE_EIAM: \
- case IXGBE_EIAC: \
- case IXGBE_EICR: \
- case IXGBE_EICS: \
- printk("%s: Reg - 0x%05X, value - 0x%08X\n", __func__, \
- reg, (u32)(value)); \
- default: \
- break; \
- } \
- writel((value), ((a)->hw_addr + (reg))); \
-} while (0)
-#else
-#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
-#endif
-
-#define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
-
-#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) ( \
- writel((value), ((a)->hw_addr + (reg) + ((offset) << 2))))
-
-#define IXGBE_READ_REG_ARRAY(a, reg, offset) ( \
- readl((a)->hw_addr + (reg) + ((offset) << 2)))
-
-#ifndef writeq
-#define writeq(val, addr) do { writel((u32) (val), addr); \
- writel((u32) (val >> 32), (addr + 4)); \
- } while (0);
-#endif
-
-#define IXGBE_WRITE_REG64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))
-
-#define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
-struct ixgbe_hw;
-extern u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg);
-extern void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value);
-extern void ewarn(struct ixgbe_hw *hw, const char *str, u32 status);
-
-#define IXGBE_READ_PCIE_WORD ixgbe_read_pci_cfg_word
-#define IXGBE_WRITE_PCIE_WORD ixgbe_write_pci_cfg_word
-#define IXGBE_EEPROM_GRANT_ATTEMPS 100
-#define IXGBE_HTONL(_i) htonl(_i)
-#define IXGBE_NTOHL(_i) ntohl(_i)
-#define IXGBE_NTOHS(_i) ntohs(_i)
-#define IXGBE_CPU_TO_LE32(_i) cpu_to_le32(_i)
-#define IXGBE_LE32_TO_CPUS(_i) le32_to_cpus(_i)
-#define EWARN(H, W, S) ewarn(H, W, S)
-
-#endif /* _IXGBE_OSDEP_H_ */
diff --git a/kernel/linux/kni/ethtool/ixgbe/ixgbe_phy.c b/kernel/linux/kni/ethtool/ixgbe/ixgbe_phy.c
deleted file mode 100644
index a47a2ff..0000000
--- a/kernel/linux/kni/ethtool/ixgbe/ixgbe_phy.c
+++ /dev/null
@@ -1,1832 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*******************************************************************************
-
- Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2012 Intel Corporation.
-
- Contact Information:
- e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
- Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-
-#include "ixgbe_api.h"
-#include "ixgbe_common.h"
-#include "ixgbe_phy.h"
-
-static void ixgbe_i2c_start(struct ixgbe_hw *hw);
-static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
-static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
-static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
-static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
-static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
-static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
-static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
-static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
-static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
-static bool ixgbe_get_i2c_data(u32 *i2cctl);
-
-/**
- * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
- * @hw: pointer to the hardware structure
- *
- * Initialize the function pointers.
- **/
-s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
-{
- struct ixgbe_phy_info *phy = &hw->phy;
-
- /* PHY */
- phy->ops.identify = &ixgbe_identify_phy_generic;
- phy->ops.reset = &ixgbe_reset_phy_generic;
- phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
- phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
- phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
- phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
- phy->ops.check_link = NULL;
- phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
- phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
- phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
- phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
- phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
- phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
- phy->ops.identify_sfp = &ixgbe_identify_module_generic;
- phy->sfp_type = ixgbe_sfp_type_unknown;
- phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
- return 0;
-}
-
-/**
- * ixgbe_identify_phy_generic - Get physical layer module
- * @hw: pointer to hardware structure
- *
- * Determines the physical layer module found on the current adapter.
- **/
-s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
-{
- s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
- u32 phy_addr;
- u16 ext_ability = 0;
-
- if (hw->phy.type == ixgbe_phy_unknown) {
- for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
- if (ixgbe_validate_phy_addr(hw, phy_addr)) {
- hw->phy.addr = phy_addr;
- ixgbe_get_phy_id(hw);
- hw->phy.type =
- ixgbe_get_phy_type_from_id(hw->phy.id);
-
- if (hw->phy.type == ixgbe_phy_unknown) {
- hw->phy.ops.read_reg(hw,
- IXGBE_MDIO_PHY_EXT_ABILITY,
- IXGBE_MDIO_PMA_PMD_DEV_TYPE,
- &ext_ability);
- if (ext_ability &
- (IXGBE_MDIO_PHY_10GBASET_ABILITY |
- IXGBE_MDIO_PHY_1000BASET_ABILITY))
- hw->phy.type =
- ixgbe_phy_cu_unknown;
- else
- hw->phy.type =
- ixgbe_phy_generic;
- }
-
- status = 0;
- break;
- }
- }
- /* clear value if nothing found */
- if (status != 0)
- hw->phy.addr = 0;
- } else {
- status = 0;
- }
-
- return status;
-}
-
-/**
- * ixgbe_validate_phy_addr - Determines phy address is valid
- * @hw: pointer to hardware structure
- *
- **/
-bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
-{
- u16 phy_id = 0;
- bool valid = false;
-
- hw->phy.addr = phy_addr;
- hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
- IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
-
- if (phy_id != 0xFFFF && phy_id != 0x0)
- valid = true;
-
- return valid;
-}
-
-/**
- * ixgbe_get_phy_id - Get the phy type
- * @hw: pointer to hardware structure
- *
- **/
-s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
-{
- u32 status;
- u16 phy_id_high = 0;
- u16 phy_id_low = 0;
-
- status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
- IXGBE_MDIO_PMA_PMD_DEV_TYPE,
- &phy_id_high);
-
- if (status == 0) {
- hw->phy.id = (u32)(phy_id_high << 16);
- status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
- IXGBE_MDIO_PMA_PMD_DEV_TYPE,
- &phy_id_low);
- hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
- hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
- }
- return status;
-}
-
-/**
- * ixgbe_get_phy_type_from_id - Get the phy type
- * @hw: pointer to hardware structure
- *
- **/
-enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
-{
- enum ixgbe_phy_type phy_type;
-
- switch (phy_id) {
- case TN1010_PHY_ID:
- phy_type = ixgbe_phy_tn;
- break;
- case X540_PHY_ID:
- phy_type = ixgbe_phy_aq;
- break;
- case QT2022_PHY_ID:
- phy_type = ixgbe_phy_qt;
- break;
- case ATH_PHY_ID:
- phy_type = ixgbe_phy_nl;
- break;
- default:
- phy_type = ixgbe_phy_unknown;
- break;
- }
-
- hw_dbg(hw, "phy type found is %d\n", phy_type);
- return phy_type;
-}
-
-/**
- * ixgbe_reset_phy_generic - Performs a PHY reset
- * @hw: pointer to hardware structure
- **/
-s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
-{
- u32 i;
- u16 ctrl = 0;
- s32 status = 0;
-
- if (hw->phy.type == ixgbe_phy_unknown)
- status = ixgbe_identify_phy_generic(hw);
-
- if (status != 0 || hw->phy.type == ixgbe_phy_none)
- goto out;
-
- /* Don't reset PHY if it's shut down due to overtemp. */
- if (!hw->phy.reset_if_overtemp &&
- (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
- goto out;
-
- /*
- * Perform soft PHY reset to the PHY_XS.
- * This will cause a soft reset to the PHY
- */
- hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
- IXGBE_MDIO_PHY_XS_DEV_TYPE,
- IXGBE_MDIO_PHY_XS_RESET);
-
- /*
- * Poll for reset bit to self-clear indicating reset is complete.
- * Some PHYs could take up to 3 seconds to complete and need about
- * 1.7 usec delay after the reset is complete.
- */
- for (i = 0; i < 30; i++) {
- msleep(100);
- hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
- IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
- if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
- udelay(2);
- break;
- }
- }
-
- if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
- status = IXGBE_ERR_RESET_FAILED;
- hw_dbg(hw, "PHY reset polling failed to complete.\n");
- }
-
-out:
- return status;
-}
-
-/**
- * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
- * @hw: pointer to hardware structure
- * @reg_addr: 32 bit address of PHY register to read
- * @phy_data: Pointer to read data from PHY register
- **/
-s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
- u32 device_type, u16 *phy_data)
-{
- u32 command;
- u32 i;
- u32 data;
- s32 status = 0;
- u16 gssr;
-
- if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
- gssr = IXGBE_GSSR_PHY1_SM;
- else
- gssr = IXGBE_GSSR_PHY0_SM;
-
- if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
- status = IXGBE_ERR_SWFW_SYNC;
-
- if (status == 0) {
- /* Setup and write the address cycle command */
- command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
- (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
- (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
- (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
-
- IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
-
- /*
- * Check every 10 usec to see if the address cycle completed.
- * The MDI Command bit will clear when the operation is
- * complete
- */
- for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
- udelay(10);
-
- command = IXGBE_READ_REG(hw, IXGBE_MSCA);
-
- if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
- break;
- }
-
- if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
- hw_dbg(hw, "PHY address command did not complete.\n");
- status = IXGBE_ERR_PHY;
- }
-
- if (status == 0) {
- /*
- * Address cycle complete, setup and write the read
- * command
- */
- command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
- (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
- (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
- (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
-
- IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
-
- /*
- * Check every 10 usec to see if the address cycle
- * completed. The MDI Command bit will clear when the
- * operation is complete
- */
- for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
- udelay(10);
-
- command = IXGBE_READ_REG(hw, IXGBE_MSCA);
-
- if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
- break;
- }
-
- if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
- hw_dbg(hw, "PHY read command didn't complete\n");
- status = IXGBE_ERR_PHY;
- } else {
- /*
- * Read operation is complete. Get the data
- * from MSRWD
- */
- data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
- data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
- *phy_data = (u16)(data);
- }
- }
-
- hw->mac.ops.release_swfw_sync(hw, gssr);
- }
-
- return status;
-}
-
-/**
- * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
- * @hw: pointer to hardware structure
- * @reg_addr: 32 bit PHY register to write
- * @device_type: 5 bit device type
- * @phy_data: Data to write to the PHY register
- **/
-s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
- u32 device_type, u16 phy_data)
-{
- u32 command;
- u32 i;
- s32 status = 0;
- u16 gssr;
-
- if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
- gssr = IXGBE_GSSR_PHY1_SM;
- else
- gssr = IXGBE_GSSR_PHY0_SM;
-
- if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
- status = IXGBE_ERR_SWFW_SYNC;
-
- if (status == 0) {
- /* Put the data in the MDI single read and write data register*/
- IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
-
- /* Setup and write the address cycle command */
- command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
- (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
- (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
- (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
-
- IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
-
- /*
- * Check every 10 usec to see if the address cycle completed.
- * The MDI Command bit will clear when the operation is
- * complete
- */
- for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
- udelay(10);
-
- command = IXGBE_READ_REG(hw, IXGBE_MSCA);
-
- if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
- break;
- }
-
- if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
- hw_dbg(hw, "PHY address cmd didn't complete\n");
- status = IXGBE_ERR_PHY;
- }
-
- if (status == 0) {
- /*
- * Address cycle complete, setup and write the write
- * command
- */
- command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
- (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
- (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
- (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
-
- IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
-
- /*
- * Check every 10 usec to see if the address cycle
- * completed. The MDI Command bit will clear when the
- * operation is complete
- */
- for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
- udelay(10);
-
- command = IXGBE_READ_REG(hw, IXGBE_MSCA);
-
- if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
- break;
- }
-
- if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
- hw_dbg(hw, "PHY address cmd didn't complete\n");
- status = IXGBE_ERR_PHY;
- }
- }
-
- hw->mac.ops.release_swfw_sync(hw, gssr);
- }
-
- return status;
-}
-
-/**
- * ixgbe_setup_phy_link_generic - Set and restart autoneg
- * @hw: pointer to hardware structure
- *
- * Restart autonegotiation and PHY and waits for completion.
- **/
-s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
-{
- s32 status = 0;
- u32 time_out;
- u32 max_time_out = 10;
- u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
- bool autoneg = false;
- ixgbe_link_speed speed;
-
- ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
-
- if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
- /* Set or unset auto-negotiation 10G advertisement */
- hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- &autoneg_reg);
-
- autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
- if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
- autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
-
- hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- autoneg_reg);
- }
-
- if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
- /* Set or unset auto-negotiation 1G advertisement */
- hw->phy.ops.read_reg(hw,
- IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- &autoneg_reg);
-
- autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
- if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
- autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
-
- hw->phy.ops.write_reg(hw,
- IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- autoneg_reg);
- }
-
- if (speed & IXGBE_LINK_SPEED_100_FULL) {
- /* Set or unset auto-negotiation 100M advertisement */
- hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- &autoneg_reg);
-
- autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
- IXGBE_MII_100BASE_T_ADVERTISE_HALF);
- if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
- autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
-
- hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- autoneg_reg);
- }
-
- /* Restart PHY autonegotiation and wait for completion */
- hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
-
- autoneg_reg |= IXGBE_MII_RESTART;
-
- hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
-
- /* Wait for autonegotiation to finish */
- for (time_out = 0; time_out < max_time_out; time_out++) {
- udelay(10);
- /* Restart PHY autonegotiation and wait for completion */
- status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- &autoneg_reg);
-
- autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
- if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
- break;
- }
-
- if (time_out == max_time_out) {
- status = IXGBE_ERR_LINK_SETUP;
- hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out");
- }
-
- return status;
-}
-
-/**
- * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg: true if autonegotiation enabled
- **/
-s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
- ixgbe_link_speed speed,
- bool autoneg,
- bool autoneg_wait_to_complete)
-{
-
- /*
- * Clear autoneg_advertised and set new values based on input link
- * speed.
- */
- hw->phy.autoneg_advertised = 0;
-
- if (speed & IXGBE_LINK_SPEED_10GB_FULL)
- hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
-
- if (speed & IXGBE_LINK_SPEED_1GB_FULL)
- hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
-
- if (speed & IXGBE_LINK_SPEED_100_FULL)
- hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
-
- /* Setup link based on the new speed settings */
- hw->phy.ops.setup_link(hw);
-
- return 0;
-}
-
-/**
- * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
- * @hw: pointer to hardware structure
- * @speed: pointer to link speed
- * @autoneg: boolean auto-negotiation value
- *
- * Determines the link capabilities by reading the AUTOC register.
- **/
-s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed,
- bool *autoneg)
-{
- s32 status = IXGBE_ERR_LINK_SETUP;
- u16 speed_ability;
-
- *speed = 0;
- *autoneg = true;
-
- status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
- IXGBE_MDIO_PMA_PMD_DEV_TYPE,
- &speed_ability);
-
- if (status == 0) {
- if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
- *speed |= IXGBE_LINK_SPEED_10GB_FULL;
- if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
- *speed |= IXGBE_LINK_SPEED_1GB_FULL;
- if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
- *speed |= IXGBE_LINK_SPEED_100_FULL;
- }
-
- return status;
-}
-
-/**
- * ixgbe_check_phy_link_tnx - Determine link and speed status
- * @hw: pointer to hardware structure
- *
- * Reads the VS1 register to determine if link is up and the current speed for
- * the PHY.
- **/
-s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
- bool *link_up)
-{
- s32 status = 0;
- u32 time_out;
- u32 max_time_out = 10;
- u16 phy_link = 0;
- u16 phy_speed = 0;
- u16 phy_data = 0;
-
- /* Initialize speed and link to default case */
- *link_up = false;
- *speed = IXGBE_LINK_SPEED_10GB_FULL;
-
- /*
- * Check current speed and link status of the PHY register.
- * This is a vendor specific register and may have to
- * be changed for other copper PHYs.
- */
- for (time_out = 0; time_out < max_time_out; time_out++) {
- udelay(10);
- status = hw->phy.ops.read_reg(hw,
- IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
- IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
- &phy_data);
- phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
- phy_speed = phy_data &
- IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
- if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
- *link_up = true;
- if (phy_speed ==
- IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
- *speed = IXGBE_LINK_SPEED_1GB_FULL;
- break;
- }
- }
-
- return status;
-}
-
-/**
- * ixgbe_setup_phy_link_tnx - Set and restart autoneg
- * @hw: pointer to hardware structure
- *
- * Restart autonegotiation and PHY and waits for completion.
- **/
-s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
-{
- s32 status = 0;
- u32 time_out;
- u32 max_time_out = 10;
- u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
- bool autoneg = false;
- ixgbe_link_speed speed;
-
- ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
-
- if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
- /* Set or unset auto-negotiation 10G advertisement */
- hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- &autoneg_reg);
-
- autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
- if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
- autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
-
- hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- autoneg_reg);
- }
-
- if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
- /* Set or unset auto-negotiation 1G advertisement */
- hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- &autoneg_reg);
-
- autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
- if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
- autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
-
- hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- autoneg_reg);
- }
-
- if (speed & IXGBE_LINK_SPEED_100_FULL) {
- /* Set or unset auto-negotiation 100M advertisement */
- hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- &autoneg_reg);
-
- autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
- if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
- autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
-
- hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- autoneg_reg);
- }
-
- /* Restart PHY autonegotiation and wait for completion */
- hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
-
- autoneg_reg |= IXGBE_MII_RESTART;
-
- hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
-
- /* Wait for autonegotiation to finish */
- for (time_out = 0; time_out < max_time_out; time_out++) {
- udelay(10);
- /* Restart PHY autonegotiation and wait for completion */
- status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
- &autoneg_reg);
-
- autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
- if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
- break;
- }
-
- if (time_out == max_time_out) {
- status = IXGBE_ERR_LINK_SETUP;
- hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out");
- }
-
- return status;
-}
-
-/**
- * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
- * @hw: pointer to hardware structure
- * @firmware_version: pointer to the PHY Firmware Version
- **/
-s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
- u16 *firmware_version)
-{
- s32 status = 0;
-
- status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
- IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
- firmware_version);
-
- return status;
-}
-
-/**
- * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
- * @hw: pointer to hardware structure
- * @firmware_version: pointer to the PHY Firmware Version
- **/
-s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
- u16 *firmware_version)
-{
- s32 status = 0;
-
- status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
- IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
- firmware_version);
-
- return status;
-}
-
-/**
- * ixgbe_reset_phy_nl - Performs a PHY reset
- * @hw: pointer to hardware structure
- **/
-s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
-{
- u16 phy_offset, control, eword, edata, block_crc;
- bool end_data = false;
- u16 list_offset, data_offset;
- u16 phy_data = 0;
- s32 ret_val = 0;
- u32 i;
-
- hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
- IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
-
- /* reset the PHY and poll for completion */
- hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
- IXGBE_MDIO_PHY_XS_DEV_TYPE,
- (phy_data | IXGBE_MDIO_PHY_XS_RESET));
-
- for (i = 0; i < 100; i++) {
- hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
- IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
- if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
- break;
- msleep(10);
- }
-
- if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
- hw_dbg(hw, "PHY reset did not complete.\n");
- ret_val = IXGBE_ERR_PHY;
- goto out;
- }
-
- /* Get init offsets */
- ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
- &data_offset);
- if (ret_val != 0)
- goto out;
-
- ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
- data_offset++;
- while (!end_data) {
- /*
- * Read control word from PHY init contents offset
- */
- ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
- control = (eword & IXGBE_CONTROL_MASK_NL) >>
- IXGBE_CONTROL_SHIFT_NL;
- edata = eword & IXGBE_DATA_MASK_NL;
- switch (control) {
- case IXGBE_DELAY_NL:
- data_offset++;
- hw_dbg(hw, "DELAY: %d MS\n", edata);
- msleep(edata);
- break;
- case IXGBE_DATA_NL:
- hw_dbg(hw, "DATA:\n");
- data_offset++;
- hw->eeprom.ops.read(hw, data_offset++,
- &phy_offset);
- for (i = 0; i < edata; i++) {
- hw->eeprom.ops.read(hw, data_offset, &eword);
- hw->phy.ops.write_reg(hw, phy_offset,
- IXGBE_TWINAX_DEV, eword);
- hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
- phy_offset);
- data_offset++;
- phy_offset++;
- }
- break;
- case IXGBE_CONTROL_NL:
- data_offset++;
- hw_dbg(hw, "CONTROL:\n");
- if (edata == IXGBE_CONTROL_EOL_NL) {
- hw_dbg(hw, "EOL\n");
- end_data = true;
- } else if (edata == IXGBE_CONTROL_SOL_NL) {
- hw_dbg(hw, "SOL\n");
- } else {
- hw_dbg(hw, "Bad control value\n");
- ret_val = IXGBE_ERR_PHY;
- goto out;
- }
- break;
- default:
- hw_dbg(hw, "Bad control type\n");
- ret_val = IXGBE_ERR_PHY;
- goto out;
- }
- }
-
-out:
- return ret_val;
-}
-
-/**
- * ixgbe_identify_module_generic - Identifies module type
- * @hw: pointer to hardware structure
- *
- * Determines HW type and calls appropriate function.
- **/
-s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
-{
- s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
-
- switch (hw->mac.ops.get_media_type(hw)) {
- case ixgbe_media_type_fiber:
- status = ixgbe_identify_sfp_module_generic(hw);
- break;
-
- case ixgbe_media_type_fiber_qsfp:
- status = ixgbe_identify_qsfp_module_generic(hw);
- break;
-
- default:
- hw->phy.sfp_type = ixgbe_sfp_type_not_present;
- status = IXGBE_ERR_SFP_NOT_PRESENT;
- break;
- }
-
- return status;
-}
-
-/**
- * ixgbe_identify_sfp_module_generic - Identifies SFP modules
- * @hw: pointer to hardware structure
- *
- * Searches for and identifies the SFP module and assigns appropriate PHY type.
- **/
-s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
-{
- s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
- u32 vendor_oui = 0;
- enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
- u8 identifier = 0;
- u8 comp_codes_1g = 0;
- u8 comp_codes_10g = 0;
- u8 oui_bytes[3] = {0, 0, 0};
- u8 cable_tech = 0;
- u8 cable_spec = 0;
- u16 enforce_sfp = 0;
-
- if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
- hw->phy.sfp_type = ixgbe_sfp_type_not_present;
- status = IXGBE_ERR_SFP_NOT_PRESENT;
- goto out;
- }
-
- status = hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_IDENTIFIER,
- &identifier);
-
- if (status == IXGBE_ERR_SWFW_SYNC ||
- status == IXGBE_ERR_I2C ||
- status == IXGBE_ERR_SFP_NOT_PRESENT)
- goto err_read_i2c_eeprom;
-
- /* LAN ID is needed for sfp_type determination */
- hw->mac.ops.set_lan_id(hw);
-
- if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
- hw->phy.type = ixgbe_phy_sfp_unsupported;
- status = IXGBE_ERR_SFP_NOT_SUPPORTED;
- } else {
- status = hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_1GBE_COMP_CODES,
- &comp_codes_1g);
-
- if (status == IXGBE_ERR_SWFW_SYNC ||
- status == IXGBE_ERR_I2C ||
- status == IXGBE_ERR_SFP_NOT_PRESENT)
- goto err_read_i2c_eeprom;
-
- status = hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_10GBE_COMP_CODES,
- &comp_codes_10g);
-
- if (status == IXGBE_ERR_SWFW_SYNC ||
- status == IXGBE_ERR_I2C ||
- status == IXGBE_ERR_SFP_NOT_PRESENT)
- goto err_read_i2c_eeprom;
- status = hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_CABLE_TECHNOLOGY,
- &cable_tech);
-
- if (status == IXGBE_ERR_SWFW_SYNC ||
- status == IXGBE_ERR_I2C ||
- status == IXGBE_ERR_SFP_NOT_PRESENT)
- goto err_read_i2c_eeprom;
-
- /* ID Module
- * =========
- * 0 SFP_DA_CU
- * 1 SFP_SR
- * 2 SFP_LR
- * 3 SFP_DA_CORE0 - 82599-specific
- * 4 SFP_DA_CORE1 - 82599-specific
- * 5 SFP_SR/LR_CORE0 - 82599-specific
- * 6 SFP_SR/LR_CORE1 - 82599-specific
- * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
- * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
- * 9 SFP_1g_cu_CORE0 - 82599-specific
- * 10 SFP_1g_cu_CORE1 - 82599-specific
- * 11 SFP_1g_sx_CORE0 - 82599-specific
- * 12 SFP_1g_sx_CORE1 - 82599-specific
- */
- if (hw->mac.type == ixgbe_mac_82598EB) {
- if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
- hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
- else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
- hw->phy.sfp_type = ixgbe_sfp_type_sr;
- else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
- hw->phy.sfp_type = ixgbe_sfp_type_lr;
- else
- hw->phy.sfp_type = ixgbe_sfp_type_unknown;
- } else if (hw->mac.type == ixgbe_mac_82599EB) {
- if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
- if (hw->bus.lan_id == 0)
- hw->phy.sfp_type =
- ixgbe_sfp_type_da_cu_core0;
- else
- hw->phy.sfp_type =
- ixgbe_sfp_type_da_cu_core1;
- } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
- hw->phy.ops.read_i2c_eeprom(
- hw, IXGBE_SFF_CABLE_SPEC_COMP,
- &cable_spec);
- if (cable_spec &
- IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
- if (hw->bus.lan_id == 0)
- hw->phy.sfp_type =
- ixgbe_sfp_type_da_act_lmt_core0;
- else
- hw->phy.sfp_type =
- ixgbe_sfp_type_da_act_lmt_core1;
- } else {
- hw->phy.sfp_type =
- ixgbe_sfp_type_unknown;
- }
- } else if (comp_codes_10g &
- (IXGBE_SFF_10GBASESR_CAPABLE |
- IXGBE_SFF_10GBASELR_CAPABLE)) {
- if (hw->bus.lan_id == 0)
- hw->phy.sfp_type =
- ixgbe_sfp_type_srlr_core0;
- else
- hw->phy.sfp_type =
- ixgbe_sfp_type_srlr_core1;
- } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
- if (hw->bus.lan_id == 0)
- hw->phy.sfp_type =
- ixgbe_sfp_type_1g_cu_core0;
- else
- hw->phy.sfp_type =
- ixgbe_sfp_type_1g_cu_core1;
- } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
- if (hw->bus.lan_id == 0)
- hw->phy.sfp_type =
- ixgbe_sfp_type_1g_sx_core0;
- else
- hw->phy.sfp_type =
- ixgbe_sfp_type_1g_sx_core1;
- } else {
- hw->phy.sfp_type = ixgbe_sfp_type_unknown;
- }
- }
-
- if (hw->phy.sfp_type != stored_sfp_type)
- hw->phy.sfp_setup_needed = true;
-
- /* Determine if the SFP+ PHY is dual speed or not. */
- hw->phy.multispeed_fiber = false;
- if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
- (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
- ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
- (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
- hw->phy.multispeed_fiber = true;
-
- /* Determine PHY vendor */
- if (hw->phy.type != ixgbe_phy_nl) {
- hw->phy.id = identifier;
- status = hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_VENDOR_OUI_BYTE0,
- &oui_bytes[0]);
-
- if (status == IXGBE_ERR_SWFW_SYNC ||
- status == IXGBE_ERR_I2C ||
- status == IXGBE_ERR_SFP_NOT_PRESENT)
- goto err_read_i2c_eeprom;
-
- status = hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_VENDOR_OUI_BYTE1,
- &oui_bytes[1]);
-
- if (status == IXGBE_ERR_SWFW_SYNC ||
- status == IXGBE_ERR_I2C ||
- status == IXGBE_ERR_SFP_NOT_PRESENT)
- goto err_read_i2c_eeprom;
-
- status = hw->phy.ops.read_i2c_eeprom(hw,
- IXGBE_SFF_VENDOR_OUI_BYTE2,
- &oui_bytes[2]);
-
- if (status == IXGBE_ERR_SWFW_SYNC ||
- status == IXGBE_ERR_I2C ||
- status == IXGBE_ERR_SFP_NOT_PRESENT)
- goto err_read_i2c_eeprom;
-
- vendor_oui =
- ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
- (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
- (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
-
- switch (vendor_oui) {
- case IXGBE_SFF_VENDOR_OUI_TYCO:
- if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
- hw->phy.type =
- ixgbe_phy_sfp_passive_tyco;
- break;
- case IXGBE_SFF_VENDOR_OUI_FTL:
- if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
- hw->phy.type = ixgbe_phy_sfp_ftl_active;
- else
- hw->phy.type = ixgbe_phy_sfp_ftl;
- break;
- case IXGBE_SFF_VENDOR_OUI_AVAGO:
- hw->phy.type = ixgbe_phy_sfp_avago;
- break;
- case IXGBE_SFF_VENDOR_OUI_INTEL:
- hw->phy.type = ixgbe_phy_sfp_intel;
- break;
- default:
- if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
- hw->phy.type =
- ixgbe_phy_sfp_passive_unknown;
- else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
- hw->phy.type =
- ixgbe_phy_sfp_active_unknown;
- else
- hw->phy.type = ixgbe_phy_sfp_unknown;
- break;
- }
- }
-
- /* Allow any DA cable vendor */
- if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
- IXGBE_SFF_DA_ACTIVE_CABLE)) {
- status = 0;
- goto out;
- }
-
- /* Verify supported 1G SFP modules */
- if (comp_codes_10g == 0 &&
- !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
- hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
- hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
- hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
- hw->phy.type = ixgbe_phy_sfp_unsupported;
- status = IXGBE_ERR_SFP_NOT_SUPPORTED;
- goto out;
- }
-
- /* Anything else 82598-based is supported */
- if (hw->mac.type == ixgbe_mac_82598EB) {
- status = 0;
- goto out;
- }
-
- ixgbe_get_device_caps(hw, &enforce_sfp);
- if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
- !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
- (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||
- (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0) ||
- (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) {
- /* Make sure we're a supported PHY type */
- if (hw->phy.type == ixgbe_phy_sfp_intel) {
- status = 0;
- } else {
- if (hw->allow_unsupported_sfp == true) {
- EWARN(hw, "WARNING: Intel (R) Network "
- "Connections are quality tested "
- "using Intel (R) Ethernet Optics."
- " Using untested modules is not "
- "supported and may cause unstable"
- " operation or damage to the "
- "module or the adapter. Intel "
- "Corporation is not responsible "
- "for any harm caused by using "
- "untested modules.\n", status);
- status = 0;
- } else {
- hw_dbg(hw, "SFP+ module not supported\n");
- hw->phy.type =
- ixgbe_phy_sfp_unsupported;
- status = IXGBE_ERR_SFP_NOT_SUPPORTED;
- }
- }
- } else {
- status = 0;
- }
- }
-
-out:
- return status;
-
-err_read_i2c_eeprom:
- hw->phy.sfp_type = ixgbe_sfp_type_not_present;
- if (hw->phy.type != ixgbe_phy_nl) {
- hw->phy.id = 0;
- hw->phy.type = ixgbe_phy_unknown;
- }
- return IXGBE_ERR_SFP_NOT_PRESENT;
-}
-
-/**
- * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
- * @hw: pointer to hardware structure
- *
- * Searches for and identifies the QSFP module and assigns appropriate PHY type
- **/
-s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
-{
- s32 status = 0;
-
- if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
- hw->phy.sfp_type = ixgbe_sfp_type_not_present;
- status = IXGBE_ERR_SFP_NOT_PRESENT;
- }
-
- return status;
-}
-
-
-/**
- * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
- * @hw: pointer to hardware structure
- * @list_offset: offset to the SFP ID list
- * @data_offset: offset to the SFP data block
- *
- * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
- * so it returns the offsets to the phy init sequence block.
- **/
-s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
- u16 *list_offset,
- u16 *data_offset)
-{
- u16 sfp_id;
- u16 sfp_type = hw->phy.sfp_type;
-
- if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
- return IXGBE_ERR_SFP_NOT_SUPPORTED;
-
- if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
- return IXGBE_ERR_SFP_NOT_PRESENT;
-
- if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
- (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
- return IXGBE_ERR_SFP_NOT_SUPPORTED;
-
- /*
- * Limiting active cables and 1G Phys must be initialized as
- * SR modules
- */
- if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
- sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
- sfp_type == ixgbe_sfp_type_1g_sx_core0)
- sfp_type = ixgbe_sfp_type_srlr_core0;
- else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
- sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
- sfp_type == ixgbe_sfp_type_1g_sx_core1)
- sfp_type = ixgbe_sfp_type_srlr_core1;
-
- /* Read offset to PHY init contents */
- hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
-
- if ((!*list_offset) || (*list_offset == 0xFFFF))
- return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
-
- /* Shift offset to first ID word */
- (*list_offset)++;
-
- /*
- * Find the matching SFP ID in the EEPROM
- * and program the init sequence
- */
- hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
-
- while (sfp_id != IXGBE_PHY_INIT_END_NL) {
- if (sfp_id == sfp_type) {
- (*list_offset)++;
- hw->eeprom.ops.read(hw, *list_offset, data_offset);
- if ((!*data_offset) || (*data_offset == 0xFFFF)) {
- hw_dbg(hw, "SFP+ module not supported\n");
- return IXGBE_ERR_SFP_NOT_SUPPORTED;
- } else {
- break;
- }
- } else {
- (*list_offset) += 2;
- if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
- return IXGBE_ERR_PHY;
- }
- }
-
- if (sfp_id == IXGBE_PHY_INIT_END_NL) {
- hw_dbg(hw, "No matching SFP+ module found\n");
- return IXGBE_ERR_SFP_NOT_SUPPORTED;
- }
-
- return 0;
-}
-
-/**
- * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
- * @hw: pointer to hardware structure
- * @byte_offset: EEPROM byte offset to read
- * @eeprom_data: value read
- *
- * Performs byte read operation to SFP module's EEPROM over I2C interface.
- **/
-s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
- u8 *eeprom_data)
-{
- return hw->phy.ops.read_i2c_byte(hw, byte_offset,
- IXGBE_I2C_EEPROM_DEV_ADDR,
- eeprom_data);
-}
-
-/**
- * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
- * @hw: pointer to hardware structure
- * @byte_offset: EEPROM byte offset to write
- * @eeprom_data: value to write
- *
- * Performs byte write operation to SFP module's EEPROM over I2C interface.
- **/
-s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
- u8 eeprom_data)
-{
- return hw->phy.ops.write_i2c_byte(hw, byte_offset,
- IXGBE_I2C_EEPROM_DEV_ADDR,
- eeprom_data);
-}
-
-/**
- * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
- * @hw: pointer to hardware structure
- * @byte_offset: byte offset to read
- * @data: value read
- *
- * Performs byte read operation to SFP module's EEPROM over I2C interface at
- * a specified device address.
- **/
-s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
- u8 dev_addr, u8 *data)
-{
- s32 status = 0;
- u32 max_retry = 10;
- u32 retry = 0;
- u16 swfw_mask = 0;
- bool nack = 1;
- *data = 0;
-
- if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
- swfw_mask = IXGBE_GSSR_PHY1_SM;
- else
- swfw_mask = IXGBE_GSSR_PHY0_SM;
-
- do {
- if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
- != 0) {
- status = IXGBE_ERR_SWFW_SYNC;
- goto read_byte_out;
- }
-
- ixgbe_i2c_start(hw);
-
- /* Device Address and write indication */
- status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
- if (status != 0)
- goto fail;
-
- status = ixgbe_get_i2c_ack(hw);
- if (status != 0)
- goto fail;
-
- status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
- if (status != 0)
- goto fail;
-
- status = ixgbe_get_i2c_ack(hw);
- if (status != 0)
- goto fail;
-
- ixgbe_i2c_start(hw);
-
- /* Device Address and read indication */
- status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
- if (status != 0)
- goto fail;
-
- status = ixgbe_get_i2c_ack(hw);
- if (status != 0)
- goto fail;
-
- status = ixgbe_clock_in_i2c_byte(hw, data);
- if (status != 0)
- goto fail;
-
- status = ixgbe_clock_out_i2c_bit(hw, nack);
- if (status != 0)
- goto fail;
-
- ixgbe_i2c_stop(hw);
- break;
-
-fail:
- hw->mac.ops.release_swfw_sync(hw, swfw_mask);
- msleep(100);
- ixgbe_i2c_bus_clear(hw);
- retry++;
- if (retry < max_retry)
- hw_dbg(hw, "I2C byte read error - Retrying.\n");
- else
- hw_dbg(hw, "I2C byte read error.\n");
-
- } while (retry < max_retry);
-
- hw->mac.ops.release_swfw_sync(hw, swfw_mask);
-
-read_byte_out:
- return status;
-}
-
-/**
- * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
- * @hw: pointer to hardware structure
- * @byte_offset: byte offset to write
- * @data: value to write
- *
- * Performs byte write operation to SFP module's EEPROM over I2C interface at
- * a specified device address.
- **/
-s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
- u8 dev_addr, u8 data)
-{
- s32 status = 0;
- u32 max_retry = 1;
- u32 retry = 0;
- u16 swfw_mask = 0;
-
- if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
- swfw_mask = IXGBE_GSSR_PHY1_SM;
- else
- swfw_mask = IXGBE_GSSR_PHY0_SM;
-
- if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
- status = IXGBE_ERR_SWFW_SYNC;
- goto write_byte_out;
- }
-
- do {
- ixgbe_i2c_start(hw);
-
- status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
- if (status != 0)
- goto fail;
-
- status = ixgbe_get_i2c_ack(hw);
- if (status != 0)
- goto fail;
-
- status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
- if (status != 0)
- goto fail;
-
- status = ixgbe_get_i2c_ack(hw);
- if (status != 0)
- goto fail;
-
- status = ixgbe_clock_out_i2c_byte(hw, data);
- if (status != 0)
- goto fail;
-
- status = ixgbe_get_i2c_ack(hw);
- if (status != 0)
- goto fail;
-
- ixgbe_i2c_stop(hw);
- break;
-
-fail:
- ixgbe_i2c_bus_clear(hw);
- retry++;
- if (retry < max_retry)
- hw_dbg(hw, "I2C byte write error - Retrying.\n");
- else
- hw_dbg(hw, "I2C byte write error.\n");
- } while (retry < max_retry);
-
- hw->mac.ops.release_swfw_sync(hw, swfw_mask);
-
-write_byte_out:
- return status;
-}
-
-/**
- * ixgbe_i2c_start - Sets I2C start condition
- * @hw: pointer to hardware structure
- *
- * Sets I2C start condition (High -> Low on SDA while SCL is High)
- **/
-static void ixgbe_i2c_start(struct ixgbe_hw *hw)
-{
- u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
-
- /* Start condition must begin with data and clock high */
- ixgbe_set_i2c_data(hw, &i2cctl, 1);
- ixgbe_raise_i2c_clk(hw, &i2cctl);
-
- /* Setup time for start condition (4.7us) */
- udelay(IXGBE_I2C_T_SU_STA);
-
- ixgbe_set_i2c_data(hw, &i2cctl, 0);
-
- /* Hold time for start condition (4us) */
- udelay(IXGBE_I2C_T_HD_STA);
-
- ixgbe_lower_i2c_clk(hw, &i2cctl);
-
- /* Minimum low period of clock is 4.7 us */
- udelay(IXGBE_I2C_T_LOW);
-
-}
-
-/**
- * ixgbe_i2c_stop - Sets I2C stop condition
- * @hw: pointer to hardware structure
- *
- * Sets I2C stop condition (Low -> High on SDA while SCL is High)
- **/
-static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
-{
- u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
-
- /* Stop condition must begin with data low and clock high */
- ixgbe_set_i2c_data(hw, &i2cctl, 0);
- ixgbe_raise_i2c_clk(hw, &i2cctl);
-
- /* Setup time for stop condition (4us) */
- udelay(IXGBE_I2C_T_SU_STO);
-
- ixgbe_set_i2c_data(hw, &i2cctl, 1);
-
- /* bus free time between stop and start (4.7us)*/
- udelay(IXGBE_I2C_T_BUF);
-}
-
-/**
- * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
- * @hw: pointer to hardware structure
- * @data: data byte to clock in
- *
- * Clocks in one byte data via I2C data/clock
- **/
-static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
-{
- s32 i;
- bool bit = 0;
-
- for (i = 7; i >= 0; i--) {
- ixgbe_clock_in_i2c_bit(hw, &bit);
- *data |= bit << i;
- }
-
- return 0;
-}
-
-/**
- * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
- * @hw: pointer to hardware structure
- * @data: data byte clocked out
- *
- * Clocks out one byte data via I2C data/clock
- **/
-static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
-{
- s32 status = 0;
- s32 i;
- u32 i2cctl;
- bool bit = 0;
-
- for (i = 7; i >= 0; i--) {
- bit = (data >> i) & 0x1;
- status = ixgbe_clock_out_i2c_bit(hw, bit);
-
- if (status != 0)
- break;
- }
-
- /* Release SDA line (set high) */
- i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
- i2cctl |= IXGBE_I2C_DATA_OUT;
- IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
- IXGBE_WRITE_FLUSH(hw);
-
- return status;
-}
-
-/**
- * ixgbe_get_i2c_ack - Polls for I2C ACK
- * @hw: pointer to hardware structure
- *
- * Clocks in/out one bit via I2C data/clock
- **/
-static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
-{
- s32 status = 0;
- u32 i = 0;
- u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
- u32 timeout = 10;
- bool ack = 1;
-
- ixgbe_raise_i2c_clk(hw, &i2cctl);
-
-
- /* Minimum high period of clock is 4us */
- udelay(IXGBE_I2C_T_HIGH);
-
- /* Poll for ACK. Note that ACK in I2C spec is
- * transition from 1 to 0 */
- for (i = 0; i < timeout; i++) {
- i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
- ack = ixgbe_get_i2c_data(&i2cctl);
-
- udelay(1);
- if (ack == 0)
- break;
- }
-
- if (ack == 1) {
- hw_dbg(hw, "I2C ack was not received.\n");
- status = IXGBE_ERR_I2C;
- }
-
- ixgbe_lower_i2c_clk(hw, &i2cctl);
-
- /* Minimum low period of clock is 4.7 us */
- udelay(IXGBE_I2C_T_LOW);
-
- return status;
-}
-
-/**
- * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
- * @hw: pointer to hardware structure
- * @data: read data value
- *
- * Clocks in one bit via I2C data/clock
- **/
-static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
-{
- u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
-
- ixgbe_raise_i2c_clk(hw, &i2cctl);
-
- /* Minimum high period of clock is 4us */
- udelay(IXGBE_I2C_T_HIGH);
-
- i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
- *data = ixgbe_get_i2c_data(&i2cctl);
-
- ixgbe_lower_i2c_clk(hw, &i2cctl);
-
- /* Minimum low period of clock is 4.7 us */
- udelay(IXGBE_I2C_T_LOW);
-
- return 0;
-}
-
-/**
- * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
- * @hw: pointer to hardware structure
- * @data: data value to write
- *
- * Clocks out one bit via I2C data/clock
- **/
-static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
-{
- s32 status;
- u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
-
- status = ixgbe_set_i2c_data(hw, &i2cctl, data);
- if (status == 0) {
- ixgbe_raise_i2c_clk(hw, &i2cctl);
-
- /* Minimum high period of clock is 4us */
- udelay(IXGBE_I2C_T_HIGH);
-
- ixgbe_lower_i2c_clk(hw, &i2cctl);
-
- /* Minimum low period of clock is 4.7 us.
- * This also takes care of the data hold time.
- */
- udelay(IXGBE_I2C_T_LOW);
- } else {
- status = IXGBE_ERR_I2C;
- hw_dbg(hw, "I2C data was not set to %X\n", data);
- }
-
- return status;
-}
-/**
- * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
- * @hw: pointer to hardware structure
- * @i2cctl: Current value of I2CCTL register
- *
- * Raises the I2C clock line '0'->'1'
- **/
-static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
-{
- u32 i = 0;
- u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
- u32 i2cctl_r = 0;
-
- for (i = 0; i < timeout; i++) {
- *i2cctl |= IXGBE_I2C_CLK_OUT;
-
- IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
- IXGBE_WRITE_FLUSH(hw);
- /* SCL rise time (1000ns) */
- udelay(IXGBE_I2C_T_RISE);
-
- i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
- if (i2cctl_r & IXGBE_I2C_CLK_IN)
- break;
- }
-}
-
-/**
- * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
- * @hw: pointer to hardware structure
- * @i2cctl: Current value of I2CCTL register
- *
- * Lowers the I2C clock line '1'->'0'
- **/
-static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
-{
-
- *i2cctl &= ~IXGBE_I2C_CLK_OUT;
-
- IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
- IXGBE_WRITE_FLUSH(hw);
-
- /* SCL fall time (300ns) */
- udelay(IXGBE_I2C_T_FALL);
-}
-
-/**
- * ixgbe_set_i2c_data - Sets the I2C data bit
- * @hw: pointer to hardware structure
- * @i2cctl: Current value of I2CCTL register
- * @data: I2C data value (0 or 1) to set
- *
- * Sets the I2C data bit
- **/
-static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
-{
- s32 status = 0;
-
- if (data)
- *i2cctl |= IXGBE_I2C_DATA_OUT;
- else
- *i2cctl &= ~IXGBE_I2C_DATA_OUT;
-
- IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
- IXGBE_WRITE_FLUSH(hw);
-
- /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
- udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
-
- /* Verify data was set correctly */
- *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
- if (data != ixgbe_get_i2c_data(i2cctl)) {
- status = IXGBE_ERR_I2C;
- hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
- }
-
- return status;
-}
-
-/**
- * ixgbe_get_i2c_data - Reads the I2C SDA data bit
- * @hw: pointer to hardware structure
- * @i2cctl: Current value of I2CCTL register
- *
- * Returns the I2C data bit value
- **/
-static bool ixgbe_get_i2c_data(u32 *i2cctl)
-{
- bool data;
-
- if (*i2cctl & IXGBE_I2C_DATA_IN)
- data = 1;
- else
- data = 0;
-
- return data;
-}
-
-/**
- * ixgbe_i2c_bus_clear - Clears the I2C bus
- * @hw: pointer to hardware structure
- *
- * Clears the I2C bus by sending nine clock pulses.
- * Used when data line is stuck low.
- **/
-void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
-{
- u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
- u32 i;
-
- ixgbe_i2c_start(hw);
-
- ixgbe_set_i2c_data(hw, &i2cctl, 1);
-
- for (i = 0; i < 9; i++) {
- ixgbe_raise_i2c_clk(hw, &i2cctl);
-
- /* Min high period of clock is 4us */
- udelay(IXGBE_I2C_T_HIGH);
-
- ixgbe_lower_i2c_clk(hw, &i2cctl);
-
- /* Min low period of clock is 4.7us*/
- udelay(IXGBE_I2C_T_LOW);
- }
-
- ixgbe_i2c_start(hw);
-
- /* Put the i2c bus back to default state */
- ixgbe_i2c_stop(hw);
-}
-
-/**
- * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
- * @hw: pointer to hardware structure
- *
- * Checks if the LASI temp alarm status was triggered due to overtemp
- **/
-s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
-{
- s32 status = 0;
- u16 phy_data = 0;
-
- if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
- goto out;
-
- /* Check that the LASI temp alarm status was triggered */
- hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
- IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
-
- if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
- goto out;
-
- status = IXGBE_ERR_OVERTEMP;
-out:
- return status;
-}
diff --git a/kernel/linux/kni/ethtool/ixgbe/ixgbe_phy.h b/kernel/linux/kni/ethtool/ixgbe/ixgbe_phy.h
deleted file mode 100644
index 6baa9ac..0000000
--- a/kernel/linux/kni/ethtool/ixgbe/ixgbe_phy.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*******************************************************************************
-
- Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2012 Intel Corporation.
-
- Contact Information:
- e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
- Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-
-#ifndef _IXGBE_PHY_H_
-#define _IXGBE_PHY_H_
-
-#include "ixgbe_type.h"
-#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0
-
-/* EEPROM byte offsets */
-#define IXGBE_SFF_IDENTIFIER 0x0
-#define IXGBE_SFF_IDENTIFIER_SFP 0x3
-#define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25
-#define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26
-#define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27
-#define IXGBE_SFF_1GBE_COMP_CODES 0x6
-#define IXGBE_SFF_10GBE_COMP_CODES 0x3
-#define IXGBE_SFF_CABLE_TECHNOLOGY 0x8
-#define IXGBE_SFF_CABLE_SPEC_COMP 0x3C
-
-/* Bitmasks */
-#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4
-#define IXGBE_SFF_DA_ACTIVE_CABLE 0x8
-#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4
-#define IXGBE_SFF_1GBASESX_CAPABLE 0x1
-#define IXGBE_SFF_1GBASELX_CAPABLE 0x2
-#define IXGBE_SFF_1GBASET_CAPABLE 0x8
-#define IXGBE_SFF_10GBASESR_CAPABLE 0x10
-#define IXGBE_SFF_10GBASELR_CAPABLE 0x20
-#define IXGBE_I2C_EEPROM_READ_MASK 0x100
-#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3
-#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
-#define IXGBE_I2C_EEPROM_STATUS_PASS 0x1
-#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2
-#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
-
-/* Flow control defines */
-#define IXGBE_TAF_SYM_PAUSE 0x400
-#define IXGBE_TAF_ASM_PAUSE 0x800
-
-/* Bit-shift macros */
-#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24
-#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16
-#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8
-
-/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
-#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600
-#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500
-#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
-#define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100
-
-/* I2C SDA and SCL timing parameters for standard mode */
-#define IXGBE_I2C_T_HD_STA 4
-#define IXGBE_I2C_T_LOW 5
-#define IXGBE_I2C_T_HIGH 4
-#define IXGBE_I2C_T_SU_STA 5
-#define IXGBE_I2C_T_HD_DATA 5
-#define IXGBE_I2C_T_SU_DATA 1
-#define IXGBE_I2C_T_RISE 1
-#define IXGBE_I2C_T_FALL 1
-#define IXGBE_I2C_T_SU_STO 4
-#define IXGBE_I2C_T_BUF 5
-
-#define IXGBE_TN_LASI_STATUS_REG 0x9005
-#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
-
-s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
-bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
-enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
-s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
-s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
-s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
-s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
- u32 device_type, u16 *phy_data);
-s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
- u32 device_type, u16 phy_data);
-s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
-s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
- ixgbe_link_speed speed,
- bool autoneg,
- bool autoneg_wait_to_complete);
-s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed,
- bool *autoneg);
-
-/* PHY specific */
-s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
- ixgbe_link_speed *speed,
- bool *link_up);
-s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
-s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
- u16 *firmware_version);
-s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
- u16 *firmware_version);
-
-s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
-s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
-s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
-s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
-s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
- u16 *list_offset,
- u16 *data_offset);
-s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
-s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
- u8 dev_addr, u8 *data);
-s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
- u8 dev_addr, u8 data);
-s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
- u8 *eeprom_data);
-s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
- u8 eeprom_data);
-void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
-#endif /* _IXGBE_PHY_H_ */
diff --git a/kernel/linux/kni/ethtool/ixgbe/ixgbe_type.h b/kernel/linux/kni/ethtool/ixgbe/ixgbe_type.h
deleted file mode 100644
index 0689590..0000000
--- a/kernel/linux/kni/ethtool/ixgbe/ixgbe_type.h
+++ /dev/null
@@ -1,3239 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*******************************************************************************
-
- Intel 10 Gigabit PCI Express Linux driver
- Copyright(c) 1999 - 2012 Intel Corporation.
-
- Contact Information:
- e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
- Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-
-#ifndef _IXGBE_TYPE_H_
-#define _IXGBE_TYPE_H_
-
-#include "ixgbe_osdep.h"
-
-
-/* Vendor ID */
-#define IXGBE_INTEL_VENDOR_ID 0x8086
-
-/* Device IDs */
-#define IXGBE_DEV_ID_82598 0x10B6
-#define IXGBE_DEV_ID_82598_BX 0x1508
-#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
-#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
-#define IXGBE_DEV_ID_82598AT 0x10C8
-#define IXGBE_DEV_ID_82598AT2 0x150B
-#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
-#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
-#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
-#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
-#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
-#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
-#define IXGBE_DEV_ID_82599_KX4 0x10F7
-#define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
-#define IXGBE_DEV_ID_82599_KR 0x1517
-#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
-#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
-#define IXGBE_DEV_ID_82599_CX4 0x10F9
-#define IXGBE_DEV_ID_82599_SFP 0x10FB
-#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
-#define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0
-#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A
-#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
-#define IXGBE_DEV_ID_82599_SFP_EM 0x1507
-#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D
-#define IXGBE_DEV_ID_82599_QSFP_SF_QP 0x1558
-#define IXGBE_DEV_ID_82599EN_SFP 0x1557
-#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
-#define IXGBE_DEV_ID_82599_T3_LOM 0x151C
-#define IXGBE_DEV_ID_82599_LS 0x154F
-#define IXGBE_DEV_ID_X540T 0x1528
-
-/* General Registers */
-#define IXGBE_CTRL 0x00000
-#define IXGBE_STATUS 0x00008
-#define IXGBE_CTRL_EXT 0x00018
-#define IXGBE_ESDP 0x00020
-#define IXGBE_EODSDP 0x00028
-#define IXGBE_I2CCTL 0x00028
-#define IXGBE_PHY_GPIO 0x00028
-#define IXGBE_MAC_GPIO 0x00030
-#define IXGBE_PHYINT_STATUS0 0x00100
-#define IXGBE_PHYINT_STATUS1 0x00104
-#define IXGBE_PHYINT_STATUS2 0x00108
-#define IXGBE_LEDCTL 0x00200
-#define IXGBE_FRTIMER 0x00048
-#define IXGBE_TCPTIMER 0x0004C
-#define IXGBE_CORESPARE 0x00600
-#define IXGBE_EXVET 0x05078
-
-/* NVM Registers */
-#define IXGBE_EEC 0x10010
-#define IXGBE_EERD 0x10014
-#define IXGBE_EEWR 0x10018
-#define IXGBE_FLA 0x1001C
-#define IXGBE_EEMNGCTL 0x10110
-#define IXGBE_EEMNGDATA 0x10114
-#define IXGBE_FLMNGCTL 0x10118
-#define IXGBE_FLMNGDATA 0x1011C
-#define IXGBE_FLMNGCNT 0x10120
-#define IXGBE_FLOP 0x1013C
-#define IXGBE_GRC 0x10200
-#define IXGBE_SRAMREL 0x10210
-#define IXGBE_PHYDBG 0x10218
-
-/* General Receive Control */
-#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
-#define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
-
-#define IXGBE_VPDDIAG0 0x10204
-#define IXGBE_VPDDIAG1 0x10208
-
-/* I2CCTL Bit Masks */
-#define IXGBE_I2C_CLK_IN 0x00000001
-#define IXGBE_I2C_CLK_OUT 0x00000002
-#define IXGBE_I2C_DATA_IN 0x00000004
-#define IXGBE_I2C_DATA_OUT 0x00000008
-#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500
-
-#define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8
-#define IXGBE_EMC_INTERNAL_DATA 0x00
-#define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20
-#define IXGBE_EMC_DIODE1_DATA 0x01
-#define IXGBE_EMC_DIODE1_THERM_LIMIT 0x19
-#define IXGBE_EMC_DIODE2_DATA 0x23
-#define IXGBE_EMC_DIODE2_THERM_LIMIT 0x1A
-
-#define IXGBE_MAX_SENSORS 3
-
-struct ixgbe_thermal_diode_data {
- u8 location;
- u8 temp;
- u8 caution_thresh;
- u8 max_op_thresh;
-};
-
-struct ixgbe_thermal_sensor_data {
- struct ixgbe_thermal_diode_data sensor[IXGBE_MAX_SENSORS];
-};
-
-/* Interrupt Registers */
-#define IXGBE_EICR 0x00800
-#define IXGBE_EICS 0x00808
-#define IXGBE_EIMS 0x00880
-#define IXGBE_EIMC 0x00888
-#define IXGBE_EIAC 0x00810
-#define IXGBE_EIAM 0x00890
-#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
-#define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
-#define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
-#define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
-/* 82599 EITR is only 12 bits, with the lower 3 always zero */
-/*
- * 82598 EITR is 16 bits but set the limits based on the max
- * supported by all ixgbe hardware
- */
-#define IXGBE_MAX_INT_RATE 488281
-#define IXGBE_MIN_INT_RATE 956
-#define IXGBE_MAX_EITR 0x00000FF8
-#define IXGBE_MIN_EITR 8
-#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
- (0x012300 + (((_i) - 24) * 4)))
-#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
-#define IXGBE_EITR_LLI_MOD 0x00008000
-#define IXGBE_EITR_CNT_WDIS 0x80000000
-#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
-#define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
-#define IXGBE_EITRSEL 0x00894
-#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
-#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
-#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
-#define IXGBE_GPIE 0x00898
-
-/* Flow Control Registers */
-#define IXGBE_FCADBUL 0x03210
-#define IXGBE_FCADBUH 0x03214
-#define IXGBE_FCAMACL 0x04328
-#define IXGBE_FCAMACH 0x0432C
-#define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_PFCTOP 0x03008
-#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
-#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
-#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
-#define IXGBE_FCRTV 0x032A0
-#define IXGBE_FCCFG 0x03D00
-#define IXGBE_TFCS 0x0CE00
-
-/* Receive DMA Registers */
-#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
- (0x0D000 + (((_i) - 64) * 0x40)))
-#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
- (0x0D004 + (((_i) - 64) * 0x40)))
-#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
- (0x0D008 + (((_i) - 64) * 0x40)))
-#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
- (0x0D010 + (((_i) - 64) * 0x40)))
-#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
- (0x0D018 + (((_i) - 64) * 0x40)))
-#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
- (0x0D028 + (((_i) - 64) * 0x40)))
-#define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
- (0x0D02C + (((_i) - 64) * 0x40)))
-#define IXGBE_RSCDBU 0x03028
-#define IXGBE_RDDCC 0x02F20
-#define IXGBE_RXMEMWRAP 0x03190
-#define IXGBE_STARCTRL 0x03024
-/*
- * Split and Replication Receive Control Registers
- * 00-15 : 0x02100 + n*4
- * 16-64 : 0x01014 + n*0x40
- * 64-127: 0x0D014 + (n-64)*0x40
- */
-#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
- (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
- (0x0D014 + (((_i) - 64) * 0x40))))
-/*
- * Rx DCA Control Register:
- * 00-15 : 0x02200 + n*4
- * 16-64 : 0x0100C + n*0x40
- * 64-127: 0x0D00C + (n-64)*0x40
- */
-#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
- (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
- (0x0D00C + (((_i) - 64) * 0x40))))
-#define IXGBE_RDRXCTL 0x02F00
-#define IXGBE_RDRXCTL_RSC_PUSH 0x80
-/* 8 of these 0x03C00 - 0x03C1C */
-#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
-#define IXGBE_RXCTRL 0x03000
-#define IXGBE_DROPEN 0x03D04
-#define IXGBE_RXPBSIZE_SHIFT 10
-
-/* Receive Registers */
-#define IXGBE_RXCSUM 0x05000
-#define IXGBE_RFCTL 0x05008
-#define IXGBE_DRECCCTL 0x02F08
-#define IXGBE_DRECCCTL_DISABLE 0
-#define IXGBE_DRECCCTL2 0x02F8C
-
-/* Multicast Table Array - 128 entries */
-#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
-#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
- (0x0A200 + ((_i) * 8)))
-#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
- (0x0A204 + ((_i) * 8)))
-#define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
-#define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
-/* Packet split receive type */
-#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
- (0x0EA00 + ((_i) * 4)))
-/* array of 4096 1-bit vlan filters */
-#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
-/*array of 4096 4-bit vlan vmdq indices */
-#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
-#define IXGBE_FCTRL 0x05080
-#define IXGBE_VLNCTRL 0x05088
-#define IXGBE_MCSTCTRL 0x05090
-#define IXGBE_MRQC 0x05818
-#define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
-#define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
-#define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
-#define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
-#define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */
-#define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
-#define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */
-#define IXGBE_RQTC 0x0EC70
-#define IXGBE_MTQC 0x08120
-#define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */
-#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */
-#define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */
-#define IXGBE_VT_CTL 0x051B0
-#define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */
-/* 64 Mailboxes, 16 DW each */
-#define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i)))
-#define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */
-#define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i))) /* 4 total */
-#define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
-#define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
-#define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4))
-#define IXGBE_QDE 0x2F04
-#define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4)) /* 2 total */
-#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */
-#define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
-#define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4))
-#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
-#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
-#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
-#define IXGBE_RXFECCERR0 0x051B8
-#define IXGBE_LLITHRESH 0x0EC90
-#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_IMIRVP 0x05AC0
-#define IXGBE_VMD_CTL 0x0581C
-#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
-#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
-
-/* Flow Director registers */
-#define IXGBE_FDIRCTRL 0x0EE00
-#define IXGBE_FDIRHKEY 0x0EE68
-#define IXGBE_FDIRSKEY 0x0EE6C
-#define IXGBE_FDIRDIP4M 0x0EE3C
-#define IXGBE_FDIRSIP4M 0x0EE40
-#define IXGBE_FDIRTCPM 0x0EE44
-#define IXGBE_FDIRUDPM 0x0EE48
-#define IXGBE_FDIRIP6M 0x0EE74
-#define IXGBE_FDIRM 0x0EE70
-
-/* Flow Director Stats registers */
-#define IXGBE_FDIRFREE 0x0EE38
-#define IXGBE_FDIRLEN 0x0EE4C
-#define IXGBE_FDIRUSTAT 0x0EE50
-#define IXGBE_FDIRFSTAT 0x0EE54
-#define IXGBE_FDIRMATCH 0x0EE58
-#define IXGBE_FDIRMISS 0x0EE5C
-
-/* Flow Director Programming registers */
-#define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
-#define IXGBE_FDIRIPSA 0x0EE18
-#define IXGBE_FDIRIPDA 0x0EE1C
-#define IXGBE_FDIRPORT 0x0EE20
-#define IXGBE_FDIRVLAN 0x0EE24
-#define IXGBE_FDIRHASH 0x0EE28
-#define IXGBE_FDIRCMD 0x0EE2C
-
-/* Transmit DMA registers */
-#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of them (0-31)*/
-#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
-#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
-#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
-#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
-#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
-#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
-#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
-#define IXGBE_DTXCTL 0x07E00
-
-#define IXGBE_DMATXCTL 0x04A80
-#define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
-#define IXGBE_PFDTXGSWC 0x08220
-#define IXGBE_DTXMXSZRQ 0x08100
-#define IXGBE_DTXTCPFLGL 0x04A88
-#define IXGBE_DTXTCPFLGH 0x04A8C
-#define IXGBE_LBDRPEN 0x0CA00
-#define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
-
-#define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */
-#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */
-#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */
-#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */
-
-#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
-
-/* Anti-spoofing defines */
-#define IXGBE_SPOOF_MACAS_MASK 0xFF
-#define IXGBE_SPOOF_VLANAS_MASK 0xFF00
-#define IXGBE_SPOOF_VLANAS_SHIFT 8
-#define IXGBE_PFVFSPOOF_REG_COUNT 8
-/* 16 of these (0-15) */
-#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4))
-/* Tx DCA Control register : 128 of these (0-127) */
-#define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
-#define IXGBE_TIPG 0x0CB00
-#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
-#define IXGBE_MNGTXMAP 0x0CD10
-#define IXGBE_TIPG_FIBER_DEFAULT 3
-#define IXGBE_TXPBSIZE_SHIFT 10
-
-/* Wake up registers */
-#define IXGBE_WUC 0x05800
-#define IXGBE_WUFC 0x05808
-#define IXGBE_WUS 0x05810
-#define IXGBE_IPAV 0x05838
-#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */
-#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
-
-#define IXGBE_WUPL 0x05900
-#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
-#define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */
-/* Ext Flexible Host Filter Table */
-#define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100))
-
-#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
-#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
-
-/* Each Flexible Filter is at most 128 (0x80) bytes in length */
-#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
-#define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
-#define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
-
-/* Definitions for power management and wakeup registers */
-/* Wake Up Control */
-#define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */
-#define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
-#define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */
-
-/* Wake Up Filter Control */
-#define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
-#define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
-#define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
-#define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
-#define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
-#define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
-#define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
-#define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
-#define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */
-
-#define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
-#define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
-#define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
-#define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
-#define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
-#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
-#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
-#define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */
-/* Mask for Ext. flex filters */
-#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000
-#define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all wakeup filters */
-#define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
-
-/* Wake Up Status */
-#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
-#define IXGBE_WUS_MAG IXGBE_WUFC_MAG
-#define IXGBE_WUS_EX IXGBE_WUFC_EX
-#define IXGBE_WUS_MC IXGBE_WUFC_MC
-#define IXGBE_WUS_BC IXGBE_WUFC_BC
-#define IXGBE_WUS_ARP IXGBE_WUFC_ARP
-#define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
-#define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
-#define IXGBE_WUS_MNG IXGBE_WUFC_MNG
-#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
-#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
-#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
-#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
-#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
-#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
-#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
-
-/* Wake Up Packet Length */
-#define IXGBE_WUPL_LENGTH_MASK 0xFFFF
-
-/* DCB registers */
-#define IXGBE_DCB_MAX_TRAFFIC_CLASS 8
-#define IXGBE_RMCS 0x03D00
-#define IXGBE_DPMCS 0x07F40
-#define IXGBE_PDPMCS 0x0CD00
-#define IXGBE_RUPPBMR 0x050A0
-#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
-#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
-#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
-
-
-/* Security Control Registers */
-#define IXGBE_SECTXCTRL 0x08800
-#define IXGBE_SECTXSTAT 0x08804
-#define IXGBE_SECTXBUFFAF 0x08808
-#define IXGBE_SECTXMINIFG 0x08810
-#define IXGBE_SECRXCTRL 0x08D00
-#define IXGBE_SECRXSTAT 0x08D04
-
-/* Security Bit Fields and Masks */
-#define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001
-#define IXGBE_SECTXCTRL_TX_DIS 0x00000002
-#define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004
-
-#define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001
-#define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002
-
-#define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001
-#define IXGBE_SECRXCTRL_RX_DIS 0x00000002
-
-#define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001
-#define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002
-
-/* LinkSec (MacSec) Registers */
-#define IXGBE_LSECTXCAP 0x08A00
-#define IXGBE_LSECRXCAP 0x08F00
-#define IXGBE_LSECTXCTRL 0x08A04
-#define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */
-#define IXGBE_LSECTXSCH 0x08A0C /* SCI High */
-#define IXGBE_LSECTXSA 0x08A10
-#define IXGBE_LSECTXPN0 0x08A14
-#define IXGBE_LSECTXPN1 0x08A18
-#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
-#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
-#define IXGBE_LSECRXCTRL 0x08F04
-#define IXGBE_LSECRXSCL 0x08F08
-#define IXGBE_LSECRXSCH 0x08F0C
-#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
-#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
-#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
-#define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */
-#define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */
-#define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */
-#define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */
-#define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */
-#define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */
-#define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */
-#define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */
-#define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */
-#define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */
-#define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */
-#define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */
-#define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */
-#define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */
-#define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */
-#define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
-#define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
-#define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */
-#define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */
-
-/* LinkSec (MacSec) Bit Fields and Masks */
-#define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000
-#define IXGBE_LSECTXCAP_SUM_SHIFT 16
-#define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000
-#define IXGBE_LSECRXCAP_SUM_SHIFT 16
-
-#define IXGBE_LSECTXCTRL_EN_MASK 0x00000003
-#define IXGBE_LSECTXCTRL_DISABLE 0x0
-#define IXGBE_LSECTXCTRL_AUTH 0x1
-#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2
-#define IXGBE_LSECTXCTRL_AISCI 0x00000020
-#define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
-#define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8
-
-#define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C
-#define IXGBE_LSECRXCTRL_EN_SHIFT 2
-#define IXGBE_LSECRXCTRL_DISABLE 0x0
-#define IXGBE_LSECRXCTRL_CHECK 0x1
-#define IXGBE_LSECRXCTRL_STRICT 0x2
-#define IXGBE_LSECRXCTRL_DROP 0x3
-#define IXGBE_LSECRXCTRL_PLSH 0x00000040
-#define IXGBE_LSECRXCTRL_RP 0x00000080
-#define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33
-
-/* IpSec Registers */
-#define IXGBE_IPSTXIDX 0x08900
-#define IXGBE_IPSTXSALT 0x08904
-#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
-#define IXGBE_IPSRXIDX 0x08E00
-#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
-#define IXGBE_IPSRXSPI 0x08E14
-#define IXGBE_IPSRXIPIDX 0x08E18
-#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
-#define IXGBE_IPSRXSALT 0x08E2C
-#define IXGBE_IPSRXMOD 0x08E30
-
-#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4
-
-/* DCB registers */
-#define IXGBE_RTRPCS 0x02430
-#define IXGBE_RTTDCS 0x04900
-#define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */
-#define IXGBE_RTTPCS 0x0CD00
-#define IXGBE_RTRUP2TC 0x03020
-#define IXGBE_RTTUP2TC 0x0C800
-#define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */
-#define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_RTTDQSEL 0x04904
-#define IXGBE_RTTDT1C 0x04908
-#define IXGBE_RTTDT1S 0x0490C
-#define IXGBE_RTTDTECC 0x04990
-#define IXGBE_RTTDTECC_NO_BCN 0x00000100
-
-#define IXGBE_RTTBCNRC 0x04984
-#define IXGBE_RTTBCNRC_RS_ENA 0x80000000
-#define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF
-#define IXGBE_RTTBCNRC_RF_INT_SHIFT 14
-#define IXGBE_RTTBCNRC_RF_INT_MASK \
- (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
-#define IXGBE_RTTBCNRM 0x04980
-
-/* FCoE DMA Context Registers */
-#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */
-#define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */
-#define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */
-#define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */
-#define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0*/
-#define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4))
-#define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */
-#define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */
-#define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */
-#define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */
-#define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */
-#define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3
-#define IXGBE_FCBUFF_BUFFCNT_SHIFT 8
-#define IXGBE_FCBUFF_OFFSET_SHIFT 16
-#define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */
-#define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */
-#define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */
-#define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */
-#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
-/* FCoE SOF/EOF */
-#define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */
-#define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */
-#define IXGBE_REOFF 0x05158 /* Rx FC EOF */
-#define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */
-/* FCoE Filter Context Registers */
-#define IXGBE_FCFLT 0x05108 /* FC FLT Context */
-#define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */
-#define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */
-#define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */
-#define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */
-#define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */
-#define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */
-#define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */
-#define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */
-#define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */
-/* FCoE Receive Control */
-#define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */
-#define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */
-#define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */
-#define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */
-#define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */
-#define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */
-#define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */
-#define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */
-#define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */
-#define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */
-#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
-/* FCoE Redirection */
-#define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */
-#define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */
-#define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
-#define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */
-#define IXGBE_FCRETASEL_ENA 0x2 /* FCoE FCRETASEL bit */
-#define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */
-#define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */
-
-/* Stats registers */
-#define IXGBE_CRCERRS 0x04000
-#define IXGBE_ILLERRC 0x04004
-#define IXGBE_ERRBC 0x04008
-#define IXGBE_MSPDC 0x04010
-#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
-#define IXGBE_MLFC 0x04034
-#define IXGBE_MRFC 0x04038
-#define IXGBE_RLEC 0x04040
-#define IXGBE_LXONTXC 0x03F60
-#define IXGBE_LXONRXC 0x0CF60
-#define IXGBE_LXOFFTXC 0x03F68
-#define IXGBE_LXOFFRXC 0x0CF68
-#define IXGBE_LXONRXCNT 0x041A4
-#define IXGBE_LXOFFRXCNT 0x041A8
-#define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */
-#define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */
-#define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */
-#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
-#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
-#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
-#define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
-#define IXGBE_PRC64 0x0405C
-#define IXGBE_PRC127 0x04060
-#define IXGBE_PRC255 0x04064
-#define IXGBE_PRC511 0x04068
-#define IXGBE_PRC1023 0x0406C
-#define IXGBE_PRC1522 0x04070
-#define IXGBE_GPRC 0x04074
-#define IXGBE_BPRC 0x04078
-#define IXGBE_MPRC 0x0407C
-#define IXGBE_GPTC 0x04080
-#define IXGBE_GORCL 0x04088
-#define IXGBE_GORCH 0x0408C
-#define IXGBE_GOTCL 0x04090
-#define IXGBE_GOTCH 0x04094
-#define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
-#define IXGBE_RUC 0x040A4
-#define IXGBE_RFC 0x040A8
-#define IXGBE_ROC 0x040AC
-#define IXGBE_RJC 0x040B0
-#define IXGBE_MNGPRC 0x040B4
-#define IXGBE_MNGPDC 0x040B8
-#define IXGBE_MNGPTC 0x0CF90
-#define IXGBE_TORL 0x040C0
-#define IXGBE_TORH 0x040C4
-#define IXGBE_TPR 0x040D0
-#define IXGBE_TPT 0x040D4
-#define IXGBE_PTC64 0x040D8
-#define IXGBE_PTC127 0x040DC
-#define IXGBE_PTC255 0x040E0
-#define IXGBE_PTC511 0x040E4
-#define IXGBE_PTC1023 0x040E8
-#define IXGBE_PTC1522 0x040EC
-#define IXGBE_MPTC 0x040F0
-#define IXGBE_BPTC 0x040F4
-#define IXGBE_XEC 0x04120
-#define IXGBE_SSVPC 0x08780
-
-#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
-#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
- (0x08600 + ((_i) * 4)))
-#define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4))
-
-#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
-#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
-#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
-#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
-#define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
-#define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */
-#define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
-#define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
-#define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
-#define IXGBE_FCCRC 0x05118 /* Num of Good Eth CRC w/ Bad FC CRC */
-#define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */
-#define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */
-#define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */
-#define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */
-#define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */
-#define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */
-#define IXGBE_FCCRC_CNT_MASK 0x0000FFFF /* CRC_CNT: bit 0 - 15 */
-#define IXGBE_FCLAST_CNT_MASK 0x0000FFFF /* Last_CNT: bit 0 - 15 */
-#define IXGBE_O2BGPTC 0x041C4
-#define IXGBE_O2BSPC 0x087B0
-#define IXGBE_B2OSPC 0x041C0
-#define IXGBE_B2OGPRC 0x02F90
-#define IXGBE_BUPRC 0x04180
-#define IXGBE_BMPRC 0x04184
-#define IXGBE_BBPRC 0x04188
-#define IXGBE_BUPTC 0x0418C
-#define IXGBE_BMPTC 0x04190
-#define IXGBE_BBPTC 0x04194
-#define IXGBE_BCRCERRS 0x04198
-#define IXGBE_BXONRXC 0x0419C
-#define IXGBE_BXOFFRXC 0x041E0
-#define IXGBE_BXONTXC 0x041E4
-#define IXGBE_BXOFFTXC 0x041E8
-#define IXGBE_PCRC8ECL 0x0E810
-#define IXGBE_PCRC8ECH 0x0E811
-#define IXGBE_PCRC8ECH_MASK 0x1F
-#define IXGBE_LDPCECL 0x0E820
-#define IXGBE_LDPCECH 0x0E821
-
-/* Management */
-#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_MANC 0x05820
-#define IXGBE_MFVAL 0x05824
-#define IXGBE_MANC2H 0x05860
-#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_MIPAF 0x058B0
-#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
-#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
-#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */
-#define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
-#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
-#define IXGBE_LSWFW 0x15014
-#define IXGBE_BMCIP(_i) (0x05050 + ((_i) * 4)) /* 0x5050-0x505C */
-#define IXGBE_BMCIPVAL 0x05060
-#define IXGBE_BMCIP_IPADDR_TYPE 0x00000001
-#define IXGBE_BMCIP_IPADDR_VALID 0x00000002
-
-/* Management Bit Fields and Masks */
-#define IXGBE_MANC_EN_BMC2OS 0x10000000 /* Ena BMC2OS and OS2BMC traffic */
-#define IXGBE_MANC_EN_BMC2OS_SHIFT 28
-
-/* Firmware Semaphore Register */
-#define IXGBE_FWSM_MODE_MASK 0xE
-
-/* ARC Subsystem registers */
-#define IXGBE_HICR 0x15F00
-#define IXGBE_FWSTS 0x15F0C
-#define IXGBE_HSMC0R 0x15F04
-#define IXGBE_HSMC1R 0x15F08
-#define IXGBE_SWSR 0x15F10
-#define IXGBE_HFDR 0x15FE8
-#define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */
-
-#define IXGBE_HICR_EN 0x01 /* Enable bit - RO */
-/* Driver sets this bit when done to put command in RAM */
-#define IXGBE_HICR_C 0x02
-#define IXGBE_HICR_SV 0x04 /* Status Validity */
-#define IXGBE_HICR_FW_RESET_ENABLE 0x40
-#define IXGBE_HICR_FW_RESET 0x80
-
-/* PCI-E registers */
-#define IXGBE_GCR 0x11000
-#define IXGBE_GTV 0x11004
-#define IXGBE_FUNCTAG 0x11008
-#define IXGBE_GLT 0x1100C
-#define IXGBE_PCIEPIPEADR 0x11004
-#define IXGBE_PCIEPIPEDAT 0x11008
-#define IXGBE_GSCL_1 0x11010
-#define IXGBE_GSCL_2 0x11014
-#define IXGBE_GSCL_3 0x11018
-#define IXGBE_GSCL_4 0x1101C
-#define IXGBE_GSCN_0 0x11020
-#define IXGBE_GSCN_1 0x11024
-#define IXGBE_GSCN_2 0x11028
-#define IXGBE_GSCN_3 0x1102C
-#define IXGBE_FACTPS 0x10150
-#define IXGBE_PCIEANACTL 0x11040
-#define IXGBE_SWSM 0x10140
-#define IXGBE_FWSM 0x10148
-#define IXGBE_GSSR 0x10160
-#define IXGBE_MREVID 0x11064
-#define IXGBE_DCA_ID 0x11070
-#define IXGBE_DCA_CTRL 0x11074
-#define IXGBE_SWFW_SYNC IXGBE_GSSR
-
-/* PCI-E registers 82599-Specific */
-#define IXGBE_GCR_EXT 0x11050
-#define IXGBE_GSCL_5_82599 0x11030
-#define IXGBE_GSCL_6_82599 0x11034
-#define IXGBE_GSCL_7_82599 0x11038
-#define IXGBE_GSCL_8_82599 0x1103C
-#define IXGBE_PHYADR_82599 0x11040
-#define IXGBE_PHYDAT_82599 0x11044
-#define IXGBE_PHYCTL_82599 0x11048
-#define IXGBE_PBACLR_82599 0x11068
-#define IXGBE_CIAA_82599 0x11088
-#define IXGBE_CIAD_82599 0x1108C
-#define IXGBE_PICAUSE 0x110B0
-#define IXGBE_PIENA 0x110B8
-#define IXGBE_CDQ_MBR_82599 0x110B4
-#define IXGBE_PCIESPARE 0x110BC
-#define IXGBE_MISC_REG_82599 0x110F0
-#define IXGBE_ECC_CTRL_0_82599 0x11100
-#define IXGBE_ECC_CTRL_1_82599 0x11104
-#define IXGBE_ECC_STATUS_82599 0x110E0
-#define IXGBE_BAR_CTRL_82599 0x110F4
-
-/* PCI Express Control */
-#define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000
-#define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000
-#define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000
-#define IXGBE_GCR_CAP_VER2 0x00040000
-
-#define IXGBE_GCR_EXT_MSIX_EN 0x80000000
-#define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000
-#define IXGBE_GCR_EXT_VT_MODE_16 0x00000001
-#define IXGBE_GCR_EXT_VT_MODE_32 0x00000002
-#define IXGBE_GCR_EXT_VT_MODE_64 0x00000003
-#define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \
- IXGBE_GCR_EXT_VT_MODE_64)
-/* Time Sync Registers */
-#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
-#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
-#define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */
-#define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */
-#define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */
-#define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */
-#define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */
-#define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */
-#define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */
-#define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */
-#define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */
-#define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */
-#define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */
-#define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */
-#define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */
-#define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */
-#define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */
-#define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */
-#define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */
-#define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */
-#define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */
-#define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */
-#define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */
-#define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */
-#define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */
-
-/* Diagnostic Registers */
-#define IXGBE_RDSTATCTL 0x02C20
-#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
-#define IXGBE_RDHMPN 0x02F08
-#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
-#define IXGBE_RDPROBE 0x02F20
-#define IXGBE_RDMAM 0x02F30
-#define IXGBE_RDMAD 0x02F34
-#define IXGBE_TDSTATCTL 0x07C20
-#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
-#define IXGBE_TDHMPN 0x07F08
-#define IXGBE_TDHMPN2 0x082FC
-#define IXGBE_TXDESCIC 0x082CC
-#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
-#define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
-#define IXGBE_TDPROBE 0x07F20
-#define IXGBE_TXBUFCTRL 0x0C600
-#define IXGBE_TXBUFDATA0 0x0C610
-#define IXGBE_TXBUFDATA1 0x0C614
-#define IXGBE_TXBUFDATA2 0x0C618
-#define IXGBE_TXBUFDATA3 0x0C61C
-#define IXGBE_RXBUFCTRL 0x03600
-#define IXGBE_RXBUFDATA0 0x03610
-#define IXGBE_RXBUFDATA1 0x03614
-#define IXGBE_RXBUFDATA2 0x03618
-#define IXGBE_RXBUFDATA3 0x0361C
-#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */
-#define IXGBE_RFVAL 0x050A4
-#define IXGBE_MDFTC1 0x042B8
-#define IXGBE_MDFTC2 0x042C0
-#define IXGBE_MDFTFIFO1 0x042C4
-#define IXGBE_MDFTFIFO2 0x042C8
-#define IXGBE_MDFTS 0x042CC
-#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
-#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
-#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
-#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
-#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
-#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
-#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
-#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
-#define IXGBE_PCIEECCCTL 0x1106C
-#define IXGBE_RXW