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authorFerruh Yigit <ferruh.yigit@intel.com>2018-10-28 01:08:44 +0000
committerThomas Monjalon <thomas@monjalon.net>2018-11-06 01:14:05 +0100
commit9eb06884120091a21fdfc35850167f6245c2109e (patch)
treefbcfba8b3570bcbc24493462effd0a81ae151fc4 /lib
parent1ccdc31793aff57d5fe34041c7fa0aa9c00c7f5c (diff)
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lib: fix shifting 32-bit signed variable 31 times
Fix cppcheck warning by marking variable as unsigned. Fixes: dc276b5780c2 ("acl: new library") Fixes: 986ff526fb84 ("net: add CRC computation API") Cc: stable@dpdk.org Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
Diffstat (limited to 'lib')
-rw-r--r--lib/librte_acl/acl_gen.c2
-rw-r--r--lib/librte_net/rte_net_crc.c4
2 files changed, 3 insertions, 3 deletions
diff --git a/lib/librte_acl/acl_gen.c b/lib/librte_acl/acl_gen.c
index bed66be..35a0140 100644
--- a/lib/librte_acl/acl_gen.c
+++ b/lib/librte_acl/acl_gen.c
@@ -163,7 +163,7 @@ acl_count_sequential_groups(struct rte_acl_bitset *bits, int zero_one)
for (n = QRANGE_MIN; n < UINT8_MAX + 1; n++) {
if (bits->bits[n / (sizeof(bits_t) * 8)] &
- (1 << (n % (sizeof(bits_t) * 8)))) {
+ (1U << (n % (sizeof(bits_t) * 8)))) {
if (zero_one == 1 && last_bit != 1)
ranges++;
last_bit = 1;
diff --git a/lib/librte_net/rte_net_crc.c b/lib/librte_net/rte_net_crc.c
index 73ac3a9..dca0830 100644
--- a/lib/librte_net/rte_net_crc.c
+++ b/lib/librte_net/rte_net_crc.c
@@ -69,8 +69,8 @@ reflect_32bits(uint32_t val)
uint32_t i, res = 0;
for (i = 0; i < 32; i++)
- if ((val & (1 << i)) != 0)
- res |= (uint32_t)(1 << (31 - i));
+ if ((val & (1U << i)) != 0)
+ res |= (uint32_t)(1U << (31 - i));
return res;
}