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authorOlivier Matz <olivier.matz@6wind.com>2018-04-03 15:26:44 +0200
committerThomas Monjalon <thomas@monjalon.net>2018-04-18 00:24:22 +0200
commita3d6026711d00183e308f1dd79933f6161840e04 (patch)
treec9ed37d3fffba0f7deafd793869c4cb7fcfd288e /examples/eventdev_pipeline
parent6b298c62858d9bfd6bb58deaf961ae3bd91746b2 (diff)
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ring: relax alignment constraint on ring structure
The initial objective of commit d9f0d3a1ffd4 ("ring: remove split cacheline build setting") was to add an empty cache line between the producer and consumer data (on platform with cache line size = 64B), preventing from having them on adjacent cache lines. Following discussion on the mailing list, it appears that this also imposes an alignment constraint that is not required. This patch removes the extra alignment constraint and adds the empty cache lines using padding fields in the structure. The size of rte_ring structure and the offset of the fields remain the same on platforms with cache line size = 64B: rte_ring = 384 rte_ring.name = 0 rte_ring.flags = 32 rte_ring.memzone = 40 rte_ring.size = 48 rte_ring.mask = 52 rte_ring.prod = 128 rte_ring.cons = 256 But it has an impact on platform where cache line size is 128B: rte_ring = 384 -> 768 rte_ring.name = 0 rte_ring.flags = 32 rte_ring.memzone = 40 rte_ring.size = 48 rte_ring.mask = 52 rte_ring.prod = 128 -> 256 rte_ring.cons = 256 -> 512 Suggested-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
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