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authorJerin Jacob <jerinj@marvell.com>2019-07-26 10:54:43 +0530
committerThomas Monjalon <thomas@monjalon.net>2019-07-29 22:18:41 +0200
commit5077d8887930e435b6c2120fa717f9fafa2d963d (patch)
treec2e0f5211393d368842207012e6291582859445f /drivers
parent9f741506f838dd25fce1cee0b904590f10f56f1e (diff)
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common/octeontx2: prevent STP instruction fissure
OTX2 AP core can sometimes fissure STP instructions when it is more optimal to send such writes into the pipeline as 2 separate instructions. However registers should be excluded from such optimization. This commit ensures that no CSR write is ever fissured by introducing zero cost workaround by setting STP pre-index by zero to make sure OTX2 AP core prevent fissure. Fixes: 8a4f835971f5 ("common/octeontx2: add IO handling APIs") Signed-off-by: Jerin Jacob <jerinj@marvell.com> Acked-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/common/octeontx2/otx2_io_arm64.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/common/octeontx2/otx2_io_arm64.h b/drivers/common/octeontx2/otx2_io_arm64.h
index 468243c..7e45329 100644
--- a/drivers/common/octeontx2/otx2_io_arm64.h
+++ b/drivers/common/octeontx2/otx2_io_arm64.h
@@ -14,7 +14,7 @@
#define otx2_store_pair(val0, val1, addr) ({ \
asm volatile( \
- "stp %x[x0], %x[x1], [%x[p1]]" \
+ "stp %x[x0], %x[x1], [%x[p1],#0]!" \
::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \
); })