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authorHarman Kalra <hkalra@marvell.com>2019-11-11 05:48:54 +0000
committerFerruh Yigit <ferruh.yigit@intel.com>2019-11-20 17:36:05 +0100
commit35867a370f5dedf24b4efc13fdd01474b80e8721 (patch)
treef64d5717b1dfa4a5977a968395d0fe6d6239fca7 /drivers
parentb26a63510a59e773353a0cb64cbde1b1bcfb410b (diff)
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net/octeontx2: fix PTP configurations for VF
Issue has been observed if PTP is already enabled on PF and later VFs are configured. Since PTP requires mbuf data off to be shifted by 8 bytes, due to this l3fwd/l2fwd was not working with VFs. Also some extra garbage bytes were observed in packet data when ptp was enabled. Fixes: b5dc3140448e ("net/octeontx2: support base PTP") Cc: stable@dpdk.org Signed-off-by: Harman Kalra <hkalra@marvell.com> Acked-by: Jerin Jacob <jerinj@marvell.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/common/octeontx2/otx2_mbox.h1
-rw-r--r--drivers/net/octeontx2/otx2_ethdev.c13
-rw-r--r--drivers/net/octeontx2/otx2_ethdev.h1
-rw-r--r--drivers/net/octeontx2/otx2_ethdev_ops.c2
-rw-r--r--drivers/net/octeontx2/otx2_ptp.c68
-rw-r--r--drivers/net/octeontx2/otx2_rx.h2
6 files changed, 79 insertions, 8 deletions
diff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h
index c2a9e9f..e0e4e2f 100644
--- a/drivers/common/octeontx2/otx2_mbox.h
+++ b/drivers/common/octeontx2/otx2_mbox.h
@@ -723,6 +723,7 @@ struct nix_lf_alloc_rsp {
uint8_t __otx2_io lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
uint16_t __otx2_io cints; /* NIX_AF_CONST2::CINTS */
uint16_t __otx2_io qints; /* NIX_AF_CONST2::QINTS */
+ uint8_t __otx2_io hw_rx_tstamp_en; /*set if rx timestamping enabled */
};
struct nix_lf_free_req {
diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c
index b783cc2..83a76fe 100644
--- a/drivers/net/octeontx2/otx2_ethdev.c
+++ b/drivers/net/octeontx2/otx2_ethdev.c
@@ -86,6 +86,7 @@ nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
dev->cints = rsp->cints;
dev->qints = rsp->qints;
dev->npc_flow.channel = dev->rx_chan_base;
+ dev->ptp_en = rsp->hw_rx_tstamp_en;
return 0;
}
@@ -1900,7 +1901,11 @@ otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int rc, i;
- if (eth_dev->data->nb_rx_queues != 0) {
+ /* MTU recalculate should be avoided here if PTP is enabled by PF, as
+ * otx2_nix_recalc_mtu would be invoked during otx2_nix_ptp_enable_vf
+ * call below.
+ */
+ if (eth_dev->data->nb_rx_queues != 0 && !otx2_ethdev_is_ptp_en(dev)) {
rc = otx2_nix_recalc_mtu(eth_dev);
if (rc)
return rc;
@@ -1936,6 +1941,12 @@ otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
else
otx2_nix_timesync_disable(eth_dev);
+ /* Update VF about data off shifted by 8 bytes if PTP already
+ * enabled in PF owning this VF
+ */
+ if (otx2_ethdev_is_ptp_en(dev) && otx2_dev_is_vf(dev))
+ otx2_nix_ptp_enable_vf(eth_dev);
+
rc = npc_rx_enable(dev);
if (rc) {
otx2_err("Failed to enable NPC rx %d", rc);
diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h
index f366626..00c2c44 100644
--- a/drivers/net/octeontx2/otx2_ethdev.h
+++ b/drivers/net/octeontx2/otx2_ethdev.h
@@ -567,5 +567,6 @@ int otx2_nix_timesync_read_time(struct rte_eth_dev *eth_dev,
int otx2_eth_dev_ptp_info_update(struct otx2_dev *dev, bool ptp_en);
int otx2_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *time);
int otx2_nix_raw_clock_tsc_conv(struct otx2_eth_dev *dev);
+void otx2_nix_ptp_enable_vf(struct rte_eth_dev *eth_dev);
#endif /* __OTX2_ETHDEV_H__ */
diff --git a/drivers/net/octeontx2/otx2_ethdev_ops.c b/drivers/net/octeontx2/otx2_ethdev_ops.c
index d715f40..8f1635d 100644
--- a/drivers/net/octeontx2/otx2_ethdev_ops.c
+++ b/drivers/net/octeontx2/otx2_ethdev_ops.c
@@ -17,6 +17,8 @@ otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
struct nix_frs_cfg *req;
int rc;
+ frame_size += NIX_TIMESYNC_RX_OFFSET * otx2_ethdev_is_ptp_en(dev);
+
/* Check if MTU is within the allowed range */
if (frame_size < NIX_MIN_FRS || frame_size > NIX_MAX_FRS)
return -EINVAL;
diff --git a/drivers/net/octeontx2/otx2_ptp.c b/drivers/net/octeontx2/otx2_ptp.c
index f13f040..f34b933 100644
--- a/drivers/net/octeontx2/otx2_ptp.c
+++ b/drivers/net/octeontx2/otx2_ptp.c
@@ -8,6 +8,38 @@
#define PTP_FREQ_ADJUST (1 << 9)
+/* Function to enable ptp config for VFs */
+void
+otx2_nix_ptp_enable_vf(struct rte_eth_dev *eth_dev)
+{
+ struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
+
+ if (otx2_nix_recalc_mtu(eth_dev))
+ otx2_err("Failed to set MTU size for ptp");
+
+ dev->scalar_ena = true;
+ dev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F;
+
+ /* Setting up the function pointers as per new offload flags */
+ otx2_eth_set_rx_function(eth_dev);
+ otx2_eth_set_tx_function(eth_dev);
+}
+
+static uint16_t
+nix_eth_ptp_vf_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
+{
+ struct otx2_eth_rxq *rxq = queue;
+ struct rte_eth_dev *eth_dev;
+
+ RTE_SET_USED(mbufs);
+ RTE_SET_USED(pkts);
+
+ eth_dev = rxq->eth_dev;
+ otx2_nix_ptp_enable_vf(eth_dev);
+
+ return 0;
+}
+
static int
nix_read_raw_clock(struct otx2_eth_dev *dev, uint64_t *clock, uint64_t *tsc,
uint8_t is_pmu)
@@ -104,7 +136,7 @@ nix_ptp_config(struct rte_eth_dev *eth_dev, int en)
struct otx2_mbox *mbox = dev->mbox;
uint8_t rc = -EINVAL;
- if (otx2_dev_is_vf_or_sdp(dev))
+ if (otx2_dev_is_vf_or_sdp(dev) || otx2_dev_is_lbk(dev))
return rc;
if (en) {
@@ -153,6 +185,17 @@ otx2_eth_dev_ptp_info_update(struct otx2_dev *dev, bool ptp_en)
otx2_nix_rxq_mbuf_setup(otx2_dev,
eth_dev->data->port_id);
}
+ if (otx2_dev_is_vf(otx2_dev) && !(otx2_dev_is_sdp(otx2_dev)) &&
+ !(otx2_dev_is_lbk(otx2_dev))) {
+ /* In case of VF, setting of MTU cant be done directly in this
+ * function as this is running as part of MBOX request(PF->VF)
+ * and MTU setting also requires MBOX message to be
+ * sent(VF->PF)
+ */
+ eth_dev->rx_pkt_burst = nix_eth_ptp_vf_burst;
+ rte_mb();
+ }
+
return 0;
}
@@ -162,14 +205,16 @@ otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev)
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int i, rc = 0;
- if (otx2_ethdev_is_ptp_en(dev)) {
- otx2_info("PTP mode is already enabled ");
+ /* If we are VF/SDP/LBK, ptp cannot not be enabled */
+ if (otx2_dev_is_vf_or_sdp(dev) || otx2_dev_is_lbk(dev)) {
+ otx2_info("PTP cannot be enabled in case of VF/SDP/LBK");
return -EINVAL;
}
- /* If we are VF, no further action can be taken */
- if (otx2_dev_is_vf_or_sdp(dev))
+ if (otx2_ethdev_is_ptp_en(dev)) {
+ otx2_info("PTP mode is already enabled");
return -EINVAL;
+ }
if (!(dev->rx_offload_flags & NIX_RX_OFFLOAD_PTYPE_F)) {
otx2_err("Ptype offload is disabled, it should be enabled");
@@ -207,6 +252,11 @@ otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev)
otx2_eth_set_rx_function(eth_dev);
otx2_eth_set_tx_function(eth_dev);
}
+
+ rc = otx2_nix_recalc_mtu(eth_dev);
+ if (rc)
+ otx2_err("Failed to set MTU size for ptp");
+
return rc;
}
@@ -221,8 +271,7 @@ otx2_nix_timesync_disable(struct rte_eth_dev *eth_dev)
return -EINVAL;
}
- /* If we are VF, nothing else can be done */
- if (otx2_dev_is_vf_or_sdp(dev))
+ if (otx2_dev_is_vf_or_sdp(dev) || otx2_dev_is_lbk(dev))
return -EINVAL;
dev->rx_offloads &= ~DEV_RX_OFFLOAD_TIMESTAMP;
@@ -240,6 +289,11 @@ otx2_nix_timesync_disable(struct rte_eth_dev *eth_dev)
otx2_eth_set_rx_function(eth_dev);
otx2_eth_set_tx_function(eth_dev);
}
+
+ rc = otx2_nix_recalc_mtu(eth_dev);
+ if (rc)
+ otx2_err("Failed to set MTU size for ptp");
+
return rc;
}
diff --git a/drivers/net/octeontx2/otx2_rx.h b/drivers/net/octeontx2/otx2_rx.h
index 1a1ac40..351ad0f 100644
--- a/drivers/net/octeontx2/otx2_rx.h
+++ b/drivers/net/octeontx2/otx2_rx.h
@@ -58,6 +58,8 @@ otx2_nix_mbuf_to_tstamp(struct rte_mbuf *mbuf,
(mbuf->data_off == RTE_PKTMBUF_HEADROOM +
NIX_TIMESYNC_RX_OFFSET)) {
+ mbuf->pkt_len -= NIX_TIMESYNC_RX_OFFSET;
+
/* Reading the rx timestamp inserted by CGX, viz at
* starting of the packet data.
*/