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authorYongseok Koh <yskoh@mellanox.com>2018-05-11 18:35:44 -0700
committerFerruh Yigit <ferruh.yigit@intel.com>2018-05-14 22:32:22 +0100
commit0cfdc1808de82357a924a479dc3f89de88cd91c2 (patch)
tree3de09d2be6606eb2dd7f419e2268bebcfb1d1a06 /drivers
parent5f44cfd011478bcf00430c53f276ddf9b795d443 (diff)
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net/mlx5: use coherent I/O memory barrier
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/mlx5/mlx5_rxtx.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c
index 734ba0b..cdd373e 100644
--- a/drivers/net/mlx5/mlx5_rxtx.c
+++ b/drivers/net/mlx5/mlx5_rxtx.c
@@ -2253,11 +2253,11 @@ mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
}
/* Update the consumer indexes. */
rxq->strd_ci = strd_idx;
- rte_io_wmb();
+ rte_cio_wmb();
*rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
if (rq_ci != rxq->rq_ci) {
rxq->rq_ci = rq_ci;
- rte_io_wmb();
+ rte_cio_wmb();
*rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
}
#ifdef MLX5_PMD_SOFT_COUNTERS