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authorShahaf Shuler <shahafs@mellanox.com>2017-03-02 11:05:44 +0200
committerFerruh Yigit <ferruh.yigit@intel.com>2017-04-04 15:52:51 +0200
commitf5fde520510111ef3068dbb54946da07561a4998 (patch)
treeb131215dbcc1ccddcec814e4d9a45f392b4a6acc /drivers/net/mlx5/mlx5_prm.h
parent3f13f8c23a7cc218cf8f80be270b4c9670f3314f (diff)
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net/mlx5: add hardware checksum offload for tunnel packets
Prior to this commit Tx checksum offload was supported only for the inner headers. This commit adds support for the hardware to compute the checksum for the outer headers as well. The support is for tunneling protocols GRE and VXLAN. Signed-off-by: Shahaf Shuler <shahafs@mellanox.com> Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
Diffstat (limited to 'drivers/net/mlx5/mlx5_prm.h')
-rw-r--r--drivers/net/mlx5/mlx5_prm.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h
index 3318668..0a77f5b 100644
--- a/drivers/net/mlx5/mlx5_prm.h
+++ b/drivers/net/mlx5/mlx5_prm.h
@@ -120,6 +120,12 @@
/* Tunnel packet bit in the CQE. */
#define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
+/* Inner L3 checksum offload (Tunneled packets only). */
+#define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
+
+/* Inner L4 checksum offload (Tunneled packets only). */
+#define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
+
/* INVALID is used by packets matching no flow rules. */
#define MLX5_FLOW_MARK_INVALID 0