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authorViacheslav Ovsiienko <viacheslavo@mellanox.com>2019-07-29 12:41:05 +0000
committerFerruh Yigit <ferruh.yigit@intel.com>2019-07-29 18:05:10 +0200
commit5a93e173b874e549f0adac9796f7284837a98566 (patch)
tree22a93678960cef06be1ff5321e9937135dbaffde /drivers/net/mlx5/mlx5_prm.h
parent9f350504bb328280acff3473879f97eea745e763 (diff)
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net/mlx5: fix Tx completion request generation
The packets transmitting in mlx5 is performed by building Tx descriptors (WQEs) and sending last ones to the NIC. The descriptor can contain the special flags, telling the NIC to generate Tx completion notification (CQEs). At the beginning of tx_burst() routine PMD checks whether there are some Tx completions and frees the transmitted packet buffers. The flags to request completion generation must be set once per specified amount of packets to provide uniform stream of completions and freeing the Tx queue in uniform fashion. The previous implementation sets the completion request generation once per burst, if burst size if big enough it may latency in CQE generation and freeing large amount of buffers in tx_burst routine on multiple completions which also affects the latency and even causes the Tx queue overflow and Tx drops. This patches enforces the completion request will be set in the exact Tx descriptor if specified amount of packets is already sent. Fixes: 18a1c20044c0 ("net/mlx5: implement Tx burst template") Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
Diffstat (limited to 'drivers/net/mlx5/mlx5_prm.h')
-rw-r--r--drivers/net/mlx5/mlx5_prm.h17
1 files changed, 11 insertions, 6 deletions
diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h
index 42ead7d..4ee6d89 100644
--- a/drivers/net/mlx5/mlx5_prm.h
+++ b/drivers/net/mlx5/mlx5_prm.h
@@ -72,7 +72,7 @@
* boundary with accounting the title Control and Ethernet
* segments.
*/
-#define MLX5_EMPW_DEF_INLINE_LEN (3U * MLX5_WQE_SIZE + \
+#define MLX5_EMPW_DEF_INLINE_LEN (3u * MLX5_WQE_SIZE + \
MLX5_DSEG_MIN_INLINE_SIZE - \
MLX5_WQE_DSEG_SIZE)
/*
@@ -90,11 +90,16 @@
* If there are no enough resources to built minimal
* EMPW the sending loop exits.
*/
-#define MLX5_EMPW_MIN_PACKETS (2 + 3 * 4)
-#define MLX5_EMPW_MAX_PACKETS ((MLX5_WQE_SIZE_MAX - \
- MLX5_WQE_CSEG_SIZE - \
- MLX5_WQE_ESEG_SIZE) / \
- MLX5_WSEG_SIZE)
+#define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
+/*
+ * Maximal amount of packets to be sent with EMPW.
+ * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
+ * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
+ * without CQE generation request, being multiplied by
+ * MLX5_TX_COMP_MAX_CQE it may cause significant latency
+ * in tx burst routine at the moment of freeing multiple mbufs.
+ */
+#define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
/*
* Default packet length threshold to be inlined with
* ordinary SEND. Inlining saves the MR key search