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authorMatan Azrad <matan@mellanox.com>2019-07-16 14:34:56 +0000
committerFerruh Yigit <ferruh.yigit@intel.com>2019-07-23 14:31:35 +0200
commit31538ef62ceb23d8cb655b1598c7a6f2da2ab04c (patch)
tree951ace46fe9520a3415e4f8868c6550f0f9470ef /drivers/net/mlx5/mlx5_prm.h
parentf15db67df09c1925e7d62a55931bf694e360d67a (diff)
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net/mlx5: allow basic counter management fallback
In case the asynchronous devx commands are not supported in RDMA core fallback to use a basic counter management. Here, the PMD counters cashe is redundant and the host thread doesn't update it. hence, each counter operation will go to the FW and the acceleration reduces. Signed-off-by: Matan Azrad <matan@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
Diffstat (limited to 'drivers/net/mlx5/mlx5_prm.h')
-rw-r--r--drivers/net/mlx5/mlx5_prm.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h
index 79f852b..95ff29a 100644
--- a/drivers/net/mlx5/mlx5_prm.h
+++ b/drivers/net/mlx5/mlx5_prm.h
@@ -920,7 +920,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_at_343[0x5];
u8 log_max_flow_counter_bulk[0x8];
u8 max_flow_counter_15_0[0x10];
- u8 reserved_at_360[0x3];
+ u8 modify_tis[0x1];
+ u8 flow_counters_dump[0x1];
+ u8 reserved_at_360[0x1];
u8 log_max_rq[0x5];
u8 reserved_at_368[0x3];
u8 log_max_sq[0x5];