path: root/doc/guides/rel_notes/release_18_11.rst
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authorGavin Hu <>2018-11-02 19:21:27 +0800
committerThomas Monjalon <>2018-11-05 14:34:19 +0100
commit9ed877062898dd1eb7150bca56ebbd5329e96ee4 (patch)
treeb43cee0c633c605bf4726e30aa775c0bc408d3da /doc/guides/rel_notes/release_18_11.rst
parent305921f4508d6a4c399ff99036e379e810455b9b (diff)
ring/c11: synchronize load and store of the tail
Synchronize the load-acquire of the tail and the store-release within update_tail, the store release ensures all the ring operations, enqueue or dequeue, are seen by the observers on the other side as soon as they see the updated tail. The load-acquire is needed here as the data dependency is not a reliable way for ordering as the compiler might break it by saving to temporary values to boost performance. When computing the free_entries and avail_entries, use atomic semantics to load the heads and tails instead. The patch was benchmarked with test/ring_perf_autotest and it decreases the enqueue/dequeue latency by 5% ~ 27.6% with two lcores, the real gains are dependent on the number of lcores, depth of the ring, SPSC or MPMC. For 1 lcore, it also improves a little, about 3 ~ 4%. It is a big improvement, in case of MPMC, with two lcores and ring size of 32, it saves latency up to (3.26-2.36)/3.26 = 27.6%. This patch is a bug fix, while the improvement is a bonus. In our analysis the improvement comes from the cacheline pre-filling after hoisting load- acquire from _atomic_compare_exchange_n up above. The test command: $sudo ./test/test/test -l 16-19,44-47,72-75,100-103 -n 4 --socket-mem=\ 1024 -- -i Test result with this patch(two cores): SP/SC bulk enq/dequeue (size: 8): 5.86 MP/MC bulk enq/dequeue (size: 8): 10.15 SP/SC bulk enq/dequeue (size: 32): 1.94 MP/MC bulk enq/dequeue (size: 32): 2.36 In comparison of the test result without this patch: SP/SC bulk enq/dequeue (size: 8): 6.67 MP/MC bulk enq/dequeue (size: 8): 13.12 SP/SC bulk enq/dequeue (size: 32): 2.04 MP/MC bulk enq/dequeue (size: 32): 3.26 Fixes: 39368ebfc6 ("ring: introduce C11 memory model barrier option") Cc: Signed-off-by: Gavin Hu <> Reviewed-by: Honnappa Nagarahalli <> Reviewed-by: Steve Capper <> Reviewed-by: Ola Liljedahl <> Reviewed-by: Jia He <> Acked-by: Jerin Jacob <> Tested-by: Jerin Jacob <> Acked-by: Olivier Matz <>
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