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authorYongseok Koh <yskoh@mellanox.com>2018-05-09 04:09:03 -0700
committerFerruh Yigit <ferruh.yigit@intel.com>2018-05-14 22:31:51 +0100
commitd561b5dc133fd98ddfa2dde237b1aa1d73e4df76 (patch)
tree6c264c5c0118ea71a9ed3c7d62271c4fd62bbe38 /doc/guides/nics/mlx5.rst
parenta4996bd89c42590f8886454a06a994f71acf89dd (diff)
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net/mlx5: remove memory region support
This patch removes current support of Memory Region (MR) in order to accommodate the dynamic memory hotplug patch. This patch can be compiled but traffic can't flow and HW will raise faults. Subsequent patches will add new MR support. Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Diffstat (limited to 'doc/guides/nics/mlx5.rst')
-rw-r--r--doc/guides/nics/mlx5.rst8
1 files changed, 0 insertions, 8 deletions
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index bc08515..5854106 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -167,14 +167,6 @@ These options can be modified in the ``.config`` file.
adds additional run-time checks and debugging messages at the cost of
lower performance.
-- ``CONFIG_RTE_LIBRTE_MLX5_TX_MP_CACHE`` (default **8**)
-
- Maximum number of cached memory pools (MPs) per TX queue. Each MP from
- which buffers are to be transmitted must be associated to memory regions
- (MRs). This is a slow operation that must be cached.
-
- This value is always 1 for RX queues since they use a single MP.
-
Environment variables
~~~~~~~~~~~~~~~~~~~~~