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authorXueming Li <xuemingl@mellanox.com>2018-05-09 08:14:49 +0800
committerFerruh Yigit <ferruh.yigit@intel.com>2018-05-14 22:31:49 +0100
commitc8122e93acfbc1e55117912908320f0f843da45b (patch)
tree95b119e7507fe1bc39791df3b68bf0807fc320aa /doc/guides/nics/mlx5.rst
parent87ff0be1888fc53c5916003c722551cfa4eb9efb (diff)
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net/mlx5: document update for Tx
Add document for hw header parsing and SWP. Signed-off-by: Xueming Li <xuemingl@mellanox.com> Acked-by: Yongseok Koh <yskoh@mellanox.com>
Diffstat (limited to 'doc/guides/nics/mlx5.rst')
-rw-r--r--doc/guides/nics/mlx5.rst4
1 files changed, 2 insertions, 2 deletions
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 853c48f..bc08515 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -69,8 +69,8 @@ Features
- Multiple process.
- KVM and VMware ESX SR-IOV modes are supported.
- RSS hash result is supported.
-- Hardware TSO.
-- Hardware checksum TX offload for VXLAN and GRE.
+- Hardware TSO for generic IP or UDP tunnel, including VXLAN and GRE.
+- Hardware checksum Tx offload for generic IP or UDP tunnel, including VXLAN and GRE.
- RX interrupts.
- Statistics query including Basic, Extended and per queue.
- Rx HW timestamp.