summaryrefslogtreecommitdiff
path: root/doc/guides/nics/mlx5.rst
diff options
context:
space:
mode:
authorYongseok Koh <yskoh@mellanox.com>2019-01-15 09:38:58 -0800
committerFerruh Yigit <ferruh.yigit@intel.com>2019-01-18 09:47:26 +0100
commit78c7a16daad1b3948b84399203cf225aa153a45c (patch)
treed6c5adc9f31c2193a5575cfe467d5f57367c764d /doc/guides/nics/mlx5.rst
parent76469c0631adbc007e89f70f2503ed9b5e3f7f8b (diff)
downloaddpdk-78c7a16daad1b3948b84399203cf225aa153a45c.zip
dpdk-78c7a16daad1b3948b84399203cf225aa153a45c.tar.gz
dpdk-78c7a16daad1b3948b84399203cf225aa153a45c.tar.xz
net/mlx5: fix Rx packet padding
Rx packet padding is supposed to be set by an environment variable - MLX5_PMD_ENABLE_PADDING, but it has been missing for some time by mistake. Rather than using such a variable, a PMD parameter (rxq_pkt_pad_en) is added instead. Fixes: a1366b1a2be3 ("net/mlx5: add reference counter on DPDK Rx queues") Cc: stable@dpdk.org Signed-off-by: Yongseok Koh <yskoh@mellanox.com> Reviewed-by: Erez Ferber <erezf@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
Diffstat (limited to 'doc/guides/nics/mlx5.rst')
-rw-r--r--doc/guides/nics/mlx5.rst27
1 files changed, 13 insertions, 14 deletions
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 5ddca44..3f168b1 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -233,20 +233,6 @@ Environment variables
enabled and most useful when ``CONFIG_RTE_EAL_PMD_PATH`` is also set,
since ``LD_LIBRARY_PATH`` has no effect in this case.
-- ``MLX5_PMD_ENABLE_PADDING``
-
- Enables HW packet padding in PCI bus transactions.
-
- When packet size is cache aligned and CRC stripping is enabled, 4 fewer
- bytes are written to the PCI bus. Enabling padding makes such packets
- aligned again.
-
- In cases where PCI bandwidth is the bottleneck, padding can improve
- performance by 10%.
-
- This is disabled by default since this can also decrease performance for
- unaligned packet sizes.
-
- ``MLX5_SHUT_UP_BF``
Configures HW Tx doorbell register as IO-mapped.
@@ -301,6 +287,19 @@ Run-time configuration
- CPU having 128B cacheline with ConnectX-5 and Bluefield.
+- ``rxq_pkt_pad_en`` parameter [int]
+
+ A nonzero value enables padding Rx packet to the size of cacheline on PCI
+ transaction. This feature would waste PCI bandwidth but could improve
+ performance by avoiding partial cacheline write which may cause costly
+ read-modify-copy in memory transaction on some architectures. Disabled by
+ default.
+
+ Supported on:
+
+ - x86_64 with ConnectX-4, ConnectX-4 LX, ConnectX-5, ConnectX-6 and Bluefield.
+ - POWER8 and ARMv8 with ConnectX-4 LX, ConnectX-5, ConnectX-6 and Bluefield.
+
- ``mprq_en`` parameter [int]
A nonzero value enables configuring Multi-Packet Rx queues. Rx queue is