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authorShahaf Shuler <shahafs@mellanox.com>2017-03-02 11:01:31 +0200
committerFerruh Yigit <ferruh.yigit@intel.com>2017-04-04 15:52:51 +0200
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net/mlx5: support hardware TSO
Implement support for hardware TSO. Signed-off-by: Shahaf Shuler <shahafs@mellanox.com> Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
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diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
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+++ b/doc/guides/nics/mlx5.rst
@@ -90,6 +90,7 @@ Features
- Secondary process TX is supported.
- KVM and VMware ESX SR-IOV modes are supported.
- RSS hash result is supported.
+- Hardware TSO.
Limitations
-----------
@@ -186,9 +187,20 @@ Run-time configuration
save PCI bandwidth and improve performance at the cost of a slightly
higher CPU usage.
+ This option cannot be used in conjunction with ``tso`` below. When ``tso``
+ is set, ``txq_mpw_en`` is disabled.
+
It is currently only supported on the ConnectX-4 Lx and ConnectX-5
families of adapters. Enabled by default.
+- ``tso`` parameter [int]
+
+ A nonzero value enables hardware TSO.
+ When hardware TSO is enabled, packets marked with TCP segmentation
+ offload will be divided into segments by the hardware.
+
+ Disabled by default.
+
Prerequisites
-------------