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authorJerin Jacob <jerin.jacob@caviumnetworks.com>2017-04-26 21:59:19 +0530
committerThomas Monjalon <thomas@monjalon.net>2017-04-30 23:06:23 +0200
commit852572d5db26d1d7d9021648740d9f2e0c4503c1 (patch)
tree2efefba726e10cdcb36a29ebc39266e3642a8c8e /config/defconfig_arm64-armv8a-linuxapp-gcc
parent9a1774b80a63922d5ea343cb4782a1226e2b7100 (diff)
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config: set cache line as 128B for generic arm64
armv8 implementations may have 64B or 128B cache line. Setting to the maximum available cache line size in generic config to address minimum DMA alignment across all arm64 implementations. Increasing the cacheline size has no negative impact to cache invalidation on systems with a smaller cache line. The need for the minimum DMA alignment has impact on functional aspects of the platform so default config should cater the functional aspects. There is an impact on memory usage with this scheme, but that's not too important for the single image arm64 distribution use case. The arm64 linux kernel followed the similar approach for single arm64 image use case. http://lxr.free-electrons.com/source/arch/arm64/include/asm/cache.h Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> Acked-by: Jianbo Liu <jianbo.liu@linaro.org> Acked-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Diffstat (limited to 'config/defconfig_arm64-armv8a-linuxapp-gcc')
-rw-r--r--config/defconfig_arm64-armv8a-linuxapp-gcc5
1 files changed, 5 insertions, 0 deletions
diff --git a/config/defconfig_arm64-armv8a-linuxapp-gcc b/config/defconfig_arm64-armv8a-linuxapp-gcc
index 65888ce..9f32766 100644
--- a/config/defconfig_arm64-armv8a-linuxapp-gcc
+++ b/config/defconfig_arm64-armv8a-linuxapp-gcc
@@ -42,6 +42,11 @@ CONFIG_RTE_FORCE_INTRINSICS=y
CONFIG_RTE_TOOLCHAIN="gcc"
CONFIG_RTE_TOOLCHAIN_GCC=y
+# Maximum available cache line size in arm64 implementations.
+# Setting to maximum available cache line size in generic config
+# to address minimum DMA alignment across all arm64 implementations.
+CONFIG_RTE_CACHE_LINE_SIZE=128
+
CONFIG_RTE_EAL_IGB_UIO=n
CONFIG_RTE_LIBRTE_FM10K_PMD=n