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authorBruce Richardson <bruce.richardson@intel.com>2018-01-22 20:56:29 +0530
committerBruce Richardson <bruce.richardson@intel.com>2018-01-30 21:59:00 +0100
commitb1d48c41189aa8f996db0cf3370abc90402a9984 (patch)
tree0103a608eab02efdb7d93569bdf3f19e7fe3ccf1 /config/arm
parentc22ada8c65daf7da42e263442b9a716bb841f368 (diff)
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build: support ARM with meson
Add files to enable compiling for ARM native/cross builds. This can be tested by doing a cross-compile for armv8-a type using the linaro gcc toolchain. meson arm-build --cross-file aarch64_cross.txt ninja -C arm-build where aarch64_cross.txt contained the following [binaries] c = 'aarch64-linux-gnu-gcc' cpp = 'aarch64-linux-gnu-cpp' ar = 'aarch64-linux-gnu-ar' [host_machine] system = 'linux' cpu_family = 'aarch64' cpu = 'armv8-a' endian = 'little' Signed-off-by: Bruce Richardson <bruce.richardson@intel.com> Signed-off-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com> Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Diffstat (limited to 'config/arm')
-rw-r--r--config/arm/meson.build36
1 files changed, 36 insertions, 0 deletions
diff --git a/config/arm/meson.build b/config/arm/meson.build
new file mode 100644
index 0000000..f05de4c
--- /dev/null
+++ b/config/arm/meson.build
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2017 Intel Corporation.
+# Copyright(c) 2017 Cavium, Inc
+
+# for checking defines we need to use the correct compiler flags
+march_opt = '-march=@0@'.format(machine)
+
+dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
+if cc.sizeof('void *') == 8
+ dpdk_conf.set('RTE_CACHE_LINE_SIZE', 128)
+ dpdk_conf.set('RTE_ARCH_ARM64', 1)
+ dpdk_conf.set('RTE_ARCH_64', 1)
+else
+ dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
+ dpdk_conf.set('RTE_ARCH_ARM', 1)
+ dpdk_conf.set('RTE_ARCH_ARMv7', 1)
+endif
+
+if cc.get_define('__ARM_NEON', args: march_opt) != ''
+ dpdk_conf.set('RTE_MACHINE_CPUFLAG_NEON', 1)
+ compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
+endif
+
+if cc.get_define('__ARM_FEATURE_CRC32', args: march_opt) != ''
+ dpdk_conf.set('RTE_MACHINE_CPUFLAG_CRC32', 1)
+ compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
+endif
+
+if cc.get_define('__ARM_FEATURE_CRYPTO', args: march_opt) != ''
+ dpdk_conf.set('RTE_MACHINE_CPUFLAG_AES', 1)
+ dpdk_conf.set('RTE_MACHINE_CPUFLAG_PMULL', 1)
+ dpdk_conf.set('RTE_MACHINE_CPUFLAG_SHA1', 1)
+ dpdk_conf.set('RTE_MACHINE_CPUFLAG_SHA2', 1)
+ compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
+ 'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']
+endif