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authorPhil Yang <phil.yang@arm.com>2019-09-05 18:55:07 +0800
committerFerruh Yigit <ferruh.yigit@intel.com>2019-09-20 10:19:41 +0200
commit94a24aaf6c5bd0a03c2828e7411d30a4fc0ac075 (patch)
tree1a3cbb99c0c5f3a55d3877a286fa69fe94e5b277
parentb67b4ecbde22015b48d27d1ece9d05128666ad87 (diff)
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net/mlx5: fix Rx CQ doorbell synchronization on aarch64
The Rx completion queue doorbell field needs to be updated after the last CQE decompressed. For the weaker memory model processors, the compiler barrier is not sufficient to guarantee the order of these operations, so use the coherent I/O memory barrier to make sure these fields are updated in order. Fixes: 570acdb1da8a ("net/mlx5: add vectorized Rx/Tx burst for ARM") Cc: stable@dpdk.org Suggested-by: Gavin Hu <gavin.hu@arm.com> Signed-off-by: Phil Yang <phil.yang@arm.com> Reviewed-by: Gavin Hu <gavin.hu@arm.com> Acked-by: Matan Azrad <matan@mellanox.com>
-rw-r--r--drivers/net/mlx5/mlx5_rxtx_vec_neon.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
index 9930286..e914d01 100644
--- a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
+++ b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
@@ -727,7 +727,7 @@ rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n,
rxq->decompressed -= n;
}
}
- rte_compiler_barrier();
+ rte_cio_wmb();
*rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
return rcvd_pkt;
}