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| author | Santosh Shukla <santosh.shukla@caviumnetworks.com> | 2017-01-18 06:51:28 +0530 |
|---|---|---|
| committer | Thomas Monjalon <thomas.monjalon@6wind.com> | 2017-01-18 17:18:27 +0100 |
| commit | b1cbca1e7f4d2fd2a3323f636f53faabcb89f79c (patch) | |
| tree | 48499a567ac90a1ead8cbfab364bdf55dc362df0 | |
| parent | 635acf386acbfad7b5e56f84371404e3cecbf73b (diff) | |
| download | dpdk-b1cbca1e7f4d2fd2a3323f636f53faabcb89f79c.zip dpdk-b1cbca1e7f4d2fd2a3323f636f53faabcb89f79c.tar.gz dpdk-b1cbca1e7f4d2fd2a3323f636f53faabcb89f79c.tar.xz | |
crypto/qat: use I/O device memory read/write API
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix portability
issues across different architectures.
CC: John Griffin <john.griffin@intel.com>
CC: Fiona Trahe <fiona.trahe@intel.com>
CC: Deepak Kumar Jain <deepak.k.jain@intel.com>
Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
| -rw-r--r-- | drivers/crypto/qat/qat_adf/adf_transport_access_macros.h | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h b/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h index 47f1c91..d218f85 100644 --- a/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h +++ b/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h @@ -47,14 +47,15 @@ #ifndef ADF_TRANSPORT_ACCESS_MACROS_H #define ADF_TRANSPORT_ACCESS_MACROS_H +#include <rte_io.h> + /* CSR write macro */ -#define ADF_CSR_WR(csrAddr, csrOffset, val) \ - (void)((*((volatile uint32_t *)(((uint8_t *)csrAddr) + csrOffset)) \ - = (val))) +#define ADF_CSR_WR(csrAddr, csrOffset, val) \ + rte_write32(val, (((uint8_t *)csrAddr) + csrOffset)) /* CSR read macro */ -#define ADF_CSR_RD(csrAddr, csrOffset) \ - (*((volatile uint32_t *)(((uint8_t *)csrAddr) + csrOffset))) +#define ADF_CSR_RD(csrAddr, csrOffset) \ + rte_read32((((uint8_t *)csrAddr) + csrOffset)) #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL |