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authorAlejandro Lucero <alejandro.lucero@netronome.com>2018-08-31 15:53:52 +0100
committerYongseok Koh <yskoh@mellanox.com>2018-08-31 15:00:39 -0700
commit6f43d909b39607af7200a735cb0f959853d5fef6 (patch)
treef68676c2fa6611a9d90820462715364273e6dbba
parentf0aec3ec55cef8ec38811e69a08b0945fd2e39d7 (diff)
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mem: fix max DMA maskbit size
The sanity check inside rte_eal_check_dma_mask is using 47 bits as the maximum size. It turns out there are some IOMMU hardware reporting 48 bits precluding the IOVA VA mode to be enabled. It is harmless to raise the maximum mask size to 63 bits. This patch also removes any reference to unused X86_VA_WIDTH. Fixes: 3a80bc50c949 ("mem: add function for checking memsegs IOVAs addresses") Signed-off-by: Alejandro Lucero <alejandro.lucero@netronome.com>
-rw-r--r--drivers/bus/pci/linux/pci.c1
-rw-r--r--lib/librte_eal/common/eal_common_memory.c5
2 files changed, 0 insertions, 6 deletions
diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c
index c81ed50..44440f2 100644
--- a/drivers/bus/pci/linux/pci.c
+++ b/drivers/bus/pci/linux/pci.c
@@ -583,7 +583,6 @@ pci_one_device_iommu_support_va(struct rte_pci_device *dev)
{
#define VTD_CAP_MGAW_SHIFT 16
#define VTD_CAP_MGAW_MASK (0x3fULL << VTD_CAP_MGAW_SHIFT)
-#define X86_VA_WIDTH 47 /* From Documentation/x86/x86_64/mm.txt */
struct rte_pci_addr *addr = &dev->addr;
char filename[PATH_MAX];
FILE *fp;
diff --git a/lib/librte_eal/common/eal_common_memory.c b/lib/librte_eal/common/eal_common_memory.c
index 00ab393..a0922f1 100644
--- a/lib/librte_eal/common/eal_common_memory.c
+++ b/lib/librte_eal/common/eal_common_memory.c
@@ -109,13 +109,8 @@ rte_dump_physmem_layout(FILE *f)
}
}
-#if defined(RTE_ARCH_X86)
-#define X86_VA_WIDTH 47 /* From Documentation/x86/x86_64/mm.txt */
-#define MAX_DMA_MASK_BITS X86_VA_WIDTH
-#else
/* 63 bits is good enough for a sanity check */
#define MAX_DMA_MASK_BITS 63
-#endif
/* check memseg iovas are within the required range based on dma mask */
int