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| author | Xiaoyu Min <jackmin@mellanox.com> | 2019-08-02 17:18:23 +0800 |
|---|---|---|
| committer | Kevin Traynor <ktraynor@redhat.com> | 2019-09-13 10:37:20 +0100 |
| commit | 0a2cd71d461862ea38e693b1b53163157265f991 (patch) | |
| tree | f6b13f6f114fd066ae9fdde13d17b637783fd3e8 | |
| parent | 0f408a9cea146c1ae7d5c598f681ff162a13982f (diff) | |
| download | dpdk-stable-0a2cd71d461862ea38e693b1b53163157265f991.zip dpdk-stable-0a2cd71d461862ea38e693b1b53163157265f991.tar.gz dpdk-stable-0a2cd71d461862ea38e693b1b53163157265f991.tar.xz | |
net/mlx5: fix VLAN inner type matching on DR/DV
[ upstream commit b12c7b23680159dd3e6d24e649e1761fc4f9cdcf ]
The rte_flow_item_vlan has the inner_type, which is missing on
DR/DV flow engine.
By adding this support, the example testpmd commands could be:
- matching all vlan traffic with id 2:
testpmd> flow create 0 ingress pattern eth / vlan vid is 2 / end
actions queue index 2 / end
- matching all ipv4 traffic in vlan with id 2:
testpmd> flow create 0 ingress pattern eth / vlan vid is 2
inner_type is 0x0800 / end actions queue index 2 / end
Fixes: fc2c498ccb94 ("net/mlx5: add Direct Verbs translate items")
Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
| -rw-r--r-- | drivers/net/mlx5/mlx5_flow_dv.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 207edcb..3b514d6 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1176,10 +1176,6 @@ flow_dv_translate_item_vlan(void *matcher, void *key, { const struct rte_flow_item_vlan *vlan_m = item->mask; const struct rte_flow_item_vlan *vlan_v = item->spec; - const struct rte_flow_item_vlan nic_mask = { - .tci = RTE_BE16(0x0fff), - .inner_type = RTE_BE16(0xffff), - }; void *headers_m; void *headers_v; uint16_t tci_m; @@ -1188,7 +1184,7 @@ flow_dv_translate_item_vlan(void *matcher, void *key, if (!vlan_v) return; if (!vlan_m) - vlan_m = &nic_mask; + vlan_m = &rte_flow_item_vlan_mask; if (inner) { headers_m = MLX5_ADDR_OF(fte_match_param, matcher, inner_headers); @@ -1208,6 +1204,10 @@ flow_dv_translate_item_vlan(void *matcher, void *key, MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12); MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13); MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13); + MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, + rte_be_to_cpu_16(vlan_m->inner_type)); + MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, + rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type)); } /** |