summaryrefslogtreecommitdiff
path: root/drivers/net/mvpp2/mrvl_ethdev.c
blob: c9d85ca0dfe830b215475bfb104e3486a7f0668e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2017 Marvell International Ltd.
 * Copyright(c) 2017 Semihalf.
 * All rights reserved.
 */

#include <rte_ethdev_driver.h>
#include <rte_kvargs.h>
#include <rte_log.h>
#include <rte_malloc.h>
#include <rte_bus_vdev.h>

/* Unluckily, container_of is defined by both DPDK and MUSDK,
 * we'll declare only one version.
 *
 * Note that it is not used in this PMD anyway.
 */
#ifdef container_of
#undef container_of
#endif

#include <fcntl.h>
#include <linux/ethtool.h>
#include <linux/sockios.h>
#include <net/if.h>
#include <net/if_arp.h>
#include <sys/ioctl.h>
#include <sys/socket.h>
#include <sys/stat.h>
#include <sys/types.h>

#include "mrvl_ethdev.h"
#include "mrvl_qos.h"

/* bitmask with reserved hifs */
#define MRVL_MUSDK_HIFS_RESERVED 0x0F
/* bitmask with reserved bpools */
#define MRVL_MUSDK_BPOOLS_RESERVED 0x07
/* bitmask with reserved kernel RSS tables */
#define MRVL_MUSDK_RSS_RESERVED 0x01
/* maximum number of available hifs */
#define MRVL_MUSDK_HIFS_MAX 9

/* prefetch shift */
#define MRVL_MUSDK_PREFETCH_SHIFT 2

/* TCAM has 25 entries reserved for uc/mc filter entries */
#define MRVL_MAC_ADDRS_MAX 25
#define MRVL_MATCH_LEN 16
#define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
/* Maximum allowable packet size */
#define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)

#define MRVL_IFACE_NAME_ARG "iface"
#define MRVL_CFG_ARG "cfg"

#define MRVL_BURST_SIZE 64

#define MRVL_ARP_LENGTH 28

#define MRVL_COOKIE_ADDR_INVALID ~0ULL

#define MRVL_COOKIE_HIGH_ADDR_SHIFT	(sizeof(pp2_cookie_t) * 8)
#define MRVL_COOKIE_HIGH_ADDR_MASK	(~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)

/* Memory size (in bytes) for MUSDK dma buffers */
#define MRVL_MUSDK_DMA_MEMSIZE 41943040

/** Port Rx offload capabilities */
#define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
			  DEV_RX_OFFLOAD_JUMBO_FRAME | \
			  DEV_RX_OFFLOAD_CRC_STRIP | \
			  DEV_RX_OFFLOAD_CHECKSUM)

/** Port Tx offloads capabilities */
#define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \
			  DEV_TX_OFFLOAD_UDP_CKSUM | \
			  DEV_TX_OFFLOAD_TCP_CKSUM)

static const char * const valid_args[] = {
	MRVL_IFACE_NAME_ARG,
	MRVL_CFG_ARG,
	NULL
};

static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
static struct pp2_hif *hifs[RTE_MAX_LCORE];
static int used_bpools[PP2_NUM_PKT_PROC] = {
	MRVL_MUSDK_BPOOLS_RESERVED,
	MRVL_MUSDK_BPOOLS_RESERVED
};

struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;

struct mrvl_ifnames {
	const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
	int idx;
};

/*
 * To use buffer harvesting based on loopback port shadow queue structure
 * was introduced for buffers information bookkeeping.
 *
 * Before sending the packet, related buffer information (pp2_buff_inf) is
 * stored in shadow queue. After packet is transmitted no longer used
 * packet buffer is released back to it's original hardware pool,
 * on condition it originated from interface.
 * In case it  was generated by application itself i.e: mbuf->port field is
 * 0xff then its released to software mempool.
 */
struct mrvl_shadow_txq {
	int head;           /* write index - used when sending buffers */
	int tail;           /* read index - used when releasing buffers */
	u16 size;           /* queue occupied size */
	u16 num_to_release; /* number of buffers sent, that can be released */
	struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
};

struct mrvl_rxq {
	struct mrvl_priv *priv;
	struct rte_mempool *mp;
	int queue_id;
	int port_id;
	int cksum_enabled;
	uint64_t bytes_recv;
	uint64_t drop_mac;
};

struct mrvl_txq {
	struct mrvl_priv *priv;
	int queue_id;
	int port_id;
	uint64_t bytes_sent;
	struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
	int tx_deferred_start;
};

static int mrvl_lcore_first;
static int mrvl_lcore_last;
static int mrvl_dev_num;

static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
			struct pp2_hif *hif, unsigned int core_id,
			struct mrvl_shadow_txq *sq, int qid, int force);

#define MRVL_XSTATS_TBL_ENTRY(name) { \
	#name, offsetof(struct pp2_ppio_statistics, name),	\
	sizeof(((struct pp2_ppio_statistics *)0)->name)		\
}

/* Table with xstats data */
static struct {
	const char *name;
	unsigned int offset;
	unsigned int size;
} mrvl_xstats_tbl[] = {
	MRVL_XSTATS_TBL_ENTRY(rx_bytes),
	MRVL_XSTATS_TBL_ENTRY(rx_packets),
	MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets),
	MRVL_XSTATS_TBL_ENTRY(rx_errors),
	MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped),
	MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped),
	MRVL_XSTATS_TBL_ENTRY(rx_early_dropped),
	MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped),
	MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped),
	MRVL_XSTATS_TBL_ENTRY(tx_bytes),
	MRVL_XSTATS_TBL_ENTRY(tx_packets),
	MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets),
	MRVL_XSTATS_TBL_ENTRY(tx_errors)
};

static inline int
mrvl_get_bpool_size(int pp2_id, int pool_id)
{
	int i;
	int size = 0;

	for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
		size += mrvl_port_bpool_size[pp2_id][pool_id][i];

	return size;
}

static inline int
mrvl_reserve_bit(int *bitmap, int max)
{
	int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);

	if (n >= max)
		return -1;

	*bitmap |= 1 << n;

	return n;
}

static int
mrvl_init_hif(int core_id)
{
	struct pp2_hif_params params;
	char match[MRVL_MATCH_LEN];
	int ret;

	ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
	if (ret < 0) {
		RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
		return ret;
	}

	snprintf(match, sizeof(match), "hif-%d", ret);
	memset(&params, 0, sizeof(params));
	params.match = match;
	params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
	ret = pp2_hif_init(&params, &hifs[core_id]);
	if (ret) {
		RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", core_id);
		return ret;
	}

	return 0;
}

static inline struct pp2_hif*
mrvl_get_hif(struct mrvl_priv *priv, int core_id)
{
	int ret;

	if (likely(hifs[core_id] != NULL))
		return hifs[core_id];

	rte_spinlock_lock(&priv->lock);

	ret = mrvl_init_hif(core_id);
	if (ret < 0) {
		RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
		goto out;
	}

	if (core_id < mrvl_lcore_first)
		mrvl_lcore_first = core_id;

	if (core_id > mrvl_lcore_last)
		mrvl_lcore_last = core_id;
out:
	rte_spinlock_unlock(&priv->lock);

	return hifs[core_id];
}

/**
 * Configure rss based on dpdk rss configuration.
 *
 * @param priv
 *   Pointer to private structure.
 * @param rss_conf
 *   Pointer to RSS configuration.
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static int
mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
{
	if (rss_conf->rss_key)
		RTE_LOG(WARNING, PMD, "Changing hash key is not supported\n");

	if (rss_conf->rss_hf == 0) {
		priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
	} else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
		priv->ppio_params.inqs_params.hash_type =
			PP2_PPIO_HASH_T_2_TUPLE;
	} else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
		priv->ppio_params.inqs_params.hash_type =
			PP2_PPIO_HASH_T_5_TUPLE;
		priv->rss_hf_tcp = 1;
	} else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
		priv->ppio_params.inqs_params.hash_type =
			PP2_PPIO_HASH_T_5_TUPLE;
		priv->rss_hf_tcp = 0;
	} else {
		return -EINVAL;
	}

	return 0;
}

/**
 * Ethernet device configuration.
 *
 * Prepare the driver for a given number of TX and RX queues and
 * configure RSS.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static int
mrvl_dev_configure(struct rte_eth_dev *dev)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	int ret;

	if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
	    dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
		RTE_LOG(INFO, PMD, "Unsupported rx multi queue mode %d\n",
			dev->data->dev_conf.rxmode.mq_mode);
		return -EINVAL;
	}

	if (!(dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
		RTE_LOG(INFO, PMD,
			"L2 CRC stripping is always enabled in hw\n");
		dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
	}

	if (dev->data->dev_conf.rxmode.split_hdr_size) {
		RTE_LOG(INFO, PMD, "Split headers not supported\n");
		return -EINVAL;
	}

	if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
		dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
				 ETHER_HDR_LEN - ETHER_CRC_LEN;

	ret = mrvl_configure_rxqs(priv, dev->data->port_id,
				  dev->data->nb_rx_queues);
	if (ret < 0)
		return ret;

	ret = mrvl_configure_txqs(priv, dev->data->port_id,
				  dev->data->nb_tx_queues);
	if (ret < 0)
		return ret;

	priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
	priv->ppio_params.maintain_stats = 1;
	priv->nb_rx_queues = dev->data->nb_rx_queues;

	if (dev->data->nb_rx_queues == 1 &&
	    dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
		RTE_LOG(WARNING, PMD, "Disabling hash for 1 rx queue\n");
		priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;

		return 0;
	}

	return mrvl_configure_rss(priv,
				  &dev->data->dev_conf.rx_adv_conf.rss_conf);
}

/**
 * DPDK callback to change the MTU.
 *
 * Setting the MTU affects hardware MRU (packets larger than the MRU
 * will be dropped).
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 * @param mtu
 *   New MTU.
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static int
mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	/* extra MV_MH_SIZE bytes are required for Marvell tag */
	uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
	int ret;

	if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
		return -EINVAL;

	if (!priv->ppio)
		return 0;

	ret = pp2_ppio_set_mru(priv->ppio, mru);
	if (ret)
		return ret;

	return pp2_ppio_set_mtu(priv->ppio, mtu);
}

/**
 * DPDK callback to bring the link up.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static int
mrvl_dev_set_link_up(struct rte_eth_dev *dev)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	int ret;

	if (!priv->ppio)
		return -EPERM;

	ret = pp2_ppio_enable(priv->ppio);
	if (ret)
		return ret;

	/*
	 * mtu/mru can be updated if pp2_ppio_enable() was called at least once
	 * as pp2_ppio_enable() changes port->t_mode from default 0 to
	 * PP2_TRAFFIC_INGRESS_EGRESS.
	 *
	 * Set mtu to default DPDK value here.
	 */
	ret = mrvl_mtu_set(dev, dev->data->mtu);
	if (ret)
		pp2_ppio_disable(priv->ppio);

	return ret;
}

/**
 * DPDK callback to bring the link down.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static int
mrvl_dev_set_link_down(struct rte_eth_dev *dev)
{
	struct mrvl_priv *priv = dev->data->dev_private;

	if (!priv->ppio)
		return -EPERM;

	return pp2_ppio_disable(priv->ppio);
}

/**
 * DPDK callback to start tx queue.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 * @param queue_id
 *   Transmit queue index.
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static int
mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	int ret;

	if (!priv)
		return -EPERM;

	/* passing 1 enables given tx queue */
	ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1);
	if (ret) {
		RTE_LOG(ERR, PMD, "Failed to start txq %d\n", queue_id);
		return ret;
	}

	dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED;

	return 0;
}

/**
 * DPDK callback to stop tx queue.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 * @param queue_id
 *   Transmit queue index.
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static int
mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	int ret;

	if (!priv->ppio)
		return -EPERM;

	/* passing 0 disables given tx queue */
	ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0);
	if (ret) {
		RTE_LOG(ERR, PMD, "Failed to stop txq %d\n", queue_id);
		return ret;
	}

	dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;

	return 0;
}

/**
 * DPDK callback to start the device.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 *
 * @return
 *   0 on success, negative errno value on failure.
 */
static int
mrvl_dev_start(struct rte_eth_dev *dev)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	char match[MRVL_MATCH_LEN];
	int ret = 0, i, def_init_size;

	snprintf(match, sizeof(match), "ppio-%d:%d",
		 priv->pp_id, priv->ppio_id);
	priv->ppio_params.match = match;

	/*
	 * Calculate the minimum bpool size for refill feature as follows:
	 * 2 default burst sizes multiply by number of rx queues.
	 * If the bpool size will be below this value, new buffers will
	 * be added to the pool.
	 */
	priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;

	/* In case initial bpool size configured in queues setup is
	 * smaller than minimum size add more buffers
	 */
	def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
	if (priv->bpool_init_size < def_init_size) {
		int buffs_to_add = def_init_size - priv->bpool_init_size;

		priv->bpool_init_size += buffs_to_add;
		ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
		if (ret)
			RTE_LOG(ERR, PMD, "Failed to add buffers to bpool\n");
	}

	/*
	 * Calculate the maximum bpool size for refill feature as follows:
	 * maximum number of descriptors in rx queue multiply by number
	 * of rx queues plus minimum bpool size.
	 * In case the bpool size will exceed this value, superfluous buffers
	 * will be removed
	 */
	priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
				priv->bpool_min_size;

	ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
	if (ret) {
		RTE_LOG(ERR, PMD, "Failed to init ppio\n");
		return ret;
	}

	/*
	 * In case there are some some stale uc/mc mac addresses flush them
	 * here. It cannot be done during mrvl_dev_close() as port information
	 * is already gone at that point (due to pp2_ppio_deinit() in
	 * mrvl_dev_stop()).
	 */
	if (!priv->uc_mc_flushed) {
		ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
		if (ret) {
			RTE_LOG(ERR, PMD,
				"Failed to flush uc/mc filter list\n");
			goto out;
		}
		priv->uc_mc_flushed = 1;
	}

	if (!priv->vlan_flushed) {
		ret = pp2_ppio_flush_vlan(priv->ppio);
		if (ret) {
			RTE_LOG(ERR, PMD, "Failed to flush vlan list\n");
			/*
			 * TODO
			 * once pp2_ppio_flush_vlan() is supported jump to out
			 * goto out;
			 */
		}
		priv->vlan_flushed = 1;
	}

	/* For default QoS config, don't start classifier. */
	if (mrvl_qos_cfg) {
		ret = mrvl_start_qos_mapping(priv);
		if (ret) {
			RTE_LOG(ERR, PMD, "Failed to setup QoS mapping\n");
			goto out;
		}
	}

	ret = mrvl_dev_set_link_up(dev);
	if (ret) {
		RTE_LOG(ERR, PMD, "Failed to set link up\n");
		goto out;
	}

	/* start tx queues */
	for (i = 0; i < dev->data->nb_tx_queues; i++) {
		struct mrvl_txq *txq = dev->data->tx_queues[i];

		dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;

		if (!txq->tx_deferred_start)
			continue;

		/*
		 * All txqs are started by default. Stop them
		 * so that tx_deferred_start works as expected.
		 */
		ret = mrvl_tx_queue_stop(dev, i);
		if (ret)
			goto out;
	}

	return 0;
out:
	RTE_LOG(ERR, PMD, "Failed to start device\n");
	pp2_ppio_deinit(priv->ppio);
	return ret;
}

/**
 * Flush receive queues.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 */
static void
mrvl_flush_rx_queues(struct rte_eth_dev *dev)
{
	int i;

	RTE_LOG(INFO, PMD, "Flushing rx queues\n");
	for (i = 0; i < dev->data->nb_rx_queues; i++) {
		int ret, num;

		do {
			struct mrvl_rxq *q = dev->data->rx_queues[i];
			struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];

			num = MRVL_PP2_RXD_MAX;
			ret = pp2_ppio_recv(q->priv->ppio,
					    q->priv->rxq_map[q->queue_id].tc,
					    q->priv->rxq_map[q->queue_id].inq,
					    descs, (uint16_t *)&num);
		} while (ret == 0 && num);
	}
}

/**
 * Flush transmit shadow queues.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 */
static void
mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
{
	int i, j;
	struct mrvl_txq *txq;

	RTE_LOG(INFO, PMD, "Flushing tx shadow queues\n");
	for (i = 0; i < dev->data->nb_tx_queues; i++) {
		txq = (struct mrvl_txq *)dev->data->tx_queues[i];

		for (j = 0; j < RTE_MAX_LCORE; j++) {
			struct mrvl_shadow_txq *sq;

			if (!hifs[j])
				continue;

			sq = &txq->shadow_txqs[j];
			mrvl_free_sent_buffers(txq->priv->ppio,
				hifs[j], j, sq, txq->queue_id, 1);
			while (sq->tail != sq->head) {
				uint64_t addr = cookie_addr_high |
					sq->ent[sq->tail].buff.cookie;
				rte_pktmbuf_free(
					(struct rte_mbuf *)addr);
				sq->tail = (sq->tail + 1) &
					    MRVL_PP2_TX_SHADOWQ_MASK;
			}
			memset(sq, 0, sizeof(*sq));
		}
	}
}

/**
 * Flush hardware bpool (buffer-pool).
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 */
static void
mrvl_flush_bpool(struct rte_eth_dev *dev)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	struct pp2_hif *hif;
	uint32_t num;
	int ret;
	unsigned int core_id = rte_lcore_id();

	if (core_id == LCORE_ID_ANY)
		core_id = 0;

	hif = mrvl_get_hif(priv, core_id);

	ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
	if (ret) {
		RTE_LOG(ERR, PMD, "Failed to get bpool buffers number\n");
		return;
	}

	while (num--) {
		struct pp2_buff_inf inf;
		uint64_t addr;

		ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
		if (ret)
			break;

		addr = cookie_addr_high | inf.cookie;
		rte_pktmbuf_free((struct rte_mbuf *)addr);
	}
}

/**
 * DPDK callback to stop the device.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 */
static void
mrvl_dev_stop(struct rte_eth_dev *dev)
{
	struct mrvl_priv *priv = dev->data->dev_private;

	mrvl_dev_set_link_down(dev);
	mrvl_flush_rx_queues(dev);
	mrvl_flush_tx_shadow_queues(dev);
	if (priv->cls_tbl) {
		pp2_cls_tbl_deinit(priv->cls_tbl);
		priv->cls_tbl = NULL;
	}
	if (priv->qos_tbl) {
		pp2_cls_qos_tbl_deinit(priv->qos_tbl);
		priv->qos_tbl = NULL;
	}
	if (priv->ppio)
		pp2_ppio_deinit(priv->ppio);
	priv->ppio = NULL;

	/* policer must be released after ppio deinitialization */
	if (priv->policer) {
		pp2_cls_plcr_deinit(priv->policer);
		priv->policer = NULL;
	}
}

/**
 * DPDK callback to close the device.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 */
static void
mrvl_dev_close(struct rte_eth_dev *dev)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	size_t i;

	for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
		struct pp2_ppio_tc_params *tc_params =
			&priv->ppio_params.inqs_params.tcs_params[i];

		if (tc_params->inqs_params) {
			rte_free(tc_params->inqs_params);
			tc_params->inqs_params = NULL;
		}
	}

	mrvl_flush_bpool(dev);
}

/**
 * DPDK callback to retrieve physical link information.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 * @param wait_to_complete
 *   Wait for request completion (ignored).
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static int
mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
{
	/*
	 * TODO
	 * once MUSDK provides necessary API use it here
	 */
	struct mrvl_priv *priv = dev->data->dev_private;
	struct ethtool_cmd edata;
	struct ifreq req;
	int ret, fd, link_up;

	if (!priv->ppio)
		return -EPERM;

	edata.cmd = ETHTOOL_GSET;

	strcpy(req.ifr_name, dev->data->name);
	req.ifr_data = (void *)&edata;

	fd = socket(AF_INET, SOCK_DGRAM, 0);
	if (fd == -1)
		return -EFAULT;

	ret = ioctl(fd, SIOCETHTOOL, &req);
	if (ret == -1) {
		close(fd);
		return -EFAULT;
	}

	close(fd);

	switch (ethtool_cmd_speed(&edata)) {
	case SPEED_10:
		dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
		break;
	case SPEED_100:
		dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
		break;
	case SPEED_1000:
		dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
		break;
	case SPEED_10000:
		dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
		break;
	default:
		dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
	}

	dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
							 ETH_LINK_HALF_DUPLEX;
	dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
							   ETH_LINK_FIXED;
	pp2_ppio_get_link_state(priv->ppio, &link_up);
	dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;

	return 0;
}

/**
 * DPDK callback to enable promiscuous mode.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 */
static void
mrvl_promiscuous_enable(struct rte_eth_dev *dev)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	int ret;

	if (!priv->ppio)
		return;

	if (priv->isolated)
		return;

	ret = pp2_ppio_set_promisc(priv->ppio, 1);
	if (ret)
		RTE_LOG(ERR, PMD, "Failed to enable promiscuous mode\n");
}

/**
 * DPDK callback to enable allmulti mode.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 */
static void
mrvl_allmulticast_enable(struct rte_eth_dev *dev)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	int ret;

	if (!priv->ppio)
		return;

	if (priv->isolated)
		return;

	ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
	if (ret)
		RTE_LOG(ERR, PMD, "Failed enable all-multicast mode\n");
}

/**
 * DPDK callback to disable promiscuous mode.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 */
static void
mrvl_promiscuous_disable(struct rte_eth_dev *dev)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	int ret;

	if (!priv->ppio)
		return;

	ret = pp2_ppio_set_promisc(priv->ppio, 0);
	if (ret)
		RTE_LOG(ERR, PMD, "Failed to disable promiscuous mode\n");
}

/**
 * DPDK callback to disable allmulticast mode.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 */
static void
mrvl_allmulticast_disable(struct rte_eth_dev *dev)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	int ret;

	if (!priv->ppio)
		return;

	ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
	if (ret)
		RTE_LOG(ERR, PMD, "Failed to disable all-multicast mode\n");
}

/**
 * DPDK callback to remove a MAC address.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 * @param index
 *   MAC address index.
 */
static void
mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	char buf[ETHER_ADDR_FMT_SIZE];
	int ret;

	if (!priv->ppio)
		return;

	if (priv->isolated)
		return;

	ret = pp2_ppio_remove_mac_addr(priv->ppio,
				       dev->data->mac_addrs[index].addr_bytes);
	if (ret) {
		ether_format_addr(buf, sizeof(buf),
				  &dev->data->mac_addrs[index]);
		RTE_LOG(ERR, PMD, "Failed to remove mac %s\n", buf);
	}
}

/**
 * DPDK callback to add a MAC address.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 * @param mac_addr
 *   MAC address to register.
 * @param index
 *   MAC address index.
 * @param vmdq
 *   VMDq pool index to associate address with (unused).
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static int
mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
		  uint32_t index, uint32_t vmdq __rte_unused)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	char buf[ETHER_ADDR_FMT_SIZE];
	int ret;

	if (priv->isolated)
		return -ENOTSUP;

	if (index == 0)
		/* For setting index 0, mrvl_mac_addr_set() should be used.*/
		return -1;

	if (!priv->ppio)
		return 0;

	/*
	 * Maximum number of uc addresses can be tuned via kernel module mvpp2x
	 * parameter uc_filter_max. Maximum number of mc addresses is then
	 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
	 * 21 respectively.
	 *
	 * If more than uc_filter_max uc addresses were added to filter list
	 * then NIC will switch to promiscuous mode automatically.
	 *
	 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
	 * were added to filter list then NIC will switch to all-multicast mode
	 * automatically.
	 */
	ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
	if (ret) {
		ether_format_addr(buf, sizeof(buf), mac_addr);
		RTE_LOG(ERR, PMD, "Failed to add mac %s\n", buf);
		return -1;
	}

	return 0;
}

/**
 * DPDK callback to set the primary MAC address.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 * @param mac_addr
 *   MAC address to register.
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static int
mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	int ret;

	if (!priv->ppio)
		return 0;

	if (priv->isolated)
		return -ENOTSUP;

	ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
	if (ret) {
		char buf[ETHER_ADDR_FMT_SIZE];
		ether_format_addr(buf, sizeof(buf), mac_addr);
		RTE_LOG(ERR, PMD, "Failed to set mac to %s\n", buf);
	}

	return ret;
}

/**
 * DPDK callback to get device statistics.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 * @param stats
 *   Stats structure output buffer.
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static int
mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	struct pp2_ppio_statistics ppio_stats;
	uint64_t drop_mac = 0;
	unsigned int i, idx, ret;

	if (!priv->ppio)
		return -EPERM;

	for (i = 0; i < dev->data->nb_rx_queues; i++) {
		struct mrvl_rxq *rxq = dev->data->rx_queues[i];
		struct pp2_ppio_inq_statistics rx_stats;

		if (!rxq)
			continue;

		idx = rxq->queue_id;
		if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
			RTE_LOG(ERR, PMD,
				"rx queue %d stats out of range (0 - %d)\n",
				idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
			continue;
		}

		ret = pp2_ppio_inq_get_statistics(priv->ppio,
						  priv->rxq_map[idx].tc,
						  priv->rxq_map[idx].inq,
						  &rx_stats, 0);
		if (unlikely(ret)) {
			RTE_LOG(ERR, PMD,
				"Failed to update rx queue %d stats\n", idx);
			break;
		}

		stats->q_ibytes[idx] = rxq->bytes_recv;
		stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
		stats->q_errors[idx] = rx_stats.drop_early +
				       rx_stats.drop_fullq +
				       rx_stats.drop_bm +
				       rxq->drop_mac;
		stats->ibytes += rxq->bytes_recv;
		drop_mac += rxq->drop_mac;
	}

	for (i = 0; i < dev->data->nb_tx_queues; i++) {
		struct mrvl_txq *txq = dev->data->tx_queues[i];
		struct pp2_ppio_outq_statistics tx_stats;

		if (!txq)
			continue;

		idx = txq->queue_id;
		if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
			RTE_LOG(ERR, PMD,
				"tx queue %d stats out of range (0 - %d)\n",
				idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
		}

		ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
						   &tx_stats, 0);
		if (unlikely(ret)) {
			RTE_LOG(ERR, PMD,
				"Failed to update tx queue %d stats\n", idx);
			break;
		}

		stats->q_opackets[idx] = tx_stats.deq_desc;
		stats->q_obytes[idx] = txq->bytes_sent;
		stats->obytes += txq->bytes_sent;
	}

	ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
	if (unlikely(ret)) {
		RTE_LOG(ERR, PMD, "Failed to update port statistics\n");
		return ret;
	}

	stats->ipackets += ppio_stats.rx_packets - drop_mac;
	stats->opackets += ppio_stats.tx_packets;
	stats->imissed += ppio_stats.rx_fullq_dropped +
			  ppio_stats.rx_bm_dropped +
			  ppio_stats.rx_early_dropped +
			  ppio_stats.rx_fifo_dropped +
			  ppio_stats.rx_cls_dropped;
	stats->ierrors = drop_mac;

	return 0;
}

/**
 * DPDK callback to clear device statistics.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 */
static void
mrvl_stats_reset(struct rte_eth_dev *dev)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	int i;

	if (!priv->ppio)
		return;

	for (i = 0; i < dev->data->nb_rx_queues; i++) {
		struct mrvl_rxq *rxq = dev->data->rx_queues[i];

		pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
					    priv->rxq_map[i].inq, NULL, 1);
		rxq->bytes_recv = 0;
		rxq->drop_mac = 0;
	}

	for (i = 0; i < dev->data->nb_tx_queues; i++) {
		struct mrvl_txq *txq = dev->data->tx_queues[i];

		pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
		txq->bytes_sent = 0;
	}

	pp2_ppio_get_statistics(priv->ppio, NULL, 1);
}

/**
 * DPDK callback to get extended statistics.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 * @param stats
 *   Pointer to xstats table.
 * @param n
 *   Number of entries in xstats table.
 * @return
 *   Negative value on error, number of read xstats otherwise.
 */
static int
mrvl_xstats_get(struct rte_eth_dev *dev,
		struct rte_eth_xstat *stats, unsigned int n)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	struct pp2_ppio_statistics ppio_stats;
	unsigned int i;

	if (!stats)
		return 0;

	pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
	for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) {
		uint64_t val;

		if (mrvl_xstats_tbl[i].size == sizeof(uint32_t))
			val = *(uint32_t *)((uint8_t *)&ppio_stats +
					    mrvl_xstats_tbl[i].offset);
		else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t))
			val = *(uint64_t *)((uint8_t *)&ppio_stats +
					    mrvl_xstats_tbl[i].offset);
		else
			return -EINVAL;

		stats[i].id = i;
		stats[i].value = val;
	}

	return n;
}

/**
 * DPDK callback to reset extended statistics.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 */
static void
mrvl_xstats_reset(struct rte_eth_dev *dev)
{
	mrvl_stats_reset(dev);
}

/**
 * DPDK callback to get extended statistics names.
 *
 * @param dev (unused)
 *   Pointer to Ethernet device structure.
 * @param xstats_names
 *   Pointer to xstats names table.
 * @param size
 *   Size of the xstats names table.
 * @return
 *   Number of read names.
 */
static int
mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
		      struct rte_eth_xstat_name *xstats_names,
		      unsigned int size)
{
	unsigned int i;

	if (!xstats_names)
		return RTE_DIM(mrvl_xstats_tbl);

	for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++)
		snprintf(xstats_names[i].name, RTE_ETH_XSTATS_NAME_SIZE, "%s",
			 mrvl_xstats_tbl[i].name);

	return size;
}

/**
 * DPDK callback to get information about the device.
 *
 * @param dev
 *   Pointer to Ethernet device structure (unused).
 * @param info
 *   Info structure output buffer.
 */
static void
mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
		   struct rte_eth_dev_info *info)
{
	info->speed_capa = ETH_LINK_SPEED_10M |
			   ETH_LINK_SPEED_100M |
			   ETH_LINK_SPEED_1G |
			   ETH_LINK_SPEED_10G;

	info->max_rx_queues = MRVL_PP2_RXQ_MAX;
	info->max_tx_queues = MRVL_PP2_TXQ_MAX;
	info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;

	info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
	info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
	info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;

	info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
	info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
	info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;

	info->rx_offload_capa = MRVL_RX_OFFLOADS;
	info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;

	info->tx_offload_capa = MRVL_TX_OFFLOADS;
	info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;

	info->flow_type_rss_offloads = ETH_RSS_IPV4 |
				       ETH_RSS_NONFRAG_IPV4_TCP |
				       ETH_RSS_NONFRAG_IPV4_UDP;

	/* By default packets are dropped if no descriptors are available */
	info->default_rxconf.rx_drop_en = 1;
	info->default_rxconf.offloads = DEV_RX_OFFLOAD_CRC_STRIP;

	info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
}

/**
 * Return supported packet types.
 *
 * @param dev
 *   Pointer to Ethernet device structure (unused).
 *
 * @return
 *   Const pointer to the table with supported packet types.
 */
static const uint32_t *
mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
{
	static const uint32_t ptypes[] = {
		RTE_PTYPE_L2_ETHER,
		RTE_PTYPE_L3_IPV4,
		RTE_PTYPE_L3_IPV4_EXT,
		RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
		RTE_PTYPE_L3_IPV6,
		RTE_PTYPE_L3_IPV6_EXT,
		RTE_PTYPE_L2_ETHER_ARP,
		RTE_PTYPE_L4_TCP,
		RTE_PTYPE_L4_UDP
	};

	return ptypes;
}

/**
 * DPDK callback to get information about specific receive queue.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 * @param rx_queue_id
 *   Receive queue index.
 * @param qinfo
 *   Receive queue information structure.
 */
static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
			      struct rte_eth_rxq_info *qinfo)
{
	struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
	struct mrvl_priv *priv = dev->data->dev_private;
	int inq = priv->rxq_map[rx_queue_id].inq;
	int tc = priv->rxq_map[rx_queue_id].tc;
	struct pp2_ppio_tc_params *tc_params =
		&priv->ppio_params.inqs_params.tcs_params[tc];

	qinfo->mp = q->mp;
	qinfo->nb_desc = tc_params->inqs_params[inq].size;
}

/**
 * DPDK callback to get information about specific transmit queue.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 * @param tx_queue_id
 *   Transmit queue index.
 * @param qinfo
 *   Transmit queue information structure.
 */
static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
			      struct rte_eth_txq_info *qinfo)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id];

	qinfo->nb_desc =
		priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
	qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
}

/**
 * DPDK callback to Configure a VLAN filter.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 * @param vlan_id
 *   VLAN ID to filter.
 * @param on
 *   Toggle filter.
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static int
mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
{
	struct mrvl_priv *priv = dev->data->dev_private;

	if (!priv->ppio)
		return -EPERM;

	if (priv->isolated)
		return -ENOTSUP;

	return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
		    pp2_ppio_remove_vlan(priv->ppio, vlan_id);
}

/**
 * Release buffers to hardware bpool (buffer-pool)
 *
 * @param rxq
 *   Receive queue pointer.
 * @param num
 *   Number of buffers to release to bpool.
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static int
mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
{
	struct buff_release_entry entries[MRVL_PP2_RXD_MAX];
	struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX];
	int i, ret;
	unsigned int core_id;
	struct pp2_hif *hif;
	struct pp2_bpool *bpool;

	core_id = rte_lcore_id();
	if (core_id == LCORE_ID_ANY)
		core_id = 0;

	hif = mrvl_get_hif(rxq->priv, core_id);
	if (!hif)
		return -1;

	bpool = rxq->priv->bpool;

	ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
	if (ret)
		return ret;

	if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
		cookie_addr_high =
			(uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;

	for (i = 0; i < num; i++) {
		if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
			!= cookie_addr_high) {
			RTE_LOG(ERR, PMD,
				"mbuf virtual addr high 0x%lx out of range\n",
				(uint64_t)mbufs[i] >> 32);
			goto out;
		}

		entries[i].buff.addr =
			rte_mbuf_data_iova_default(mbufs[i]);
		entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
		entries[i].bpool = bpool;
	}

	pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
	mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;

	if (i != num)
		goto out;

	return 0;
out:
	for (; i < num; i++)
		rte_pktmbuf_free(mbufs[i]);

	return -1;
}

/**
 * DPDK callback to configure the receive queue.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 * @param idx
 *   RX queue index.
 * @param desc
 *   Number of descriptors to configure in queue.
 * @param socket
 *   NUMA socket on which memory must be allocated.
 * @param conf
 *   Thresholds parameters.
 * @param mp
 *   Memory pool for buffer allocations.
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static int
mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
		    unsigned int socket,
		    const struct rte_eth_rxconf *conf,
		    struct rte_mempool *mp)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	struct mrvl_rxq *rxq;
	uint32_t min_size,
		 max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
	int ret, tc, inq;
	uint64_t offloads;

	offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;

	if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
		/*
		 * Unknown TC mapping, mapping will not have a correct queue.
		 */
		RTE_LOG(ERR, PMD, "Unknown TC mapping for queue %hu eth%hhu\n",
			idx, priv->ppio_id);
		return -EFAULT;
	}

	min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
		   MRVL_PKT_EFFEC_OFFS;
	if (min_size < max_rx_pkt_len) {
		RTE_LOG(ERR, PMD,
			"Mbuf size must be increased to %u bytes to hold up to %u bytes of data.\n",
			max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
			MRVL_PKT_EFFEC_OFFS,
			max_rx_pkt_len);
		return -EINVAL;
	}

	if (dev->data->rx_queues[idx]) {
		rte_free(dev->data->rx_queues[idx]);
		dev->data->rx_queues[idx] = NULL;
	}

	rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
	if (!rxq)
		return -ENOMEM;

	rxq->priv = priv;
	rxq->mp = mp;
	rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
	rxq->queue_id = idx;
	rxq->port_id = dev->data->port_id;
	mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;

	tc = priv->rxq_map[rxq->queue_id].tc,
	inq = priv->rxq_map[rxq->queue_id].inq;
	priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
		desc;

	ret = mrvl_fill_bpool(rxq, desc);
	if (ret) {
		rte_free(rxq);
		return ret;
	}

	priv->bpool_init_size += desc;

	dev->data->rx_queues[idx] = rxq;

	return 0;
}

/**
 * DPDK callback to release the receive queue.
 *
 * @param rxq
 *   Generic receive queue pointer.
 */
static void
mrvl_rx_queue_release(void *rxq)
{
	struct mrvl_rxq *q = rxq;
	struct pp2_ppio_tc_params *tc_params;
	int i, num, tc, inq;
	struct pp2_hif *hif;
	unsigned int core_id = rte_lcore_id();

	if (core_id == LCORE_ID_ANY)
		core_id = 0;

	hif = mrvl_get_hif(q->priv, core_id);

	if (!q || !hif)
		return;

	tc = q->priv->rxq_map[q->queue_id].tc;
	inq = q->priv->rxq_map[q->queue_id].inq;
	tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
	num = tc_params->inqs_params[inq].size;
	for (i = 0; i < num; i++) {
		struct pp2_buff_inf inf;
		uint64_t addr;

		pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
		addr = cookie_addr_high | inf.cookie;
		rte_pktmbuf_free((struct rte_mbuf *)addr);
	}

	rte_free(q);
}

/**
 * DPDK callback to configure the transmit queue.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 * @param idx
 *   Transmit queue index.
 * @param desc
 *   Number of descriptors to configure in the queue.
 * @param socket
 *   NUMA socket on which memory must be allocated.
 * @param conf
 *   Tx queue configuration parameters.
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static int
mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
		    unsigned int socket,
		    const struct rte_eth_txconf *conf)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	struct mrvl_txq *txq;

	if (dev->data->tx_queues[idx]) {
		rte_free(dev->data->tx_queues[idx]);
		dev->data->tx_queues[idx] = NULL;
	}

	txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
	if (!txq)
		return -ENOMEM;

	txq->priv = priv;
	txq->queue_id = idx;
	txq->port_id = dev->data->port_id;
	txq->tx_deferred_start = conf->tx_deferred_start;
	dev->data->tx_queues[idx] = txq;

	priv->ppio_params.outqs_params.outqs_params[idx].size = desc;

	return 0;
}

/**
 * DPDK callback to release the transmit queue.
 *
 * @param txq
 *   Generic transmit queue pointer.
 */
static void
mrvl_tx_queue_release(void *txq)
{
	struct mrvl_txq *q = txq;

	if (!q)
		return;

	rte_free(q);
}

/**
 * DPDK callback to get flow control configuration.
 *
 * @param dev
 *  Pointer to Ethernet device structure.
 * @param fc_conf
 *  Pointer to the flow control configuration.
 *
 * @return
 *  0 on success, negative error value otherwise.
 */
static int
mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	int ret, en;

	if (!priv)
		return -EPERM;

	ret = pp2_ppio_get_rx_pause(priv->ppio, &en);
	if (ret) {
		RTE_LOG(ERR, PMD, "Failed to read rx pause state\n");
		return ret;
	}

	fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE;

	return 0;
}

/**
 * DPDK callback to set flow control configuration.
 *
 * @param dev
 *  Pointer to Ethernet device structure.
 * @param fc_conf
 *  Pointer to the flow control configuration.
 *
 * @return
 *  0 on success, negative error value otherwise.
 */
static int
mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
{
	struct mrvl_priv *priv = dev->data->dev_private;

	if (!priv)
		return -EPERM;

	if (fc_conf->high_water ||
	    fc_conf->low_water ||
	    fc_conf->pause_time ||
	    fc_conf->mac_ctrl_frame_fwd ||
	    fc_conf->autoneg) {
		RTE_LOG(ERR, PMD, "Flowctrl parameter is not supported\n");

		return -EINVAL;
	}

	if (fc_conf->mode == RTE_FC_NONE ||
	    fc_conf->mode == RTE_FC_RX_PAUSE) {
		int ret, en;

		en = fc_conf->mode == RTE_FC_NONE ? 0 : 1;
		ret = pp2_ppio_set_rx_pause(priv->ppio, en);
		if (ret)
			RTE_LOG(ERR, PMD,
				"Failed to change flowctrl on RX side\n");

		return ret;
	}

	return 0;
}

/**
 * Update RSS hash configuration
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 * @param rss_conf
 *   Pointer to RSS configuration.
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static int
mrvl_rss_hash_update(struct rte_eth_dev *dev,
		     struct rte_eth_rss_conf *rss_conf)
{
	struct mrvl_priv *priv = dev->data->dev_private;

	if (priv->isolated)
		return -ENOTSUP;

	return mrvl_configure_rss(priv, rss_conf);
}

/**
 * DPDK callback to get RSS hash configuration.
 *
 * @param dev
 *   Pointer to Ethernet device structure.
 * @rss_conf
 *   Pointer to RSS configuration.
 *
 * @return
 *   Always 0.
 */
static int
mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
		       struct rte_eth_rss_conf *rss_conf)
{
	struct mrvl_priv *priv = dev->data->dev_private;
	enum pp2_ppio_hash_type hash_type =
		priv->ppio_params.inqs_params.hash_type;

	rss_conf->rss_key = NULL;

	if (hash_type == PP2_PPIO_HASH_T_NONE)
		rss_conf->rss_hf = 0;
	else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
		rss_conf->rss_hf = ETH_RSS_IPV4;
	else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
		rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
	else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
		rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;

	return 0;
}

/**
 * DPDK callback to get rte_flow callbacks.
 *
 * @param dev
 *   Pointer to the device structure.
 * @param filer_type
 *   Flow filter type.
 * @param filter_op
 *   Flow filter operation.
 * @param arg
 *   Pointer to pass the flow ops.
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static int
mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused,
		     enum rte_filter_type filter_type,
		     enum rte_filter_op filter_op, void *arg)
{
	switch (filter_type) {
	case RTE_ETH_FILTER_GENERIC:
		if (filter_op != RTE_ETH_FILTER_GET)
			return -EINVAL;
		*(const void **)arg = &mrvl_flow_ops;
		return 0;
	default:
		RTE_LOG(WARNING, PMD, "Filter type (%d) not supported",
				filter_type);
		return -EINVAL;
	}
}

static const struct eth_dev_ops mrvl_ops = {
	.dev_configure = mrvl_dev_configure,
	.dev_start = mrvl_dev_start,
	.dev_stop = mrvl_dev_stop,
	.dev_set_link_up = mrvl_dev_set_link_up,
	.dev_set_link_down = mrvl_dev_set_link_down,
	.dev_close = mrvl_dev_close,
	.link_update = mrvl_link_update,
	.promiscuous_enable = mrvl_promiscuous_enable,
	.allmulticast_enable = mrvl_allmulticast_enable,
	.promiscuous_disable = mrvl_promiscuous_disable,
	.allmulticast_disable = mrvl_allmulticast_disable,
	.mac_addr_remove = mrvl_mac_addr_remove,
	.mac_addr_add = mrvl_mac_addr_add,
	.mac_addr_set = mrvl_mac_addr_set,
	.mtu_set = mrvl_mtu_set,
	.stats_get = mrvl_stats_get,
	.stats_reset = mrvl_stats_reset,
	.xstats_get = mrvl_xstats_get,
	.xstats_reset = mrvl_xstats_reset,
	.xstats_get_names = mrvl_xstats_get_names,
	.dev_infos_get = mrvl_dev_infos_get,
	.dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
	.rxq_info_get = mrvl_rxq_info_get,
	.txq_info_get = mrvl_txq_info_get,
	.vlan_filter_set = mrvl_vlan_filter_set,
	.tx_queue_start = mrvl_tx_queue_start,
	.tx_queue_stop = mrvl_tx_queue_stop,
	.rx_queue_setup = mrvl_rx_queue_setup,
	.rx_queue_release = mrvl_rx_queue_release,
	.tx_queue_setup = mrvl_tx_queue_setup,
	.tx_queue_release = mrvl_tx_queue_release,
	.flow_ctrl_get = mrvl_flow_ctrl_get,
	.flow_ctrl_set = mrvl_flow_ctrl_set,
	.rss_hash_update = mrvl_rss_hash_update,
	.rss_hash_conf_get = mrvl_rss_hash_conf_get,
	.filter_ctrl = mrvl_eth_filter_ctrl,
};

/**
 * Return packet type information and l3/l4 offsets.
 *
 * @param desc
 *   Pointer to the received packet descriptor.
 * @param l3_offset
 *   l3 packet offset.
 * @param l4_offset
 *   l4 packet offset.
 *
 * @return
 *   Packet type information.
 */
static inline uint64_t
mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
				    uint8_t *l3_offset, uint8_t *l4_offset)
{
	enum pp2_inq_l3_type l3_type;
	enum pp2_inq_l4_type l4_type;
	uint64_t packet_type;

	pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
	pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);

	packet_type = RTE_PTYPE_L2_ETHER;

	switch (l3_type) {
	case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
		packet_type |= RTE_PTYPE_L3_IPV4;
		break;
	case PP2_INQ_L3_TYPE_IPV4_OK:
		packet_type |= RTE_PTYPE_L3_IPV4_EXT;
		break;
	case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
		packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
		break;
	case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
		packet_type |= RTE_PTYPE_L3_IPV6;
		break;
	case PP2_INQ_L3_TYPE_IPV6_EXT:
		packet_type |= RTE_PTYPE_L3_IPV6_EXT;
		break;
	case PP2_INQ_L3_TYPE_ARP:
		packet_type |= RTE_PTYPE_L2_ETHER_ARP;
		/*
		 * In case of ARP l4_offset is set to wrong value.
		 * Set it to proper one so that later on mbuf->l3_len can be
		 * calculated subtracting l4_offset and l3_offset.
		 */
		*l4_offset = *l3_offset + MRVL_ARP_LENGTH;
		break;
	default:
		RTE_LOG(DEBUG, PMD, "Failed to recognise l3 packet type\n");
		break;
	}

	switch (l4_type) {
	case PP2_INQ_L4_TYPE_TCP:
		packet_type |= RTE_PTYPE_L4_TCP;
		break;
	case PP2_INQ_L4_TYPE_UDP:
		packet_type |= RTE_PTYPE_L4_UDP;
		break;
	default:
		RTE_LOG(DEBUG, PMD, "Failed to recognise l4 packet type\n");
		break;
	}

	return packet_type;
}

/**
 * Get offload information from the received packet descriptor.
 *
 * @param desc
 *   Pointer to the received packet descriptor.
 *
 * @return
 *   Mbuf offload flags.
 */
static inline uint64_t
mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
{
	uint64_t flags;
	enum pp2_inq_desc_status status;

	status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
	if (unlikely(status != PP2_DESC_ERR_OK))
		flags = PKT_RX_IP_CKSUM_BAD;
	else
		flags = PKT_RX_IP_CKSUM_GOOD;

	status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
	if (unlikely(status != PP2_DESC_ERR_OK))
		flags |= PKT_RX_L4_CKSUM_BAD;
	else
		flags |= PKT_RX_L4_CKSUM_GOOD;

	return flags;
}

/**
 * DPDK callback for receive.
 *
 * @param rxq
 *   Generic pointer to the receive queue.
 * @param rx_pkts
 *   Array to store received packets.
 * @param nb_pkts
 *   Maximum number of packets in array.
 *
 * @return
 *   Number of packets successfully received.
 */
static uint16_t
mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
{
	struct mrvl_rxq *q = rxq;
	struct pp2_ppio_desc descs[nb_pkts];
	struct pp2_bpool *bpool;
	int i, ret, rx_done = 0;
	int num;
	struct pp2_hif *hif;
	unsigned int core_id = rte_lcore_id();

	hif = mrvl_get_hif(q->priv, core_id);

	if (unlikely(!q->priv->ppio || !hif))
		return 0;

	bpool = q->priv->bpool;

	ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
			    q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
	if (unlikely(ret < 0)) {
		RTE_LOG(ERR, PMD, "Failed to receive packets\n");
		return 0;
	}
	mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;

	for (i = 0; i < nb_pkts; i++) {
		struct rte_mbuf *mbuf;
		uint8_t l3_offset, l4_offset;
		enum pp2_inq_desc_status status;
		uint64_t addr;

		if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
			struct pp2_ppio_desc *pref_desc;
			u64 pref_addr;

			pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
			pref_addr = cookie_addr_high |
				    pp2_ppio_inq_desc_get_cookie(pref_desc);
			rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
			rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
		}

		addr = cookie_addr_high |
		       pp2_ppio_inq_desc_get_cookie(&descs[i]);
		mbuf = (struct rte_mbuf *)addr;
		rte_pktmbuf_reset(mbuf);

		/* drop packet in case of mac, overrun or resource error */
		status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
		if (unlikely(status != PP2_DESC_ERR_OK)) {
			struct pp2_buff_inf binf = {
				.addr = rte_mbuf_data_iova_default(mbuf),
				.cookie = (pp2_cookie_t)(uint64_t)mbuf,
			};

			pp2_bpool_put_buff(hif, bpool, &binf);
			mrvl_port_bpool_size
				[bpool->pp2_id][bpool->id][core_id]++;
			q->drop_mac++;
			continue;
		}

		mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
		mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
		mbuf->data_len = mbuf->pkt_len;
		mbuf->port = q->port_id;
		mbuf->packet_type =
			mrvl_desc_to_packet_type_and_offset(&descs[i],
							    &l3_offset,
							    &l4_offset);
		mbuf->l2_len = l3_offset;
		mbuf->l3_len = l4_offset - l3_offset;

		if (likely(q->cksum_enabled))
			mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);

		rx_pkts[rx_done++] = mbuf;
		q->bytes_recv += mbuf->pkt_len;
	}

	if (rte_spinlock_trylock(&q->priv->lock) == 1) {
		num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);

		if (unlikely(num <= q->priv->bpool_min_size ||
			     (!rx_done && num < q->priv->bpool_init_size))) {
			ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
			if (ret)
				RTE_LOG(ERR, PMD, "Failed to fill bpool\n");
		} else if (unlikely(num > q->priv->bpool_max_size)) {
			int i;
			int pkt_to_remove = num - q->priv->bpool_init_size;
			struct rte_mbuf *mbuf;
			struct pp2_buff_inf buff;

			RTE_LOG(DEBUG, PMD,
				"\nport-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)\n",
				bpool->pp2_id, q->priv->ppio->port_id,
				bpool->id, pkt_to_remove, num,
				q->priv->bpool_init_size);

			for (i = 0; i < pkt_to_remove; i++) {
				ret = pp2_bpool_get_buff(hif, bpool, &buff);
				if (ret)
					break;
				mbuf = (struct rte_mbuf *)
					(cookie_addr_high | buff.cookie);
				rte_pktmbuf_free(mbuf);
			}
			mrvl_port_bpool_size
				[bpool->pp2_id][bpool->id][core_id] -= i;
		}
		rte_spinlock_unlock(&q->priv->lock);
	}

	return rx_done;
}

/**
 * Prepare offload information.
 *
 * @param ol_flags
 *   Offload flags.
 * @param packet_type
 *   Packet type bitfield.
 * @param l3_type
 *   Pointer to the pp2_ouq_l3_type structure.
 * @param l4_type
 *   Pointer to the pp2_outq_l4_type structure.
 * @param gen_l3_cksum
 *   Will be set to 1 in case l3 checksum is computed.
 * @param l4_cksum
 *   Will be set to 1 in case l4 checksum is computed.
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static inline int
mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
			enum pp2_outq_l3_type *l3_type,
			enum pp2_outq_l4_type *l4_type,
			int *gen_l3_cksum,
			int *gen_l4_cksum)
{
	/*
	 * Based on ol_flags prepare information
	 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
	 * for offloading.
	 */
	if (ol_flags & PKT_TX_IPV4) {
		*l3_type = PP2_OUTQ_L3_TYPE_IPV4;
		*gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
	} else if (ol_flags & PKT_TX_IPV6) {
		*l3_type = PP2_OUTQ_L3_TYPE_IPV6;
		/* no checksum for ipv6 header */
		*gen_l3_cksum = 0;
	} else {
		/* if something different then stop processing */
		return -1;
	}

	ol_flags &= PKT_TX_L4_MASK;
	if ((packet_type & RTE_PTYPE_L4_TCP) &&
	    ol_flags == PKT_TX_TCP_CKSUM) {
		*l4_type = PP2_OUTQ_L4_TYPE_TCP;
		*gen_l4_cksum = 1;
	} else if ((packet_type & RTE_PTYPE_L4_UDP) &&
		   ol_flags == PKT_TX_UDP_CKSUM) {
		*l4_type = PP2_OUTQ_L4_TYPE_UDP;
		*gen_l4_cksum = 1;
	} else {
		*l4_type = PP2_OUTQ_L4_TYPE_OTHER;
		/* no checksum for other type */
		*gen_l4_cksum = 0;
	}

	return 0;
}

/**
 * Release already sent buffers to bpool (buffer-pool).
 *
 * @param ppio
 *   Pointer to the port structure.
 * @param hif
 *   Pointer to the MUSDK hardware interface.
 * @param sq
 *   Pointer to the shadow queue.
 * @param qid
 *   Queue id number.
 * @param force
 *   Force releasing packets.
 */
static inline void
mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
		       unsigned int core_id, struct mrvl_shadow_txq *sq,
		       int qid, int force)
{
	struct buff_release_entry *entry;
	uint16_t nb_done = 0, num = 0, skip_bufs = 0;
	int i;

	pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);

	sq->num_to_release += nb_done;

	if (likely(!force &&
		   sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
		return;

	nb_done = sq->num_to_release;
	sq->num_to_release = 0;

	for (i = 0; i < nb_done; i++) {
		entry = &sq->ent[sq->tail + num];
		if (unlikely(!entry->buff.addr)) {
			RTE_LOG(ERR, PMD,
				"Shadow memory @%d: cookie(%lx), pa(%lx)!\n",
				sq->tail, (u64)entry->buff.cookie,
				(u64)entry->buff.addr);
			skip_bufs = 1;
			goto skip;
		}

		if (unlikely(!entry->bpool)) {
			struct rte_mbuf *mbuf;

			mbuf = (struct rte_mbuf *)
			       (cookie_addr_high | entry->buff.cookie);
			rte_pktmbuf_free(mbuf);
			skip_bufs = 1;
			goto skip;
		}

		mrvl_port_bpool_size
			[entry->bpool->pp2_id][entry->bpool->id][core_id]++;
		num++;
		if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
			goto skip;
		continue;
skip:
		if (likely(num))
			pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
		num += skip_bufs;
		sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
		sq->size -= num;
		num = 0;
		skip_bufs = 0;
	}

	if (likely(num)) {
		pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
		sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
		sq->size -= num;
	}
}

/**
 * DPDK callback for transmit.
 *
 * @param txq
 *   Generic pointer transmit queue.
 * @param tx_pkts
 *   Packets to transmit.
 * @param nb_pkts
 *   Number of packets in array.
 *
 * @return
 *   Number of packets successfully transmitted.
 */
static uint16_t
mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
{
	struct mrvl_txq *q = txq;
	struct mrvl_shadow_txq *sq;
	struct pp2_hif *hif;
	struct pp2_ppio_desc descs[nb_pkts];
	unsigned int core_id = rte_lcore_id();
	int i, ret, bytes_sent = 0;
	uint16_t num, sq_free_size;
	uint64_t addr;

	hif = mrvl_get_hif(q->priv, core_id);
	sq = &q->shadow_txqs[core_id];

	if (unlikely(!q->priv->ppio || !hif))
		return 0;

	if (sq->size)
		mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
				       sq, q->queue_id, 0);

	sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
	if (unlikely(nb_pkts > sq_free_size)) {
		RTE_LOG(DEBUG, PMD,
			"No room in shadow queue for %d packets! %d packets will be sent.\n",
			nb_pkts, sq_free_size);
		nb_pkts = sq_free_size;
	}

	for (i = 0; i < nb_pkts; i++) {
		struct rte_mbuf *mbuf = tx_pkts[i];
		int gen_l3_cksum, gen_l4_cksum;
		enum pp2_outq_l3_type l3_type;
		enum pp2_outq_l4_type l4_type;

		if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
			struct rte_mbuf *pref_pkt_hdr;

			pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
			rte_mbuf_prefetch_part1(pref_pkt_hdr);
			rte_mbuf_prefetch_part2(pref_pkt_hdr);
		}

		sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
		sq->ent[sq->head].buff.addr =
			rte_mbuf_data_iova_default(mbuf);
		sq->ent[sq->head].bpool =
			(unlikely(mbuf->port >= RTE_MAX_ETHPORTS ||
			 mbuf->refcnt > 1)) ? NULL :
			 mrvl_port_to_bpool_lookup[mbuf->port];
		sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
		sq->size++;

		pp2_ppio_outq_desc_reset(&descs[i]);
		pp2_ppio_outq_desc_set_phys_addr(&descs[i],
						 rte_pktmbuf_iova(mbuf));
		pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
		pp2_ppio_outq_desc_set_pkt_len(&descs[i],
					       rte_pktmbuf_pkt_len(mbuf));

		bytes_sent += rte_pktmbuf_pkt_len(mbuf);
		/*
		 * in case unsupported ol_flags were passed
		 * do not update descriptor offload information
		 */
		ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
					      &l3_type, &l4_type, &gen_l3_cksum,
					      &gen_l4_cksum);
		if (unlikely(ret))
			continue;

		pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
						  mbuf->l2_len,
						  mbuf->l2_len + mbuf->l3_len,
						  gen_l3_cksum, gen_l4_cksum);
	}

	num = nb_pkts;
	pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
	/* number of packets that were not sent */
	if (unlikely(num > nb_pkts)) {
		for (i = nb_pkts; i < num; i++) {
			sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
				MRVL_PP2_TX_SHADOWQ_MASK;
			addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
			bytes_sent -=
				rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
		}
		sq->size -= num - nb_pkts;
	}

	q->bytes_sent += bytes_sent;

	return nb_pkts;
}

/**
 * Initialize packet processor.
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static int
mrvl_init_pp2(void)
{
	struct pp2_init_params init_params;

	memset(&init_params, 0, sizeof(init_params));
	init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
	init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
	init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;

	return pp2_init(&init_params);
}

/**
 * Deinitialize packet processor.
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static void
mrvl_deinit_pp2(void)
{
	pp2_deinit();
}

/**
 * Create private device structure.
 *
 * @param dev_name
 *   Pointer to the port name passed in the initialization parameters.
 *
 * @return
 *   Pointer to the newly allocated private device structure.
 */
static struct mrvl_priv *
mrvl_priv_create(const char *dev_name)
{
	struct pp2_bpool_params bpool_params;
	char match[MRVL_MATCH_LEN];
	struct mrvl_priv *priv;
	int ret, bpool_bit;

	priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
	if (!priv)
		return NULL;

	ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
				       &priv->pp_id, &priv->ppio_id);
	if (ret)
		goto out_free_priv;

	bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
				     PP2_BPOOL_NUM_POOLS);
	if (bpool_bit < 0)
		goto out_free_priv;
	priv->bpool_bit = bpool_bit;

	snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
		 priv->bpool_bit);
	memset(&bpool_params, 0, sizeof(bpool_params));
	bpool_params.match = match;
	bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
	ret = pp2_bpool_init(&bpool_params, &priv->bpool);
	if (ret)
		goto out_clear_bpool_bit;

	priv->ppio_params.type = PP2_PPIO_T_NIC;
	rte_spinlock_init(&priv->lock);

	return priv;
out_clear_bpool_bit:
	used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
out_free_priv:
	rte_free(priv);
	return NULL;
}

/**
 * Create device representing Ethernet port.
 *
 * @param name
 *   Pointer to the port's name.
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static int
mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
{
	int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
	struct rte_eth_dev *eth_dev;
	struct mrvl_priv *priv;
	struct ifreq req;

	eth_dev = rte_eth_dev_allocate(name);
	if (!eth_dev)
		return -ENOMEM;

	priv = mrvl_priv_create(name);
	if (!priv) {
		ret = -ENOMEM;
		goto out_free_dev;
	}

	eth_dev->data->mac_addrs =
		rte_zmalloc("mac_addrs",
			    ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
	if (!eth_dev->data->mac_addrs) {
		RTE_LOG(ERR, PMD, "Failed to allocate space for eth addrs\n");
		ret = -ENOMEM;
		goto out_free_priv;
	}

	memset(&req, 0, sizeof(req));
	strcpy(req.ifr_name, name);
	ret = ioctl(fd, SIOCGIFHWADDR, &req);
	if (ret)
		goto out_free_mac;

	memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
	       req.ifr_addr.sa_data, ETHER_ADDR_LEN);

	eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
	eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
	eth_dev->data->kdrv = RTE_KDRV_NONE;
	eth_dev->data->dev_private = priv;
	eth_dev->device = &vdev->device;
	eth_dev->dev_ops = &mrvl_ops;

	return 0;
out_free_mac:
	rte_free(eth_dev->data->mac_addrs);
out_free_dev:
	rte_eth_dev_release_port(eth_dev);
out_free_priv:
	rte_free(priv);

	return ret;
}

/**
 * Cleanup previously created device representing Ethernet port.
 *
 * @param name
 *   Pointer to the port name.
 */
static void
mrvl_eth_dev_destroy(const char *name)
{
	struct rte_eth_dev *eth_dev;
	struct mrvl_priv *priv;

	eth_dev = rte_eth_dev_allocated(name);
	if (!eth_dev)
		return;

	priv = eth_dev->data->dev_private;
	pp2_bpool_deinit(priv->bpool);
	used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
	rte_free(priv);
	rte_free(eth_dev->data->mac_addrs);
	rte_eth_dev_release_port(eth_dev);
}

/**
 * Callback used by rte_kvargs_process() during argument parsing.
 *
 * @param key
 *   Pointer to the parsed key (unused).
 * @param value
 *   Pointer to the parsed value.
 * @param extra_args
 *   Pointer to the extra arguments which contains address of the
 *   table of pointers to parsed interface names.
 *
 * @return
 *   Always 0.
 */
static int
mrvl_get_ifnames(const char *key __rte_unused, const char *value,
		 void *extra_args)
{
	struct mrvl_ifnames *ifnames = extra_args;

	ifnames->names[ifnames->idx++] = value;

	return 0;
}

/**
 * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
 */
static void
mrvl_deinit_hifs(void)
{
	int i;

	for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
		if (hifs[i])
			pp2_hif_deinit(hifs[i]);
	}
	used_hifs = MRVL_MUSDK_HIFS_RESERVED;
	memset(hifs, 0, sizeof(hifs));
}

/**
 * DPDK callback to register the virtual device.
 *
 * @param vdev
 *   Pointer to the virtual device.
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static int
rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
{
	struct rte_kvargs *kvlist;
	struct mrvl_ifnames ifnames;
	int ret = -EINVAL;
	uint32_t i, ifnum, cfgnum;
	const char *params;

	params = rte_vdev_device_args(vdev);
	if (!params)
		return -EINVAL;

	kvlist = rte_kvargs_parse(params, valid_args);
	if (!kvlist)
		return -EINVAL;

	ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
	if (ifnum > RTE_DIM(ifnames.names))
		goto out_free_kvlist;

	ifnames.idx = 0;
	rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
			   mrvl_get_ifnames, &ifnames);


	/*
	 * The below system initialization should be done only once,
	 * on the first provided configuration file
	 */
	if (!mrvl_qos_cfg) {
		cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
		RTE_LOG(INFO, PMD, "Parsing config file!\n");
		if (cfgnum > 1) {
			RTE_LOG(ERR, PMD, "Cannot handle more than one config file!\n");
			goto out_free_kvlist;
		} else if (cfgnum == 1) {
			rte_kvargs_process(kvlist, MRVL_CFG_ARG,
					   mrvl_get_qoscfg, &mrvl_qos_cfg);
		}
	}

	if (mrvl_dev_num)
		goto init_devices;

	RTE_LOG(INFO, PMD, "Perform MUSDK initializations\n");
	/*
	 * ret == -EEXIST is correct, it means DMA
	 * has been already initialized (by another PMD).
	 */
	ret = mv_sys_dma_mem_init(MRVL_MUSDK_DMA_MEMSIZE);
	if (ret < 0) {
		if (ret != -EEXIST)
			goto out_free_kvlist;
		else
			RTE_LOG(INFO, PMD,
				"DMA memory has been already initialized by a different driver.\n");
	}

	ret = mrvl_init_pp2();
	if (ret) {
		RTE_LOG(ERR, PMD, "Failed to init PP!\n");
		goto out_deinit_dma;
	}

	memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
	memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));

	mrvl_lcore_first = RTE_MAX_LCORE;
	mrvl_lcore_last = 0;

init_devices:
	for (i = 0; i < ifnum; i++) {
		RTE_LOG(INFO, PMD, "Creating %s\n", ifnames.names[i]);
		ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
		if (ret)
			goto out_cleanup;
	}
	mrvl_dev_num += ifnum;

	rte_kvargs_free(kvlist);

	return 0;
out_cleanup:
	for (; i > 0; i--)
		mrvl_eth_dev_destroy(ifnames.names[i]);

	if (mrvl_dev_num == 0)
		mrvl_deinit_pp2();
out_deinit_dma:
	if (mrvl_dev_num == 0)
		mv_sys_dma_mem_destroy();
out_free_kvlist:
	rte_kvargs_free(kvlist);

	return ret;
}

/**
 * DPDK callback to remove virtual device.
 *
 * @param vdev
 *   Pointer to the removed virtual device.
 *
 * @return
 *   0 on success, negative error value otherwise.
 */
static int
rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
{
	int i;
	const char *name;

	name = rte_vdev_device_name(vdev);
	if (!name)
		return -EINVAL;

	RTE_LOG(INFO, PMD, "Removing %s\n", name);

	RTE_ETH_FOREACH_DEV(i) { /* FIXME: removing all devices! */
		char ifname[RTE_ETH_NAME_MAX_LEN];

		rte_eth_dev_get_name_by_port(i, ifname);
		mrvl_eth_dev_destroy(ifname);
		mrvl_dev_num--;
	}

	if (mrvl_dev_num == 0) {
		RTE_LOG(INFO, PMD, "Perform MUSDK deinit\n");
		mrvl_deinit_hifs();
		mrvl_deinit_pp2();
		mv_sys_dma_mem_destroy();
	}

	return 0;
}

static struct rte_vdev_driver pmd_mrvl_drv = {
	.probe = rte_pmd_mrvl_probe,
	.remove = rte_pmd_mrvl_remove,
};

RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv);
RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2);