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authorIntel <intel.com>2012-12-20 00:00:00 +0100
committerThomas Monjalon <thomas.monjalon@6wind.com>2013-07-25 15:23:26 +0200
commitaf89e7f85b4a3d5f38a319460ed028ac65bcd3c9 (patch)
tree469fd924be61d9d7434222ca8c7a535944857ae7 /tools
parenta9fb536570e0cb93692606a76328d627fd84fc74 (diff)
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dpdk-af89e7f85b4a3d5f38a319460ed028ac65bcd3c9.tar.gz
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eal: rework cpu information discovery
Signed-off-by: Intel
Diffstat (limited to 'tools')
-rwxr-xr-xtools/cpu_layout.py90
1 files changed, 90 insertions, 0 deletions
diff --git a/tools/cpu_layout.py b/tools/cpu_layout.py
new file mode 100755
index 0000000..ea19214
--- /dev/null
+++ b/tools/cpu_layout.py
@@ -0,0 +1,90 @@
+#! /usr/bin/python
+#
+# BSD LICENSE
+#
+# Copyright(c) 2010-2012 Intel Corporation. All rights reserved.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# * Neither the name of Intel Corporation nor the names of its
+# contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#
+
+import sys
+
+sockets = []
+cores = []
+core_map = {}
+
+fd=open("/proc/cpuinfo")
+lines = fd.readlines()
+fd.close()
+
+core_details = []
+core_lines = {}
+for line in lines:
+ if len(line.strip()) != 0:
+ name, value = line.split(":", 1)
+ core_lines[name.strip()] = value.strip()
+ else:
+ core_details.append(core_lines)
+ core_lines = {}
+
+for core in core_details:
+ for field in ["processor", "core id", "physical id"]:
+ if field not in core:
+ print "Error getting '%s' value from /proc/cpuinfo" % field
+ sys.exit(1)
+ core[field] = int(core[field])
+
+ if core["core id"] not in cores:
+ cores.append(core["core id"])
+ if core["physical id"] not in sockets:
+ sockets.append(core["physical id"])
+ key = (core["physical id"], core["core id"])
+ if key not in core_map:
+ core_map[key] = []
+ core_map[key].append(core["processor"])
+
+print "============================================================"
+print "Core and Socket Information (as reported by '/proc/cpuinfo')"
+print "============================================================\n"
+print "cores = ",cores
+print "sockets = ", sockets
+print ""
+
+for s in sockets:
+ print "\tSocket %s" % s,
+print ""
+for s in sockets:
+ print "\t---------",
+print ""
+
+for c in cores:
+ print "Core %s" % c,
+ for s in sockets:
+ print "\t", core_map[(s,c)],
+ print "\n"