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authorChao Zhu <chaozhu@linux.vnet.ibm.com>2016-07-15 10:30:19 +0800
committerThomas Monjalon <thomas.monjalon@6wind.com>2016-07-21 16:25:31 +0200
commitd23a6bd04d728226c99d6995c8bd65d49d7e61d1 (patch)
tree7d516b97a3868ec73cd53e7797786a3e798bc7f8 /lib
parent658cf5bc54fa44b13714d0fc6840985db2d7f331 (diff)
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eal/ppc: fix memory barrier for IBM POWER
On weak memory order architecture like POWER, rte_smp_wmb/rte_smp_rmb need to use CPU instructions, not compiler barrier. This patch fixes this. Also, to improve performance on PPC64, use light weight sync instruction instead of sync instruction. Signed-off-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>
Diffstat (limited to 'lib')
-rw-r--r--lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h12
1 files changed, 10 insertions, 2 deletions
diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
index feae486..924e894 100644
--- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
@@ -62,7 +62,11 @@ extern "C" {
* Guarantees that the STORE operations generated before the barrier
* occur before the STORE operations generated after.
*/
+#ifdef RTE_ARCH_64
+#define rte_wmb() {asm volatile("lwsync" : : : "memory"); }
+#else
#define rte_wmb() {asm volatile("sync" : : : "memory"); }
+#endif
/**
* Read memory barrier.
@@ -70,13 +74,17 @@ extern "C" {
* Guarantees that the LOAD operations generated before the barrier
* occur before the LOAD operations generated after.
*/
+#ifdef RTE_ARCH_64
+#define rte_rmb() {asm volatile("lwsync" : : : "memory"); }
+#else
#define rte_rmb() {asm volatile("sync" : : : "memory"); }
+#endif
#define rte_smp_mb() rte_mb()
-#define rte_smp_wmb() rte_compiler_barrier()
+#define rte_smp_wmb() rte_wmb()
-#define rte_smp_rmb() rte_compiler_barrier()
+#define rte_smp_rmb() rte_rmb()
/*------------------------- 16 bit atomic operations -------------------------*/
/* To be compatible with Power7, use GCC built-in functions for 16 bit