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authorThomas Monjalon <thomas.monjalon@6wind.com>2016-03-30 15:59:05 +0200
committerThomas Monjalon <thomas.monjalon@6wind.com>2016-03-31 22:56:00 +0200
commite27529c61cb7c004c458dfdeaea1b19f5c40e6fc (patch)
tree01293bf3e359d8d22b39f76f5ede744e7b375883 /examples
parent8353a36a9b4b0766d4f3433fa6ad8fd41cb60bbc (diff)
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examples/ip_pipeline: fix SSE4.2 optimization branch
The branch was disabled because of a typo in the SSE4.2 flag. Change also the x86_64 flag to use a DPDK one. Fixes: 28377375c6c0 ("examples/ip_pipeline: fix build for x86_64 without SSE4.2") Signed-off-by: Thomas Monjalon <thomas.monjalon@6wind.com> Acked-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
Diffstat (limited to 'examples')
-rw-r--r--examples/ip_pipeline/pipeline/hash_func.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/examples/ip_pipeline/pipeline/hash_func.h b/examples/ip_pipeline/pipeline/hash_func.h
index 1953ad4..9db7173 100644
--- a/examples/ip_pipeline/pipeline/hash_func.h
+++ b/examples/ip_pipeline/pipeline/hash_func.h
@@ -152,7 +152,7 @@ hash_xor_key64(void *key, __rte_unused uint32_t key_size, uint64_t seed)
return (xor0 >> 32) ^ xor0;
}
-#if defined(__x86_64__) && defined(RTE_CPUFLAG_SSE4_2)
+#if defined(RTE_ARCH_X86_64) && defined(RTE_MACHINE_CPUFLAG_SSE4_2)
#include <x86intrin.h>