summaryrefslogtreecommitdiff
path: root/examples/l3fwd-power/main.c
diff options
context:
space:
mode:
authorRadu Nicolau <radu.nicolau@intel.com>2018-06-11 11:03:23 +0100
committerThomas Monjalon <thomas@monjalon.net>2018-07-12 19:19:07 +0200
commitf88e7c175a68ed451d14c1bc379fef60fea07aff (patch)
tree43e024e65d9527a8b939c01980fbf90e4baec482 /examples/l3fwd-power/main.c
parent39e38d58307559d08c37495d589177350b8c8c6e (diff)
downloaddpdk-f88e7c175a68ed451d14c1bc379fef60fea07aff.zip
dpdk-f88e7c175a68ed451d14c1bc379fef60fea07aff.tar.gz
dpdk-f88e7c175a68ed451d14c1bc379fef60fea07aff.tar.xz
examples/l3fwd-power: add high/regular perf cores options
Added high/regular performance core pinning configuration options that can be used in place of the existing 'config' option. '--high-perf-cores CORELIST' option allow the user to specify a high performance cores list; if this option is not used and the 'perf-config' option is used, the application will query the system using the rte_power library in order to get a list of available high performance cores. The cores that are considered high performance are the cores that have turbo enabled. '--perf-config (port,queue,hi_perf,lcore_index)' option is similar to the existing config option, the cores are specified as indices for bins containing high or regular performance cores. Example: l3fwd-power -l 6,7 -- -p 0xff \ --high-perf-cores 6 --perf-config="(0,0,0,0),(1,0,1,0)" cores 6 and 7 are used, core 6 is specified as a high performance core. port 0 queue 0 will use a regular performance core, index 0 (core 7) port 1 queue 0 will use a high performance core, index 0 (core 6) Signed-off-by: Radu Nicolau <radu.nicolau@intel.com> Acked-by: David Hunt <david.hunt@intel.com>
Diffstat (limited to 'examples/l3fwd-power/main.c')
-rw-r--r--examples/l3fwd-power/main.c74
1 files changed, 57 insertions, 17 deletions
diff --git a/examples/l3fwd-power/main.c b/examples/l3fwd-power/main.c
index f6fabd9..d15cd52 100644
--- a/examples/l3fwd-power/main.c
+++ b/examples/l3fwd-power/main.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2010-2016 Intel Corporation
+ * Copyright(c) 2010-2018 Intel Corporation
*/
#include <stdio.h>
@@ -44,6 +44,9 @@
#include <rte_power.h>
#include <rte_spinlock.h>
+#include "perf_core.h"
+#include "main.h"
+
#define RTE_LOGTYPE_L3FWD_POWER RTE_LOGTYPE_USER1
#define MAX_PKT_BURST 32
@@ -155,14 +158,7 @@ struct lcore_rx_queue {
#define MAX_RX_QUEUE_INTERRUPT_PER_PORT 16
-#define MAX_LCORE_PARAMS 1024
-struct lcore_params {
- uint16_t port_id;
- uint8_t queue_id;
- uint8_t lcore_id;
-} __rte_cache_aligned;
-
-static struct lcore_params lcore_params_array[MAX_LCORE_PARAMS];
+struct lcore_params lcore_params_array[MAX_LCORE_PARAMS];
static struct lcore_params lcore_params_array_default[] = {
{0, 0, 2},
{0, 1, 2},
@@ -175,8 +171,8 @@ static struct lcore_params lcore_params_array_default[] = {
{3, 1, 3},
};
-static struct lcore_params * lcore_params = lcore_params_array_default;
-static uint16_t nb_lcore_params = sizeof(lcore_params_array_default) /
+struct lcore_params *lcore_params = lcore_params_array_default;
+uint16_t nb_lcore_params = sizeof(lcore_params_array_default) /
sizeof(lcore_params_array_default[0]);
static struct rte_eth_conf port_conf = {
@@ -1120,10 +1116,15 @@ print_usage(const char *prgname)
{
printf ("%s [EAL options] -- -p PORTMASK -P"
" [--config (port,queue,lcore)[,(port,queue,lcore]]"
+ " [--high-perf-cores CORELIST"
+ " [--perf-config (port,queue,hi_perf,lcore_index)[,(port,queue,hi_perf,lcore_index]]"
" [--enable-jumbo [--max-pkt-len PKTLEN]]\n"
" -p PORTMASK: hexadecimal bitmask of ports to configure\n"
" -P : enable promiscuous mode\n"
" --config (port,queue,lcore): rx queues configuration\n"
+ " --high-perf-cores CORELIST: list of high performance cores\n"
+ " --perf-config: similar as config, cores specified as indices"
+ " for bins containing high or regular performance cores\n"
" --no-numa: optional, disable numa awareness\n"
" --enable-jumbo: enable jumbo frame"
" which max packet len is PKTLEN in decimal (64-9600)\n"
@@ -1233,6 +1234,8 @@ parse_args(int argc, char **argv)
char *prgname = argv[0];
static struct option lgopts[] = {
{"config", 1, 0, 0},
+ {"perf-config", 1, 0, 0},
+ {"high-perf-cores", 1, 0, 0},
{"no-numa", 0, 0, 0},
{"enable-jumbo", 0, 0, 0},
{CMD_LINE_OPT_PARSE_PTYPE, 0, 0, 0},
@@ -1271,6 +1274,26 @@ parse_args(int argc, char **argv)
}
if (!strncmp(lgopts[option_index].name,
+ "perf-config", 11)) {
+ ret = parse_perf_config(optarg);
+ if (ret) {
+ printf("invalid perf-config\n");
+ print_usage(prgname);
+ return -1;
+ }
+ }
+
+ if (!strncmp(lgopts[option_index].name,
+ "high-perf-cores", 15)) {
+ ret = parse_perf_core_list(optarg);
+ if (ret) {
+ printf("invalid high-perf-cores\n");
+ print_usage(prgname);
+ return -1;
+ }
+ }
+
+ if (!strncmp(lgopts[option_index].name,
"no-numa", 7)) {
printf("numa is disabled \n");
numa_on = 0;
@@ -1608,6 +1631,23 @@ static int check_ptype(uint16_t portid)
}
+static int
+init_power_library(void)
+{
+ int ret = 0, lcore_id;
+ for (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {
+ if (rte_lcore_is_enabled(lcore_id)) {
+ /* init power management library */
+ ret = rte_power_init(lcore_id);
+ if (ret)
+ RTE_LOG(ERR, POWER,
+ "Library initialization failed on core %u\n",
+ lcore_id);
+ }
+ }
+ return ret;
+}
+
int
main(int argc, char **argv)
{
@@ -1642,6 +1682,12 @@ main(int argc, char **argv)
if (ret < 0)
rte_exit(EXIT_FAILURE, "Invalid L3FWD parameters\n");
+ if (init_power_library())
+ rte_exit(EXIT_FAILURE, "init_power_library failed\n");
+
+ if (update_lcore_params() < 0)
+ rte_exit(EXIT_FAILURE, "update_lcore_params failed\n");
+
if (check_lcore_params() < 0)
rte_exit(EXIT_FAILURE, "check_lcore_params failed\n");
@@ -1783,12 +1829,6 @@ main(int argc, char **argv)
if (rte_lcore_is_enabled(lcore_id) == 0)
continue;
- /* init power management library */
- ret = rte_power_init(lcore_id);
- if (ret)
- RTE_LOG(ERR, POWER,
- "Library initialization failed on core %u\n", lcore_id);
-
/* init timer structures for each enabled lcore */
rte_timer_init(&power_timers[lcore_id]);
hz = rte_get_timer_hz();