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authorBruce Richardson <bruce.richardson@intel.com>2017-03-29 16:21:17 +0100
committerThomas Monjalon <thomas.monjalon@6wind.com>2017-03-29 22:21:51 +0200
commitd9f0d3a1ffd4b66e75485cc8b63b9aedfbdfe8b0 (patch)
treed934575114c6ee487ad4fde130b1e80795a4d330 /config
parent05cc9fec458ca6fb316342246f4775591988088e (diff)
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ring: remove split cacheline build setting
Users compiling DPDK should not need to know or care about the arrangement of cachelines in the rte_ring structure. Therefore just remove the build option and set the structures to be always split. On platforms with 64B cachelines, for improved performance use 128B rather than 64B alignment since it stops the producer and consumer data being on adjacent cachelines. Signed-off-by: Bruce Richardson <bruce.richardson@intel.com> Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Acked-by: Olivier Matz <olivier.matz@6wind.com>
Diffstat (limited to 'config')
-rw-r--r--config/common_base1
1 files changed, 0 insertions, 1 deletions
diff --git a/config/common_base b/config/common_base
index 37aa1e1..c394651 100644
--- a/config/common_base
+++ b/config/common_base
@@ -453,7 +453,6 @@ CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO=y
#
CONFIG_RTE_LIBRTE_RING=y
CONFIG_RTE_LIBRTE_RING_DEBUG=n
-CONFIG_RTE_RING_SPLIT_PROD_CONS=n
CONFIG_RTE_RING_PAUSE_REP_COUNT=0
#