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authorShahaf Shuler <shahafs@mellanox.com>2017-07-28 17:28:31 +0300
committerThomas Monjalon <thomas@monjalon.net>2017-07-31 23:57:49 +0200
commite5e0878afcb390af9abacca377649a2137dc4bc2 (patch)
tree6cd0b1f6be263d1b5f893a69b2878ab8f9da5d89
parentec57ed08c992bf61d7a90fedf807dc38a511383d (diff)
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doc: update mlx5 supported features
Supported features which were not included: * ARMv8 * Extended stats Not supported features which were wrongly included: * Inner L3 checksum * Inner L4 checksum Signed-off-by: Shahaf Shuler <shahafs@mellanox.com> Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com> Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com> Acked-by: John McNamara <john.mcnamara@intel.com>
-rw-r--r--doc/guides/nics/features/mlx5.ini4
1 files changed, 2 insertions, 2 deletions
diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini
index e228c41..2913591 100644
--- a/doc/guides/nics/features/mlx5.ini
+++ b/doc/guides/nics/features/mlx5.ini
@@ -28,15 +28,15 @@ CRC offload = Y
VLAN offload = Y
L3 checksum offload = Y
L4 checksum offload = Y
-Inner L3 checksum = Y
-Inner L4 checksum = Y
Packet type parsing = Y
Rx descriptor status = Y
Tx descriptor status = Y
Basic stats = Y
+Extended stats = Y
Stats per queue = Y
Multiprocess aware = Y
Other kdrv = Y
+ARMv8 = Y
Power8 = Y
x86-32 = Y
x86-64 = Y