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authorAlejandro Lucero <alejandro.lucero@netronome.com>2017-11-08 12:28:11 +0000
committerFerruh Yigit <ferruh.yigit@intel.com>2017-11-10 09:31:24 +0000
commit1fdbf9b06a45d78f0f94b9c793847047070d6827 (patch)
tree093c07c5d045d1124b4bb828e4ed2b5a2694805f
parentf5cba91b095d54e8d7fcea57e515b5b4453b02ba (diff)
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net/nfp: fix possible bad shif operation
We do not know how big can the BAR be, but we know anything less than 1MB is an error. This BAR needs to be big enough for accessing most of NFP internals. Coverity issue: 195024 Fixes: d12206e00590 ("net/nfp: add NSP user space interface") Signed-off-by: Alejandro Lucero <alejandro.lucero@netronome.com>
-rw-r--r--drivers/net/nfp/nfp_nfpu.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/net/nfp/nfp_nfpu.c b/drivers/net/nfp/nfp_nfpu.c
index 5775d8d..f11afef 100644
--- a/drivers/net/nfp/nfp_nfpu.c
+++ b/drivers/net/nfp/nfp_nfpu.c
@@ -75,8 +75,13 @@ nfpu_open(struct rte_pci_device *pci_dev, nfpu_desc_t *desc, int nfp)
/* barsz in log2 */
while (barsz >>= 1)
i++;
+
barsz = i;
+ /* Sanity check: we can assume any bar size less than 1MB an error */
+ if (barsz < 20)
+ return -1;
+
/* Getting address for NFP expansion BAR registers */
cfg_base = pci_dev->mem_resource[0].addr;
cfg_base = (uint8_t *)cfg_base + NFP_CFG_EXP_BAR_CFG_BASE;