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authorJerin Jacob <jerin.jacob@caviumnetworks.com>2017-01-18 06:51:16 +0530
committerThomas Monjalon <thomas.monjalon@6wind.com>2017-01-18 16:57:11 +0100
commitdff90714b15c9f36d259c55c5c86dd054005eeb7 (patch)
tree4aba3a7c7a5897caa570959cced9bc909b21aafb
parente8025211711a08257c4731a69bb5624d7de6d7c6 (diff)
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eal/tile: define I/O device memory barriers
The patch does not provide any functional change for tile. I/O barriers are mapped to existing smp barriers. CC: Zhigang Lu <zlu@ezchip.com> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
-rw-r--r--lib/librte_eal/common/include/arch/tile/rte_atomic.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/librte_eal/common/include/arch/tile/rte_atomic.h b/lib/librte_eal/common/include/arch/tile/rte_atomic.h
index 28825ff..1f332ee 100644
--- a/lib/librte_eal/common/include/arch/tile/rte_atomic.h
+++ b/lib/librte_eal/common/include/arch/tile/rte_atomic.h
@@ -85,6 +85,12 @@ static inline void rte_rmb(void)
#define rte_smp_rmb() rte_compiler_barrier()
+#define rte_io_mb() rte_mb()
+
+#define rte_io_wmb() rte_compiler_barrier()
+
+#define rte_io_rmb() rte_compiler_barrier()
+
#ifdef __cplusplus
}
#endif