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authorJerin Jacob <jerin.jacob@caviumnetworks.com>2017-01-18 06:51:17 +0530
committerThomas Monjalon <thomas.monjalon@6wind.com>2017-01-18 16:57:11 +0100
commitda07a35be5c957b879ea0a28b49f1c10dca0cc82 (patch)
treee9864314efc57fd5824d1c00b879bb4798bc06bb
parentdff90714b15c9f36d259c55c5c86dd054005eeb7 (diff)
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eal/ppc64: define I/O device memory barriers
The patch does not provide any functional change for ppc_64. I/O barriers are mapped to existing smp barriers. CC: Chao Zhu <chaozhu@linux.vnet.ibm.com> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
-rw-r--r--lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
index fb4fccb..150810c 100644
--- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
@@ -87,6 +87,12 @@ extern "C" {
#define rte_smp_rmb() rte_rmb()
+#define rte_io_mb() rte_mb()
+
+#define rte_io_wmb() rte_wmb()
+
+#define rte_io_rmb() rte_rmb()
+
/*------------------------- 16 bit atomic operations -------------------------*/
/* To be compatible with Power7, use GCC built-in functions for 16 bit
* operations */