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authorJerin Jacob <jerin.jacob@caviumnetworks.com>2017-01-18 06:51:27 +0530
committerThomas Monjalon <thomas.monjalon@6wind.com>2017-01-18 17:18:26 +0100
commitb15740bd435c9131b61755f6114c5cb151ce8ff4 (patch)
tree90adf8f75df91076142fb92bf4e703a3d813efe3
parente783b81d44415c992ab5a990a3f4b56c04eb0b1b (diff)
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eal/arm64: change barrier definitions to macros
Change rte_*wb definitions to macros in order to keep consistent with other barrier definitions in the file. Suggested-by: Jianbo Liu <jianbo.liu@linaro.org> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
-rw-r--r--lib/librte_eal/common/include/arch/arm/rte_atomic_64.h36
1 files changed, 3 insertions, 33 deletions
diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
index ef0efc7..dc3a0f3 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
@@ -46,41 +46,11 @@ extern "C" {
#define dsb(opt) { asm volatile("dsb " #opt : : : "memory"); }
#define dmb(opt) { asm volatile("dmb " #opt : : : "memory"); }
-/**
- * General memory barrier.
- *
- * Guarantees that the LOAD and STORE operations generated before the
- * barrier occur before the LOAD and STORE operations generated after.
- * This function is architecture dependent.
- */
-static inline void rte_mb(void)
-{
- dsb(sy);
-}
+#define rte_mb() dsb(sy)
-/**
- * Write memory barrier.
- *
- * Guarantees that the STORE operations generated before the barrier
- * occur before the STORE operations generated after.
- * This function is architecture dependent.
- */
-static inline void rte_wmb(void)
-{
- dsb(st);
-}
+#define rte_wmb() dsb(st)
-/**
- * Read memory barrier.
- *
- * Guarantees that the LOAD operations generated before the barrier
- * occur before the LOAD operations generated after.
- * This function is architecture dependent.
- */
-static inline void rte_rmb(void)
-{
- dsb(ld);
-}
+#define rte_rmb() dsb(ld)
#define rte_smp_mb() dmb(ish)