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authorJerin Jacob <jerin.jacob@caviumnetworks.com>2017-01-18 06:51:20 +0530
committerThomas Monjalon <thomas.monjalon@6wind.com>2017-01-18 16:57:11 +0100
commit84733fd0d75e4943f7f798e868e18d7ef0ed41ea (patch)
tree32939458bb77bc7a3d0e2b71f79a6fbbf397b14b
parentb41508b7a4845f2ffd4a78ac2a7177b1dd5cc2d3 (diff)
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eal/arm64: fix memory barrier definition
dsb instruction based barrier is used for non smp version of memory barrier. Fixes: d708f01b7102 ("eal/arm: add atomic operations for ARMv8") Cc: stable@dpdk.org Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> Acked-by: Jianbo Liu <jianbo.liu@linaro.org>
-rw-r--r--lib/librte_eal/common/include/arch/arm/rte_atomic_64.h9
1 files changed, 5 insertions, 4 deletions
diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
index d854aac..bc7de64 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
@@ -43,7 +43,8 @@ extern "C" {
#include "generic/rte_atomic.h"
-#define dmb(opt) do { asm volatile("dmb " #opt : : : "memory"); } while (0)
+#define dsb(opt) { asm volatile("dsb " #opt : : : "memory"); }
+#define dmb(opt) { asm volatile("dmb " #opt : : : "memory"); }
/**
* General memory barrier.
@@ -54,7 +55,7 @@ extern "C" {
*/
static inline void rte_mb(void)
{
- dmb(ish);
+ dsb(sy);
}
/**
@@ -66,7 +67,7 @@ static inline void rte_mb(void)
*/
static inline void rte_wmb(void)
{
- dmb(ishst);
+ dsb(st);
}
/**
@@ -78,7 +79,7 @@ static inline void rte_wmb(void)
*/
static inline void rte_rmb(void)
{
- dmb(ishld);
+ dsb(ld);
}
#define rte_smp_mb() rte_mb()